For Tft (epo) Patents (Class 257/E29.151)
  • Patent number: 7196383
    Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: March 27, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, John W. Hartzell, Masahiro Adachi, Yoshi Ono
  • Publication number: 20070065993
    Abstract: A method of fabricating a flexible thin film transistor array substrate is provided. First, a rigid substrate is provided, and a polymer material layer is coated on the rigid substrate. Then, an insulating layer is coated over the polymer material layer by a spin coating process. The insulating layer covers the sides of the polymer material layer. Thereafter, a thin film transistor array is formed over the insulating layer. Then, the polymer material layer having the thin film transistor array is separated from the rigid substrate.
    Type: Application
    Filed: January 3, 2006
    Publication date: March 22, 2007
    Inventors: Te-chi Wong, Jian-Shu Wu, Horng-Long Tyan, Chyi-Ming Leu
  • Patent number: 7193280
    Abstract: One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2O3 film comprises: depositing an In film using a PVD process, typically with a power in the range of 200 to 300 watts; forming a film including In overlying a substrate material; simultaneously (with the formation of the In-including film) heating the substrate material, typically the substrate is heated to a temperature in the range of 20 to 200 degrees C.; following the formation of the In-including film, post-annealing, typically in an O2 atmosphere; and, in response to the post-annealing: forming an In2O3 film; and, controlling the resistivity in the In2O3 film. For example, the resistivity can be controlled in the range of 260 to 800 ohm-cm.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 20, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Sheng Teng Hsu
  • Patent number: 7193238
    Abstract: An image display device which includes a display pixel block and circuit blocks peripheral thereto. Each block has a circuit made of high-performance thin film transistors. The display pixel block and the peripheral circuit blocks including the four corners of the display device are formed on an image display device substrate of circuit-built-in type thin film transistors having a small circuit occupation surface area. A circuit including thin film transistors of a polycrystalline silicon film anisotropically crystal-grown and having crystal grains aligned in its longitudinal direction with a current direction is provided in the whole or partial surface of the display pixel block and circuit blocks. The longitudinal direction is aligned with a horizontal or vertical direction within the block, and blocks aligned in the horizontal and vertical directions can be arranged as mixed when viewed from an identical straight line.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: March 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takeo Shiba, Mutsuko Hatano, Shinya Yamaguchi, Seong-kee Park
  • Publication number: 20070059855
    Abstract: In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substrate, forming a common electrode on the substrate, forming a second metal layer on the substrate, etching the second metal layer to form a first electrode, a second electrode, a common line and a plurality of data lines on the substrate, and forming a pixel electrode overlapping the common electrode, wherein the gate lines intersect the data lines to form at least one enclosed area, the common electrode and the pixel electrode are positioned in the enclosed area, the first electrode is connected to the pixel electrode and the second electrode is connected to the data lines.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 15, 2007
    Applicant: HannStar Display Corp.
    Inventor: Po-Sheng Shih
  • Patent number: 7189995
    Abstract: The present invention relates to a thin film transistor for easily displaying gradation of an organic electroluminescence display device and a fabrication method of the thin film transistor, and an organic electroluminescence display device using the thin film transistor. The present invention provides an organic electroluminescence display device comprising a thin film transistor; a protection film and an organic light-emitting device electrically connected to the thin film transistor, wherein an S-factor of the thin film transistor is 0.35 V/dec or more.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: March 13, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Bon Koo, Sang-Il Park
  • Patent number: 7189603
    Abstract: A semiconductor layer with a threshold voltage for n-channel is formed and patterned to TFT island areas. A gate insulating film is deposited. The first gate electrode layer is fomed and pattered to form an opening. Phosphorous ions are implanted into a p-channel TFT in the opening to set threshold voltage for p-channel TFT. A second gate electrode layer is formed and patterned to form second gate electrodes. By using the first gate electrode layer as a mask, boron ions are implanted at a high concentration to form source/drain regions of the p-channel TFT. By using the second gate electrodes as a mask, the first gate electrode layer is etched to form gate electrodes. Phosphorous ions are implanted at a low concentration to form LDD regions. By using a fourth mask, P ions are implanted at a high concentration to form source/drain regions of n-channel TFTs.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: March 13, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20070051993
    Abstract: A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to form a poly silicon layer. Next, the first insulating layer and the poly silicon layer are patterned to form an island. Then, a gate electrode is formed on the island. Finally, a source region and a drain region are formed inside the poly silicon layer of the island. After the annealing process is performed, the boundary between the poly silicon layer and the gate insulating layer becomes denser, so that the current leakage of the thin film transistor can be reduced.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Ming-Che Ho, Yun-Pei Yang, Po-Chih Liu, Chia-Chien Lu
  • Patent number: 7179694
    Abstract: A method of manufacturing a semiconductor device includes an origin part forming process in order to form a plurality of origin parts, each of which serves as an origin for crystallization of a semiconductor film on a substrate, a semiconductor film forming process to form the semiconductor film on the substrate where the origin parts have been formed, and a thermal treatment process in which the semiconductor film is thermally treated in order to form a plurality of nearly single crystalline grains, each of which is almost centered at each of the plurality of origin parts.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: February 20, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Yasushi Hiroshima
  • Patent number: 7176535
    Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: February 13, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Gee-Sung Chae
  • Patent number: 7176488
    Abstract: In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which seals the semiconductor chip. Durability of the thin film semiconductor device against stress due to bending of the substrate is improved by using the protective cap.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-young Kim, Wan-jun Park, Young-soo Park, June-key Lee, Yo-sep Min, Jang-yeon Kwon, Sun-ae Seo, Young-min Choi, Soo-doo Chae
  • Patent number: 7172929
    Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: February 6, 2007
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Patent number: 7166499
    Abstract: A method for making a thin film transistor, TFT, (306) on a substrate includes a photolithographic process step of patterning three layers of materials to form a TFT (306) and to form a bridging structure (308) crossing over a TFT gate bus-line conductor (202) at a cross over region; followed by patterning a conductor metal to form a TFT source electrode terminal (404) and a TFT drain electrode terminal (402), and to comprise a continuous data bus-line (206) extending over the bridging structure (308).
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: January 23, 2007
    Assignee: AU Optronics Corporation
    Inventor: Chih-Hung Shih
  • Patent number: 7161176
    Abstract: There is provided an active matrix type display device in which the display device is formed of a driver circuit with an insulated gate FET capable of operating at high speed, and even if an area of a pixel electrode per unit pixel is made small, sufficient storage capacitance can be obtained. In a semiconductor device comprising an active matrix circuit with an insulated gate field effect transistor having at least an active layer made of single crystalline semiconductor, an organic resin insulating layer is formed over the insulated gate field effect transistor, a storage capacitance is formed of a light shielding layer formed over the organic resin insulating layer, a dielectric layer formed to be in close contact with the light shielding layer, and a light reflecting electrode connected to the insulated gate field effect transistor.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: January 9, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Yasuyuki Arai
  • Patent number: 7161177
    Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: January 9, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Koji Ono, Toru Takayama, Tatsuya Arao, Shunpei Yamazaki
  • Patent number: 7145209
    Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: December 5, 2006
    Assignee: TPO Displays Corp.
    Inventors: Shih-Chang Chang, De-Hua Deng, Chun-Hsiang Fang, Yaw-Ming Tsai
  • Patent number: 7122832
    Abstract: An EL element and an interface between a channel and an impurity diffusion area of a thin film transistor provided in the vicinity of the EL element are spaced apart. A light shielding film is provided between the EL element and the interface. By providing such a space and/or the light shielding film, generation of a leak current, which would otherwise be caused by light emitted from the self-emissive EL element entering the TFT, is reliably prevented, thereby ensuring that emitted light is not brighter than a predetermined luminance.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: October 17, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Ryuji Nishikawa
  • Patent number: 7122831
    Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: October 17, 2006
    Assignee: TPO Displays Corp.
    Inventor: Naoki Sumi
  • Patent number: 7109108
    Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon. A high performance TFT can be realized.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: September 19, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Publication number: 20060157787
    Abstract: A thin film transistor (TFT) that can prevent damage to a silicon layer under a gate electrode in an annealing process by using a first gate electrode having high thermal resistance and a second gate electrode having high reflectance and a method of manufacturing the TFT are provided. The method of manufacturing a TFT includes forming a double-layered gate electrode which includes a first gate electrode formed of a material having high thermal resistance and a second gate electrode formed of a metal having high optical reflectance on the first gate electrode, and forming a source and a drain by annealing doped regions on both sides of a silicon layer under the gate electrode by radiating a laser beam onto the entire upper surface of the silicon layer.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 20, 2006
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hans Cho, Hyuck Lim, Takashi Noguchi, Jang-yeon Kwon
  • Patent number: 6890784
    Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 10, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroshi Shibata, Takeshi Fukunaga