Quantum Effect Device (epo) Patents (Class 257/E29.168)
  • Patent number: 9040958
    Abstract: Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-seung Lee, Yong-sung Kim, Joo-ho Lee, Yong-seok Jung
  • Patent number: 9024415
    Abstract: An electrical device includes a current transport layer formed using a layer of a topological material selected from the group of a topological insulator, a quantum anomalous hall (QAH) insulator, a topological insulator variant, and a topological magnetic insulator. In one embodiment, the current transport layer forms a conductive wire on an integrated circuit where the conductive wire includes two spatially separated edge channels, each edge channel carrying charge carriers propagating in one direction only. In other embodiments, an optical device includes an optical layer formed using a layer of the topological material. The optical layer can be a light absorbing layer, a light emitting layer, a light transport layer, or a light modulation layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Shoucheng Zhang, Xiao Zhang
  • Patent number: 9018082
    Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 28, 2015
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 8963215
    Abstract: A mechanism is provided for base recognition of an integrated transistor and nanochannel. A target molecule is forced down to a carbon nanotube a single base at a time in the nanochannel by applying a gate voltage to a top electrode, and/or a narrow thickness of the nanochannel. The nanochannel exposes an exposed portion of the carbon nanotube at a bottom wall, and the top electrode is positioned over the exposed portion. The exposed portion of the carbon nanotube is smaller than the distance between bases to only accommodate the single base at a time. The target molecule is stretched by the narrow thickness and by applying a traverse voltage across a length direction of the nanochannel. The target molecule is frictionally restricted by the narrow thickness of the nanochannel to stretch is restrictedly translocates in the length direction. Current is measured to determine an identity of the single base.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Gustavo A. Stolovitzky, Deqiang Wang
  • Patent number: 8946679
    Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventor: Ravi Pillarisetty
  • Patent number: 8933463
    Abstract: A semiconductor element including an MISFET exhibits diode characteristics in a reverse direction through an epitaxial channel layer. The semiconductor element includes: a silicon carbide semiconductor substrate of a first conductivity type, semiconductor layer of the first conductivity type, body region of a second conductivity type, source region of the first conductivity type, epitaxial channel layer in contact with the body region, source electrode, gate insulating film, gate electrode and drain electrode. If the voltage applied to the gate electrode is smaller than a threshold voltage, the semiconductor element functions as a diode wherein current flows from the source electrode to the drain electrode through the epitaxial channel layer. The absolute value of the turn-on voltage of this diode is smaller than the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kazuhiro Adachi, Osamu Kusumoto, Masao Uchida, Koichi Hashimoto, Shun Kazama
  • Patent number: 8872360
    Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jerry M. Chow, Jay M. Gambetta, Seth T. Merkel, Chad T. Rigetti, Matthias Steffen
  • Patent number: 8866126
    Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 21, 2014
    Assignee: The Regents of the University of California
    Inventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
  • Patent number: 8853061
    Abstract: A method for forming a graphite-based device on a substrate having a plurality of zones is provided where the substrate is carbon doped in zones. Each such zone comprises a plurality of dopant profiles. One or more graphene stacks are generated in the doped zones. A graphene stack so generated comprises a non-planar graphene layer characterized by a bending angle, curvature, characteristic dimension, graphene orientation, graphene type, or combinations thereof. A method for forming a graphite-based device on a substrate is provided, the substrate comprising a graphene foundation material and a plurality of zones. The substrate is patterned to form features in the zones. One feature comprises a non-planar surface or at least two adjacent surfaces that are not coplanar. One or more graphene stacks are concurrently generated, at least one of which comprises a non-planar graphene layer overlaying the non-planar surface or the at least two adjacent surfaces.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: October 7, 2014
    Assignee: Solan, LLC
    Inventor: Mark Alan Davis
  • Patent number: 8853672
    Abstract: A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 ?m. A relationship of (H?L)/H×100?80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 7, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventor: Shunsuke Yamamoto
  • Patent number: 8835285
    Abstract: The present invention relates to growth of vertically-oriented crystalline nanowire arrays upon a transparent conductive or other substrate for use in 3rd generation photovoltaic and other applications. A method of growing crystalline anatase nanowires includes the steps of: deposition of titania onto a substrate; conversion of the titania into titanate nanowires; and, treatment of the titanate nanowires to produce crystalline anatase nanowires.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Flux Photon Corporation
    Inventors: Craig A. Grimes, Xinjian Feng, Kevin E. Kreisler
  • Patent number: 8816325
    Abstract: A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 26, 2014
    Assignee: The Regents of the University of California
    Inventors: Thomas Schenkel, Cheuk Chi Lo, Christoph Weis, Stephen Lyon, Alexei Tyryshkin, Jeffrey Bokor
  • Patent number: 8816479
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 26, 2014
    Assignees: National Research Council of Canada, The Governors of The University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 8803131
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8796668
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8704210
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 22, 2014
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Patent number: 8698129
    Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 15, 2014
    Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Geert Hellings, Geert Eneman
  • Patent number: 8629427
    Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: January 14, 2014
    Assignee: Texas A&M University
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
  • Patent number: 8592820
    Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group(—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 26, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Hyun Kim, Bo-Hyun Lee, Tae-Hyoung Moon
  • Patent number: 8581233
    Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Christoph Wasshuber
  • Patent number: 8581227
    Abstract: A computer-implemented method for encryption and decryption using quantum computational model is disclosed. Such a method includes providing a model of a lattice having a system of non-abelian anyons disposed thereon. From the lattice model, a first quantum state associated with the lattice is determined. Movement of non-abelian anyons within the lattice is modeled to model formation of first and second quantum braids in the space-time of the lattice. The first quantum braid corresponds to first text. The second quantum braid corresponds to second text. A second quantum state associated with the lattice is determined from the lattice model after formation of the first and second quantum braids has been modeled. The second quantum state corresponds to second text that is different from the first text.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 12, 2013
    Assignee: Microsoft Corporation
    Inventors: Michael Freedman, Chetan Nayak, Kirill Shtengel
  • Patent number: 8575591
    Abstract: An apparatus applies a carrier fluid to a semiconductor substrate. The carrier fluid carries nanoparticles. The positions of a plurality of particles in the carrier fluid are manipulated by applying an electric field, removing the carrier fluid from the substrate so as to leave the nanoparticles on the substrate, and sintering the nanoparticles to form a region.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: November 5, 2013
    Assignee: Nokia Corporation
    Inventors: Petri Juhani Korpi, Risto Johannes Johannes Rönkkä
  • Patent number: 8569740
    Abstract: Growth of thermoelectric materials in the form of quantum well superlattices on three-dimensionally structured substrates provide the means to achieve high conversion efficiency of the thermoelectric module combined with inexpensiveness of fabrication and compatibility with large scale production. Thermoelectric devices utilizing thermoelectric materials in the form of quantum well semiconductor superlattices grown on three-dimensionally structured substrates provide improved thermoelectric characteristics that can be used for power generation, cooling and other applications.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: October 29, 2013
    Assignee: MicroXact Inc.
    Inventor: Vladimir Kochergin
  • Patent number: 8507892
    Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8481991
    Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 9, 2013
    Assignee: The Regents of the University of California
    Inventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
  • Patent number: 8455861
    Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8450198
    Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Publication number: 20130100978
    Abstract: An (Al,In,B,Ga)N based device including a plurality of (Al,In,B,Ga)N layers overlying a semi-polar or non-polar GaN substrate, wherein the (Al,In,B,Ga)N layers include at least a defected layer, a blocking layer, and an active region, the blocking layer is between the active region and the defected layer of the device, and the blocking layer has a larger band gap than surrounding layers to prevent carriers from escaping the active region to the defected layer. One or more (AlInGaN) device layers are above and/or below the (Al,In,B,Ga)N layers. Also described is a nonpolar or semipolar (Al,In,B,Ga)N based optoelectronic device including at least an active region, wherein stress relaxation (Misfit Dislocation formation) is at heterointerfaces above and/or below the active region.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 25, 2013
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: The Regents of the University of California
  • Patent number: 8421060
    Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 16, 2013
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku
  • Patent number: 8399334
    Abstract: A method of manufacturing a nano device by directly printing a plurality of NW devices in a desired shape on a predesigned gate substrate. The method includes preparing an NW solution, preparing a building block for performing decaling onto the substrate by carrying an NW device, forming the NW device by connecting electrodes of each of building block units of the building block using NWs by dropping the NW solution between the electrodes and then through dielectrophoresis, visually inspecting the numbers of NW bridges that are formed between the electrodes of each of the building block units through the dielectrophoresis, grouping the building block units according to the numbers, and decaling the NW device formed on each of the building block units onto the gate substrate by bringing the grouped building block units into contact with the predesigned gate substrate and then detaching the grouped building block units.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: March 19, 2013
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Jae Min Myoung, Hong Koo Baik, Tae Il Lee
  • Publication number: 20130056705
    Abstract: A method of manufacturing a quantum dot layer, and a quantum dot optoelectronic device including the quantum dot layer. The method includes sequentially stacking a self-assembled monolayer, a sacrificial layer, and a quantum dot layer on a source substrate; disposing a stamp on the quantum dot layer; picking up the sacrificial layer, the quantum dot layer and the stamp; and removing the sacrificial layer from the quantum dot layer using a solution that dissolves the sacrificial layer.
    Type: Application
    Filed: May 29, 2012
    Publication date: March 7, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-ho KIM, Kyung-sang CHO, Dae-young CHUNG, Byoung-lyong CHOI
  • Publication number: 20130048952
    Abstract: An article includes a layer of graphene having a first work function; and a metal oxide film disposed on the layer of graphene, the metal oxide film having a second work function greater than the first work function. Electrons are transferred from the layer of graphene to the metal oxide film, forming a hole accumulation layer in the layer of graphene.
    Type: Application
    Filed: May 5, 2011
    Publication date: February 28, 2013
    Applicant: National University of Singapore
    Inventors: Wei Chen, Zhenyu Chen, Thye Shen Andrew Wee, Lanfei Xie, Xiao Wang, Jiatao Sun, Ariando
  • Publication number: 20130048947
    Abstract: The present invention relates to growth of vertically-oriented crystalline nanowire arrays upon a transparent conductive or other substrate for use in 3rd generation photovoltaic and other applications. A method of growing crystalline anatase nanowires includes the steps of: deposition of titania onto a substrate; conversion of the titania into titanate nanowires; and, treatment of the titanate nanowires to produce crystalline anatase nanowires.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 28, 2013
    Inventors: Craig A. Grimes, Xinjian Feng, Kevin E. Kreisler
  • Patent number: 8384122
    Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: February 26, 2013
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Anupama Bowonder, Pratik Patel, Daniel Chou, Prashant Majhi
  • Patent number: 8373153
    Abstract: Implementations of quantum well photodetectors are provided. In one embodiment, a quantum structure includes a first barrier layer, a well layer located on the first barrier layer, and a second barrier layer located on the well layer. A metal layer is located adjacent to the quantum structure.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: February 12, 2013
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8368052
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Publication number: 20130022072
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of III-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.
    Type: Application
    Filed: January 27, 2012
    Publication date: January 24, 2013
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: John Edward Bowers
  • Patent number: 8357921
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: January 22, 2013
    Assignee: Nantero Inc.
    Inventor: Claude L. Bertin
  • Patent number: 8354662
    Abstract: The invention relates to semiconducting nanoparticles. The nanoparticles of the invention comprise a single element or a compound of elements in one or more of groups II, III, IV, V, VI. The nanoparticles have a size in the range of 1 nm to 500 nm, and comprise from 0.1 to 20 atomic percent of oxygen or hydrogen. The nanoparticles are typically formed by comminution of bulk high purity silicon. One application of the nanoparticles is in the preparation of inks which can be used to define active layers or structures of semiconductor devices by simple printing methods.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: January 15, 2013
    Assignee: PST Sensors, Ltd.
    Inventors: David Thomas Britton, Margit Härting
  • Patent number: 8350252
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 8, 2013
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Publication number: 20130001519
    Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Zhihong Chen, Aaron Daniel Franklin, Shu-Jen Han
  • Patent number: 8344367
    Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Kim, Dong-Gun Park, Sung-Young Lee, Yang-Kyu Choi, Lee-Eun Yu
  • Patent number: 8344357
    Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: January 1, 2013
    Assignee: Sony Corporation
    Inventor: Toshiyuki Kobayashi
  • Publication number: 20120326129
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Publication number: 20120319082
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Application
    Filed: December 1, 2011
    Publication date: December 20, 2012
    Applicant: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 8319205
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: November 27, 2012
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, H. M. Manning
  • Publication number: 20120292590
    Abstract: An optical component comprising an emitter and a solid reflector, said reflector having a convex outer surface, said emitter being located within the solid reflector, the emitter being configured to emit radiation via an electric dipole transition, the dipole having a dipole axis being orientated at an angle of 45 degrees or less to the surface normal at the apex of the reflector.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Anthony John BENNETT, Andrew James SHIELDS, Joanna Krystyna SKIBA-SZYMANSKA
  • Publication number: 20120286235
    Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: International Business Machines Corporation
    Inventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20120273763
    Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Bhagawan R. Sahu, Priyamvada Jadaun, Jiwon Chang
  • Publication number: 20120267608
    Abstract: A functional device and functional system are provided. A functional device is formed by coupling a first structure formed by local interaction and a second structure formed according to a predetermined global rule via a third structure having an anisotropic configuration.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: Fujifilm Corporation
    Inventor: Akira Ishibashi