Abstract: A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.

Abstract: A functional device and functional system are provided. A functional device is formed by coupling a first structure formed by local interaction and a second structure formed according to a predetermined global rule via a third structure having an anisotropic configuration.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to a

Abstract: The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process.

Abstract: The present disclosure provides a single-quantum dot device and a method of manufacturing the same. A transparent dielectric thin film is formed on a cover layer and an energy band of quantum dots is adjusted based on compressive stress due to difference in coefficient of thermal expansion therebetween. Specifically, the dielectric thin film has a lower coefficient of thermal expansion than the cover layer and compressive stress is applied to the cover layer by radiation of laser beams. Then, the quantum dots undergo compressive stress and the energy band of the quantum dots increases with increasing intensity of the laser beams.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A switching device includes: a first layer including a carbon material having a six-member ring network structure; a first electrode electrically connected to a first portion of the first layer; a second electrode electrically connected to a second portion of the first layer and provided apart from the first electrode; a third electrode including a fourth portion provided opposing a third portion between the first portion and the second portion of the first layer; and a second layer provided between the third portion of the first layer and the fourth portion of the third electrode. The second layer includes: a base portion; and a functional group portion. The functional group portion is provided between the base portion and the first layer. The functional group portion is bonded to the base portion. A ratio of sp2-bonded carbon and sp3-bonded carbon of the first layer is changeable by a voltage applied between the first layer and the third electrode.

Abstract: A nanoconverter or nanosensor is disclosed capable of directly generating electricity through physisorption interactions with molecules that are dipole containing organic species in a molecule interaction zone. High surface-to-volume ratio semiconductor nanowires or nanotubes (such as ZnO, silicon, carbon, etc.) are grown either aligned or randomly-aligned on a substrate. Epoxy or other nonconductive polymers are used to seal portions of the nanowires or nanotubes to create molecule noninteraction zones. By correlating certain molecule species to voltages generated, a nanosensor may quickly identify which species is detected. Nanoconverters in a series parallel arrangement may be constructed in planar, stacked, or rolled arrays to supply power to nano- and micro-devices without use of external batteries. In some cases breath, from human or other life forms, contain sufficient molecules to power a nanoconverter.

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: Silicon, silicon-germanium alloy, and germanium nanowire optoelectronic devices and methods for fabricating the same are provided. According to one embodiment, a P-I-N device is provided that includes a parallel array of intrinsic silicon, silicon-germanium or germanium nanowires located between a p+ contact and an n+ contact. In certain embodiments, the intrinsic silicon and germanium nanowires can be fabricated with diameters of less than 4.9 nm and 19 nm, respectively. In a further embodiment, vertically stacked silicon, silicon-germanium and germanium nanowires can be formed.

Abstract: A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: One, several or very many parallel quantum wires, e.g. especially 1-dimensional quantum-conducting heavy ion tracks—“true” quantum wires at room temperature—see similarly EP1096569A1 [1] and [2], or also perhaps SWCNTs, vertically directed or also slightly tilted—up to about 45 degrees—arranged in a 2 dimensional plane, which as a 2-dimensional array interconnect the source and drain contacts of the here invented transistor, are modulated with respect to their quantum-mechanical conductivity via the strength of an applied electric or magnetic field [3], which is homogenous or variable in space locally across the 2 dimensional quantum wire array. The I-V curves of such quantum wires are measured via a double resonant tunnelling effect which allows identifying quantum effects at room temperature. A “true” quantum wire is characterized by quantized current steps and sharp current peaks in the I-V (Isd versus Usd, not just Is a versus Ugate) curve.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: An electronic device using quantum dots, which comprises a ferromagnetic micro magnet and performs individual ESR control on each multi-quantum bit in a power saving way. The electronic device comprising the ferromagnetic micro magnet (10) disposed in the vicinity of the quantum dots (8, 9) of a plurality of aligned semiconductor quantum dots, wherein a strong magnetic field is applied so as to induce electron spin resonance (ESR), and the layout of the ferromagnetic micro magnet (10) is changed, thereby controlling the resonance frequency of the quantum dots (8, 9). Under the condition where the resonance frequency of each quantum dot (8, 9) is controlled, swapping of the electron spins in the quantum dots (8, 9) is performed, thereby creating a quantum bit (QUBIT) required for quantum calculation.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein.

Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.

Abstract: In a method of making a monolithic elongated nanowire, a mask polymer layer is applied to a selected crystal surface of a seed crystal. A plurality of spaced apart elongated openings is defined through the mask polymer layer, thereby exposing a corresponding plurality of portions of the crystal surface. The openings are disposed so as to be aligned with and parallel to a selected crystal axis of the seed crystal. The portions of the crystal surface are subjected to a chemical nutrient environment that causes crystalline material to grow from the plurality of portions for at least a period of time so that monocrystalline members grow from the elongated openings and until the monocrystalline members laterally expand so that each monocrystalline member grows into and merges with an adjacent one of the monocrystalline members, thereby forming a monolithic elongated nanowire.

Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: Precision quantum dot clusters and methods for producing and tuning quantum dot clusters are described herein. Also described herein are materials and devices, including photovoltaic devices, that may include one or more quantum dot clusters.

Abstract: A gain medium and an interband cascade laser, having the gain medium are presented. The gain medium can have one or both of the following features: (1) the thicknesses of the one or more hole quantum wells in the hole injector region are reduced commensurate with the thickness of the active hole quantum well in the active quantum well region, so as to place the valence band maximum in the hole injector region at least about 100 meV lower than the valence band maximum in the active hole quantum well; and (2) the thickness of the last well of the electron injector region is between 85 and 110% of the thickness of the first active electron quantum well in the active gain region of the next stage of the medium. A laser incorporating a gain medium in accordance with the present invention can emit in the mid-IR range from about 2.5 to 8 ?m at high temperatures with room-temperature continuous wave operation to wavelengths of at least 4.

Abstract: One embodiment of the invention includes a quantum system. The system includes a superconducting qubit that is controlled by a control parameter to manipulate a photon for performing quantum operations. The system also includes a quantum resonator system coupled to the superconducting qubit and which includes a first resonator and a second resonator having approximately equal resonator frequencies. The quantum resonator system can represent a first quantum logic state based on a first physical quantum state of the first and second resonators with respect to storage of the photon and a second quantum logic state based on a second physical quantum state of the first and second resonators with respect to storage of the photon.

Abstract: The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer.

Abstract: A nanowire device includes a nanowire 40 having differently functionalized segments 50, 51. Each of the segments 50, 51 is configured to interact with a species A, B to modulate the conductance of a segment 50, 51. The nanowire 40 is grown from a single catalyst 401 and the segments 50, 51 include a first segment 50 at a non-linear angle from a second segment 51.

Abstract: Photoelectrochemical solar cells (PECs) consisting of a photoanode were prepared by direct deposition of independently synthesized CdSe nanocrystal quantum dots (NQDs) onto a nanocrystalline TiO2 film (NQD/TiO2), aqueous Na2S or Li2S electrolyte and a Pt counter electrode. The light harvesting efficiency (LHE) of the NQD/TiO2 photoanode is significantly enhanced when the NQD surface passivation is changed from tri-n-octylphosphine oxide (TOPO) to a smaller ligand (e.g. n-butylamine (BA)). Using NQDs with a shorter passivating ligand, BA, leads to a significant enhancement in both the electron injection efficiency at the NQD/TiO2 interface and charge collection efficiency at the NQD/electrolyte interface, with the latter attributed mostly to a more efficient diffusion of the electrolyte through the pores of the photoanode.

Abstract: A spin bus quantum computing architecture includes a spin bus formed of multiple strongly coupled and always on qubits that define a string of spin qubits. A plurality of information bearing qubits are disposed adjacent a qubit of the spin bus. Electrodes are formed to the information bearing qubits and the spin bus qubits to allow control of the establishment and breaking of coupling between qubits to allow control of the establishment and breaking of coupling between each information bearing qubit and the spin bus qubit adjacent to it. The spin bus architecture allows rapid and reliable long-range coupling of qubits.

Abstract: An optoelectronic device is disclosed which includes a quantum dot layer including plurality of quantum dots which do not have capping layers. This optoelectronic device may be a quantum dot light-emitting device, which includes (1) a substrate which is transparent or translucent, (2) an anode electrical conducting layer which is transparent or translucent, and is located adjacent to the substrate, (3) a planarizing/hole injection layer which is located adjacent to the anode electrical conducting layer, (4) a quantum dot layer including the plurality of quantum dots which do not have capping layers, and (5) a cathode electrical conducting layer which is located adjacent to the quantum dot layer.

Abstract: A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages.

Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: A microwave circuit includes at least one inductive portion and at least one capacitive portion and having a resonance frequency, the microwave circuit including a material which acts as a dielectric for the capacitive portion, characterized in that the material acting as a dielectric includes an active region that is an electrically pumped semiconductor heterostructure having at least two energy levels whose energy separation is close to the resonance frequency of the microwave circuit.

Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.

Abstract: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.

Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: Sensor are generally provided that include a layer of silicon oxide on a portion of a n+ layer to form an uneven surface where the layer of silicon oxide defines a thicker region than an exposed portion of the n+ layer. First and second metal contacts can be on the layer of silicon oxide, with first and second nanowires extending respectively from a first base on the first metal contact and a second base on the second metal contact. The first nanowire and the second nanowire are connected together at an apex to form a v-shaped nanocantilever, wherein the apex is positioned over the exposed n+ layer, and wherein the nanowires comprise indium and nitrogen. Methods of fabricating such sensors, along with methods of their use, are also generally provided.

Abstract: A method for forming graphene includes introducing a substrate and a carbon-containing reactant source into a chamber, and radiating a laser beam onto the substrate to decompose the carbon-containing reactant source and form graphene over the substrate using carbon atoms generated by decomposition of the carbon-containing reactant source. A carbon-containing gas (methane) decomposes upon radiation of a laser beam. The carbon-containing gas has a decomposition rate on the order of femtoseconds and the laser beam has a pulse on the order of nanoseconds or more. The graphene is grown in a single layer along the surface of the substrate. Then, the graphene is selectively patterned using a laser beam to form a desired pattern.

Abstract: This invention provides a self supporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. The n-type conductive aluminum nitride semiconductor crystal, by which the self supporting substrate is made up, contains Si atom at a concentration of 1×1018 to 5×1020 cm?3 is substantially free of halogen atoms and substantially does not absorb the light having the energy of not more than 5.9 eV. The self supporting substrate can be obtained by a method comprising the steps of forming an AlN crystal layer on a single crystal substrate such as a sapphire by the HVPE method, preheating the obtained substrate having the AlN crystal layer to a temperature of 1,200° C. or more, forming a second layer consisting of the n-type conductive aluminum nitride semiconductor crystal is formed on the AlN crystal layer in high rate by the HVPE method and separating the second layer from the obtained laminate.

Abstract: Semiconductor structures and laser devices including the semiconductor structures are provided. The semiconductor structures have a quantum cascade laser (QCL) structure including an electron injector, an active region, and an electron extractor. The active region of the semiconductor structures includes a configuration of quantum wells and barriers that virtually suppresses electron leakage, thereby providing laser devices including such structures with superior electro-optical characteristics.

Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Abstract: A flexible electronic device is made up of nanostructures. Specifically, the device includes a flexible substrate, a film of nanostructures in contact with the flexible substrate, a first conducting element in contact with the film of nanostructures, and a second conducting element in contact with the film of nanostructures. The nanostructures may comprise nanotubes, such as carbon nanotubes disposed along the flexible substrate, such as an organic or polymer substrate. The first and second conductive elements may serve as electrical terminals, or as a source and drain. In addition, the electronic device may include a gate electrode that is in proximity to the nanotubes and not in electrical contact with the nanotubes. In this configuration, the device can operate as a transistor or a FET. The device may also be operated in a resistive mode as a chemical sensor (e.g., for sensing NH3).

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO2 mask into stripes oriented in the gallium nitride <1 100> or <11 20> direction; (3) growing epitaxial lateral overgrowth of (ELO) gallium nitride layers by controlling the facet planes via choosing the growth temperature and the reactor; (4) depositing zinc oxide films on facets ELO gallium nitride templates by chemical vapor deposition (CVD). Zinc oxide crystal of high quality with a reduced number of crystal defects can be grown on a gallium nitride template. This method can be used to fabricate zinc oxide films with low dislocation density lower than 104/cm?2, which will find important applications in future electronic and optoelectronic devices.