Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.

Abstract: Amongst the candidates for very high efficiency solid state lights sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects. Further manufacturing requirements demand reproducible nanowire diameter, length etc to allow these nanowires to be embedded within device structures. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group III—nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. The technique also allows for unique dot-within-a-dot nanowire structures.

Abstract: A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.

Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.

Abstract: A group III nitride semiconductor optical device 11a has a group III nitride semiconductor substrate 13 having a main surface 13a forming a finite angle with a reference plane Sc orthogonal to a reference axis Cx extending in a c-axis direction of the group III nitride semiconductor and an active layer 17 of a quantum-well structure, disposed on the main surface 13a of the group III nitride semiconductor substrate 13, including a well layer 28 made of a group III nitride semiconductor and a plurality of barrier layers 29 made of a group III nitride semiconductor. The main surface 13a exhibits semipolarity. The active layer 17 has an oxygen content of at least 1×1017 cm?3 but not exceeding 8×1017 cm?3. The plurality of barrier layers 29 contain an n-type impurity other than oxygen by at least 1×1017 cm?3 but not exceeding 1×1019 cm?3 in an upper near-interface area 29u in contact with a lower interface 28Sd of the well layer 28 on the group III nitride semiconductor substrate side.

Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.

Abstract: A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer.

Abstract: Method for producing a nanoparticle comprised of core, first shell and second shell semiconductor materials. Effecting conversion of a core precursor composition comprising separate first and second precursor species to the core material and then depositing said first and second shells. The conversion is effected in the presence of a molecular cluster compound under conditions permitting seeding and growth of the nanoparticle core. Core/multishell nanoparticles in which at least two of the core, first shell and second shell materials incorporate ions from groups 12 and 15, 14 and 16, or 11, 13 and 16 of the periodic table. Core/multishell nanoparticles in which the second shell material incorporates at least two different group 12 ions and group 16 ions. Core/multishell nanoparticles in which at least one of the core, first and second semiconductor materials incorporates group 11, 13 and 16 ions and the other semiconductor material does not incorporate group 11, 13 and 16 ions.

Abstract: Provided are an electronic device and a light-receiving and light-emitting device which can control the electron configuration of a graphene sheet and the band gap thereof, and an electronic integrated circuit and an optical integrated circuit which use the devices. By shaping the graphene sheet into a curve, the electron configuration thereof is controlled. The graphene sheet can be shaped into a curve by forming the sheet on a base film having a convex structure or a concave structure. The local electron states in the curved part can be formed by bending the graphene sheet. Thus, the same electron states as the cylinder or cap part of a nanotube can be realized, and the band gaps at the K points in the reciprocal lattice space can be formed.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

Abstract: A semiconductor device includes a substrate comprising a first surface having a first orientation and a second surface having a second orientation and a plurality of III-V nitride layers on the substrate, wherein the plurality of III-V nitride layers are configured to emit light when an electric current is produced in one or more of the plurality of III-V nitride layers.

Abstract: A transistor includes at least three terminals comprising a gate electrode, a source electrode and a drain electrode, an insulating layer disposed on a substrate, and a semiconductor layer disposed on the substrate, wherein a current which flows between the source electrode and the drain electrode is controlled by application of a voltage to the gate electrode, where the semiconductor layer includes a graphene layer and at least one of a metal atomic layer and a metal ion layer, and where the metal atomic layer or the metal ion layer is interposed between the graphene layer and the insulating layer.

Abstract: An organic/inorganic composite is provided. The organic/inorganic composite comprises a silicon (Si) substrate formed with nanorods or nanoholes and three-dimensional networks of carbon nanotubes (CNTs) grown horizontally in parallel and suspended between the adjacent nanorods or inside the nanoholes. In the organic/inorganic composite, metal catalysts can be uniformly formed on the nanorods or inside the nanoholes, irrespective of the height of the nanorods or the depth of the nanoholes and the shape and aspect ratio of the nanorods or nanoholes. In addition, the carbon nanotubes grow in a three-dimensional network structure directly over the entire surface of the nanorods or the whole inner surface of the nanoholes and are directly connected to the base electrodes. With this configuration, the three-dimensional carbon nanotube networks are highly dense per unit volume, and the organic/inorganic composite is highly electrically conductive and has a large surface area.

Abstract: Disclosed are layers and patterns of nanowire or nanotube using a chemical self assembly for forming a semiconductor layer and a conductive layer of a thin film transistor by using a nanowire and/or nanotube solution and an diamine-based self-assembled monolayer (SAM) material. The Layers and patterns including layers and patterns of nanowire or nanotube using a chemical self assembly include: a substrate having a surface terminated with amine group (—NH2) by using a chemical self-assembled monolayer (SAM) material having at least one end terminated with amine group (—NH2); and a first nanowire or nanotube layer ionically coupled to the amine group (—NH2) of the surface of the substrate.

Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates. The device also includes top and bottom electrodes separated from one another between the top and bottom thermally conductive substrates to define a tunneling path, wherein the top electrode is disposed on the thermal blocking layer and the bottom electrode is disposed on the bottom thermally conductive substrate.

Abstract: A nanoparticle complex, including a semiconductor nanocrystal; and a metal complex ligand on the surface of the semiconductor nanocrystal. The nanoparticle complex may further include a polymer shell contacting the metal complex ligand.

Abstract: The present invention provides photoactive materials that include quantum-confined semiconductor nanostructures in combination with non-quantum confined and bulk semiconductor structures to enhance or create a type II band offset structure. The photoactive materials are well-suited for use as the photoactive layer in photoactive devices, including photovoltaic devices, photoconductors and photodetectors.

Abstract: An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry. Another embodiment is a method and apparatus of a semiconductor device with bottom gate structure and having radial contact using nanowires. A gate electrode is deposited on a substrate. A dielectric layer is deposited on the substrate and the gate electrode. A source-drain assembly is deposited on the dielectric layer. The source-drain assembly has source and drain electrodes connected via a nanowire in a rotationally invariant geometry. Another embodiment is a method and apparatus of a semiconductor device with top gate structure and having radial contact using nanowires. An isolation barrier layer is deposited on a substrate.

Abstract: A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.

Abstract: An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the charged defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.

Abstract: Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.

Abstract: Quantum well thermoelectric modules and a low-cost method of mass producing the modules. The devices are comprised of n-legs and p-legs, each leg being comprised of layers of quantum well material in the form of very thin alternating layers. In the n-legs the alternating layers are layers of n-type semiconductor material and electrical insulating material. In the p-legs the alternating layers are layers of p-type semiconductor material and electrical insulating material. Both n-legs and p-legs are comprised of materials providing similar thermal expansion. In preferred embodiments the layers, referred to as super-lattice layers are about 4 nm to 20 nm thick. The layers of quantum well material is separated by much larger layers of thermal and electrical insulating material such that the volume of insulating material in each leg is at least 20 times larger than the volume of quantum well material.

Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.

Abstract: A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.

Abstract: An electronic device comprises a drawn glass tube having opposing ends, a semiconductive material disposed inside of the drawn glass tube, and a first electrode and a second electrode disposed at the opposing ends of the drawn glass tube. A method of making an electrical device comprises disposing a semiconductive material inside of a glass tube, and drawing the glass tube with the semiconductive material disposed therein to form a drawn glass tube. The method of making an electrical device also comprises disposing a first electrode and a second electrode on the opposing ends of the drawn glass tube to form an electric device.

Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract: Provided is a compound semiconductor nanoparticle that exhibits circularly polarized luminescence characteristics. CdS prepared inside a core of ferritin, which is a cage-like protein, exhibits a high circularly polarized luminescence (CPL). A wavelength of the circularly polarized luminescence (CPL) can be controlled by laser irradiation, thereby enabling utilization of the compound semiconductor nanoparticle in the field of bionanotechnology, for example, in creating a WORM (Write-Once Read-Many times) memory. As the cage-like protein, which is a protein with a cavity formed therein, a protein belonging to the ferritin protein family, such as apoferritin, or a recombinant thereof can be used.

Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current carriers: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.

Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.

Abstract: Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.

Abstract: A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering).

Abstract: Described is a scalable quantum computer that includes at least two classical to quantum interface devices, with each being connected to a distinct quantum processing unit (QPU). An Einstein-Podolsky-Rosen pair generator (EPRPG) is included for generating an entangled Einstein-Podolsky-Rosen pair that is sent to the QPUs. Each QPU is quantumly connected with the EPRPG and is configured to receive a mobile qubit from the EPRPG and perform a sequence of operations such that the mobile qubit interacts with a source qubit when a teleportation algorithm is initiated, leaving a second mobile qubit in the original quantum state of the source qubit.

Abstract: In one aspect of the present invention, an article including a nanostructured functional coating disposed on a substrate is described. The functional coating is characterized by both anti-reflection properties and down-converting properties. Related optoelectronic devices are also described.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit lattice thickness of SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein.

Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to a

Abstract: The invention relates to a core-alloyed shell semiconductor nanocrystal comprising: (i) a core of a semiconductor material having a selected band gap energy; (ii) a core-overcoating shell consisting of one or more layers comprised of an alloy of the said semiconductor of (i) and a second semiconductor; (iii) and an outer organic ligand layer, provided that the core semiconductor material is not HgTe. In certain embodiments, the core semiconductor material is PbSe and the alloy shell semiconductor material has the PbSexS1-x structure; or the core semiconductor material is CdTe and the alloy shell semiconductor material has either the CdTexSe1-x or CdTexS1-x structure.

Abstract: The present invention provides for a graphene device comprising: a first gate structure, a second gate structure that is transparent or semi-transparent, and a bilayer graphene coupled to the first and second gate structures, the bilayer graphene situated at least partially between the first and second gate structures. The present invention also provides for a method of investigating semiconductor properties of bilayer graphene and a method of operating the graphene device by producing a bandgap of at least 50 mV within the bilayer graphene by using the graphene device.

Abstract: The present invention generally relates to nanotechnology and sub-microelectronic devices that can be used in circuitry, and, in particular, to nanoscale wires and other nanostructures able to encode data. One aspect of the present invention is directed to a device comprising an electrical crossbar array comprising at least two crossed wires at a cross point. In some cases, at least one of the crossed wires is a nanoscale wire, and in certain instances, at least one of the crossed wires is a nanoscale wire comprising a core and at least one shell surrounding the core. For instance, the core may comprise a crystal (e.g., crystalline silicon) and the shell may be at least partially amorphous (e.g., amorphous silicon). In certain embodiments, the cross point may exhibit intrinsic current rectification, or other electrical behaviors, and the cross point can be used as a memory device.