Abstract: The invention relates to semiconducting nanoparticles. The nanoparticles of the invention comprise a single element or a compound of elements in one or more of groups II, III, IV, V, VI. The nanoparticles have a size in the range of 1 nm to 500 nm, and comprise from 0.1 to 20 atomic percent of oxygen or hydrogen. The nanoparticles are typically formed by comminution of bulk high purity silicon. One application of the nanoparticles is in the preparation of inks which can be used to define active layers or structures of semiconductor devices by simple printing methods.

Abstract: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes a catalyst portion (55) containing a second material which is different from the first material. The first material includes a metal containing at least one of elements selected from the second group to the fourteenth group of the periodic table or a compound thereof. The second material is a catalyst which grows carbon nanotubes in a vapor phase.

Abstract: Disclosed are methods of fabricating nanogaps and various devices composed of nanogaps. The nanogap devices disclosed herein can be used as in a number of electronic, photonic and quantum mechanical devices, including field-effect transistors and logic circuits.

Abstract: Disclosed herein is a method for producing catalyst-free single crystal silicon nanowires. According to the method, nanowires can be produced in a simple and economical manner without the use of any metal catalyst. In addition, impurities contained in a metal catalyst can be prevented from being introduced into the nanowires, contributing to an improvement in the electrical and optical properties of the nanowires. Also disclosed herein are nanowires produced by the method and nanodevice comprising the nanowires.

Abstract: The present invention is a transistor and a process for making the transistor in which the semiconductor component comprises at least one carbon nanotube functionalized by cycloaddition with a fluorinated olefin. Functionalization with the fluorinated olefin renders the carbon nanotube semiconducting.

Abstract: A fine vacuum tube element and other electronic elements are integrated and formed on a semiconductor substrate, and the fine vacuum tube element and the other electronic elements transmit signals to and from each other. When integrating the vacuum tube element with the other electronic elements, a quantum effect is realized in a room temperature environment by utilizing ballistic electrons (non-scattering electrons) traveling through the vacuum, and in the integrated circuit, an A/D converter is constructed by an interference system such as a Mach-Zehnder interferometer. Also an integrated circuit of an advanced function-integrated type is provided, comprising an interference system such as a Mach-Zehnder interferometer wherein weighting of the Mach-Zehnder interferometer is constituted for image processing and signal code conversion.

Abstract: Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.

Abstract: A device including semiconductor nanocrystals and a layer comprising a doped organic material disposed over the substrate and in electrical connection with at least one semiconductor nanocrystals is disclosed. Methods for making the device and for improving the efficiency of a device are also disclosed.

Abstract: A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: Methods and devices for transparent electronics are disclosed. According to an embodiment, transparent electronics are provided based on transfer printed carbon nanotubes that can be disposed on both rigid and flexible substrates. Methods are provided to enable highly aligned single-walled carbon nanotubes (SWNTs) to be used in transparent electronics for achieving high carrier mobility while using low-temperature processing. According to one method, highly aligned nanotubes can be grown on a first substrate. Then, the aligned nanotubes can be transferred to a rigid or flexible substrate having pre-patterned gate electrodes. Source and drain electrodes can be formed on the transferred nanotubes. The subject devices can be integrated to provide logic gates and analog circuitry for a variety of applications.

Abstract: An electronic device has a source electrode, a drain electrode spaced apart from said source electrode, and at least one of a conducting material, dielectric material and a semiconductor material disposed between said source electrode and said drain electrode. At least one of the source electrode, the drain electrode and the semiconductor material includes at least one nanowire.

Abstract: Electrical control of the emitter of a coupled quantum emitter-resonant cavity structure is provided. Electrodes are disposed near a semiconductor quantum dot coupled to a semiconductor optical cavity such that varying an applied bias at the electrodes alters an electric field at the quantum dot. Optical input and output ports are coupled to the cavity, and an optical response of the device relates light emitted from the output port to light provided to the input port. Altering the applied bias at the electrodes is capable of altering the optical response. Preferably, the closest electrode to the cavity is disposed between or away from angular lobes of the cavity mode, to reduce loss caused by the proximity of electrode to cavity. The present approach is applicable to both waveguide-coupled devices and non-waveguide devices.

Abstract: Nanotube-based structure and method of forming the same are disclosed. A structure having two tips is provided for defining a location for forming a nanotube connection. The nanotube connection, which can be coated with an electrically conductive polymer for enhanced conductivity, can be used in forming nanotube-based devices for various applications.

Abstract: Various aspects of the present invention generally relate to nanoscale wire devices and methods for use in determining analytes suspected to be present in a sample, and systems and methods of immobilizing entities such as reaction entities relative to nanoscale wires. In one aspect, a nucleic acid, such as DNA, may be immobilized relative to a nanoscale wire, and in some cases, grown from the nanoscale wire. In certain embodiments, the nucleic acid may interact with entities such as other nucleic acids, proteins, etc., and in some cases, such interactions may be reversible. As an example, an enzyme such as telomerase may be allowed to bind to DNA immobilized relative to a nanoscale wire. The telomerase may extend the length of the DNA, for instance, by reaction with free deoxynucleotide triphosphates in solution; additionally, various properties of the nucleic acid may be determined, for example, using electric field interactions between the nucleic acid and the nanoscale wire.

Abstract: Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same.

Abstract: An optoelectronic device is disclosed which includes a quantum dot layer including plurality of quantum dots which do not have capping layers. This optoelectronic device may be a quantum dot light-emitting device, which includes (1) a substrate which is transparent or translucent, (2) an anode electrical conducting layer which is transparent or translucent, and is located adjacent to the substrate, (3) a planarizing/hole injection layer which is located adjacent to the anode electrical conducting layer, (4) a quantum dot layer including the plurality of quantum dots which do not have capping layers, and (5) a cathode electrical conducting layer which is located adjacent to the quantum dot layer.

Abstract: A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth Layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain.

Abstract: A quantum interference transistor may include a source; a drain; N channels (N?2), between the source and the drain, and having N?1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

Abstract: A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering).

Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.

Abstract: A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

Abstract: The present invention relates to the formation of electron spin EPR pairs and manipulation of such entangled electrons. The invention comprises a static quantum dot located part way along a quantum wire with means for adjusting the confining potential of the quantum dot. The quantum wire may for instance be formed by gate electrode (4, 6) with the quantum dot formed by a further gate electrode (8). The invention also comprises means for generating a electrostatic wave propagating along the wire, such as a surface acoustic wave transducer (10). In use a pair of electrons may be loaded into the static quantum dot and allowed to relax to a singlet ground state, in which the electrons are spin entangled. The propagating electrostatic wave acts as a series of quantum dots moving along the quantum wire.

Abstract: The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.

Abstract: The present teachings provide methods for sorting nanotubes according to their wall number, and optionally further in terms of their diameter, electronic type, and/or chirality. Also provided are highly enriched nanotube populations provided thereby and articles of manufacture including such populations.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.

Abstract: A carbon nanotube of a nanotube device has at least two segments with different characteristics. The segments meet at a junction and a diameter of the carbon nanotube on either side of the junction is about the same. One segment may be doped differently from another segment. One segment may be p doped and another segment n doped. One segment may be doped with a different carrier concentration from another segment. The nanotube device may be used in power semiconductor devices including power diodes and power transistors. These power devices will be very power efficient, wasting significantly less energy than similar manufactured using silicon technology.

Abstract: Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like.

Abstract: A method of synthesizing semiconductor nanostructures of at least one semiconductor material (e.g. nanowires, nanorods, nanoribbons, nanodots, quantumdots, etc.) is described which includes the steps of placing a solid catalyst particle on a substrate, placing the combination of the said substrate and the said solid catalyst in a chamber of low oxygen partial pressure, below I×10?2 mbar, adding one or more gaseous reactants comprising at least one of said semiconductor material and a suitable precursor therefor and heating the said combination to a temperature above 200° C. but below the melting point of the solid catalyst particle. Nanostructures made by the method are also claimed.

Abstract: A method of manufacturing a nanowire, a method of manufacturing a semiconductor apparatus including a nanowire and a semiconductor apparatus formed from the same are provided. The method of manufacturing a semiconductor apparatus may include forming a material layer pattern on a substrate, forming a first insulating layer on the material layer pattern, a first nanowire forming layer and a top insulating layer on the substrate, wherein a total depth of the first insulating layer and the first nanowire forming layer may be formed to be smaller than a depth of the material layer pattern, sequentially polishing the top insulating layer, the first nanowire forming layer and the first insulating layer so that the material layer pattern is exposed, exposing part of the first nanowire forming layer to form an exposed region and forming a single crystalline nanowire on an exposed region of the first nanowire forming layer.

Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.

Abstract: A photovoltaic apparatus includes an absorber layer, and an up-converter layer positioned adjacent to the absorber layer, the up-converter layer including a plurality of quantum dots of first material in a matrix of a second material. In one example, the first material has a lower bandgap than the absorber layer, and the second material comprises a semiconductive material or an insulator.

Abstract: The present invention relates to a method of manufacturing a carbon nanotube transistor in which a carbon nanotube channel is formed between a source electrode and a drain electrode and a gate electrode is formed at one side of the carbon nanotube channel, the method comprising the steps of: (a) forming the carbon nanotube channel on a substrate; (b) electrically connecting the source electrode and the drain electrode to both ends of the carbon nanotube channel, respectively; and (c) applying a stress voltage across the source electrode and the drain electrode to remove metallicity of the carbon nanotube channel. According to the method of manufacturing a carbon nanotube transistor of the present invention, a metallic part can be selectively removed from a carbon nanotube which is used as a channel of a transistor and has metallic properties and semiconductor properties mixed with each other.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant.

Abstract: This invention provides a process for producing a carbon nanotube electric field effect transistor that can improve yield in channel preparation. Carbon nanotubes dispersed in a mixed acid composed of sulfuric acid and nitric acid are subjected to radical treatment with aqueous hydrogen peroxide to cut the carbon nanotubes and thus to provide carboxyl-introduced carbon nanotube fragments. The carbon nanotube fragments are attached, through a covalent bond and/or an electrostatic bond, to a site, where a source electrode is to be formed, and a site where a drain electrode is to be formed, in a substrate with a functional group, to be attached to a carboxyl group, introduced thereinto. The carbon nanotube fragments attached to the substrate are attached to carbon nanotubes as channels through n-n interaction to fix the carbon nanotubes as channels to the substrate.

Abstract: A multiple quantum well structure (1) which comprises at least a first quantum well structure (2a) for generating radiation of a first wavelength (6) and at least a second quantum well structure (2b) for generating radiation of a second wavelength (7), which is greater than the first wavelength (6), and is provided for emission of radiation of a main wavelength (14), wherein the second wavelength (7) differs from the first wavelength (6) in such a way that the main wavelength (14) changes only by a predetermined maximum value in the event of a shift in the first wavelength (6) and the second wavelength (7). A radiation-emitting semiconductor body and a radiation-emitting component are furthermore described.

Abstract: A resonant tunneling structure for generating oscillation with multiple fundamental oscillation frequencies is provided. A first quantum well layer has a second sub-band (E2). A second quantum well layer has a first sub-band (E1) and a third sub-band (E3). When no electric field is applied, the resonant tunneling structure satisfies “(Eb1, Eb2)<E1<E2<E3”, where band edge energies of a first and second electrical contact layers relative to a carrier are expressed by Eb1 and Eb2, respectively. When a first electric field (Va) is applied, a resonant tunneling phenomenon is caused by the third sub-band and the second sub-band. When a second electric field (Vb) different in polarity from the first electric field is applied, a resonant tunneling phenomenon is caused by the second sub-band and the first sub-band.

Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.

Abstract: The invention relates to a semiconductor sensor device (10) for sensing a substance comprising at least one nanowire (11) which is formed on a surface of a semiconductor body (12) and which is connected at a first end to a first electrically conducting connection region (13) and at a second end to’ a second electrically conducting connection region (14) while a fluid (20) comprising a substance (30) to be sensed can flow along the nanowire (11) and the substance (30) to be sensed can influence’ the electrical properties of the nanowire (11), wherein the nanowire (11) comprises viewed in a longitudinal direction subsequently a first semiconductor subregion (1) comprising a first semiconductor material and a second semiconductor subregion (2) comprising a second semiconductor material different from the first semiconductor material. According to the invention’ the first semiconductor material comprises a IV element material and the second semiconductor material comprises a III-V compound.

Abstract: The present invention provides for a metal-molecule heterostructure comprising (a) a plurality of metal, semimetallic or semiconducting nanoparticles, and (b) a plurality of electrically conductive organic molecules interspersed among the nanoparticles. The metal-molecular heterostructure is useful in a device, such as a thermoelectric energy converter, battery or capacitor.

Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: A nanowire according to the present invention includes: a nanowire body made of a first material; and a plurality of semiconductor particle made of a second material and being contained in at least a portion of the interior of the nanowire body.

Abstract: It is to provide a thermodynamically and chemically stable dopant material which can achieve controls of the pn conduction types, carrier density, and threshold value of gate voltage, and a manufacturing method thereof. Further, it is to provide an actually operable semiconductor device such as a transistor with an excellent high-speed operability and high-integration characteristic. Provided is a dopant material obtained by depositing, on a carbon nanotube, a donor with a smaller ionization potential than an intrinsic work function of the carbon nanotube or an acceptor with a larger electron affinity than the intrinsic work function of the carbon nanotube. The ionization potential of the donor in vacuum is desired to be 6.4 eV or less, and the electron affinity of the acceptor in vacuum to be 2.3 eV or more.

Abstract: Provided are beam ablation lithography methods capable of removing and manipulating material at the nanoscale. Also provided are nanoscale devices, nanogap field effect transistors, nano-wires, nano-crystals and artificial atoms made using the disclosed methods.

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Abstract: Provided are a silica nanowire that includes silicon nanodots and a method of preparing the same. The silica nanowire has excellent capacitance characteristics and improved light absorption ability, and thus can be effectively used in a variety of fields, such as various semiconductor devices including CTF memory, image sensors, photodetectors, light emitting diodes, laser diodes, and the like.