Single Electron Transistors: Coulomb Blockade Device (epo) Patents (Class 257/E29.322)
  • Patent number: 11580437
    Abstract: A qubit device includes a crystal immobilized on a substrate and in contact with electrodes. The crystal exhibits a charge pair symmetry and with an electron current moving clockwise, counter clockwise, or both. The current in can be placed in a state of superposition wherein the current is unknown until it is measured, and the direction of the current is measured to produce a binary output corresponding to a logical zero or a logical one. A state of the qubit device is monitored by measuring a voltage, a current, or a magnetic field and assigning a superposition or base state depending on a threshold value.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: February 14, 2023
    Assignees: Streamline Automation LLC, Wake Forest University
    Inventors: David L. Carroll, Alton J. Reich, Roberto Di Salvo
  • Publication number: 20120286243
    Abstract: A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8093638
    Abstract: Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide provides a reliable gate dielectric with an equivalent oxide thickness thinner than attainable using SiO2.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8044379
    Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: October 25, 2011
    Assignees: Hitachi Chemical Co., Ltd., Hitachi Chemical Research Center, Inc.
    Inventor: Yongxian Wu
  • Publication number: 20110233523
    Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 29, 2011
    Inventors: Sung-Dae SUK, Kyoung-Hwan YEO, Ming LI, Yun-Young YEOH
  • Patent number: 8017935
    Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Renaldi Winoto, Dirk Leipold
  • Publication number: 20110121895
    Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the ESR line substrate beneath it. A fourth gate in close proximity to a single dopant donor gate atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.
    Type: Application
    Filed: February 11, 2009
    Publication date: May 26, 2011
    Inventors: Andrea Morello, Andrew Dzurak, Hans-Gregor Huebl, Robert Graham Clark, Laurens Henry Willems Van Beveren, Lloyd Christopher Leonard Hollenberg, David Normal Jamieson, Christopher Escott
  • Patent number: 7872253
    Abstract: A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit lattice thickness of SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: January 18, 2011
    Assignee: National University Corporation Nagoya University
    Inventors: Hiromichi Ohta, Kunihito Koumoto, Yoriko Mune
  • Patent number: 7749922
    Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 6, 2010
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Alexey Bezryadin, Mikas Remeika
  • Patent number: 7700984
    Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: April 20, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Mikio Yukawa
  • Patent number: 7700937
    Abstract: A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 20, 2010
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Shinichi Hirose, Motomu Takatsu, Tatsuya Usuki, Yasuhiko Arakawa
  • Patent number: 7629244
    Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: December 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Chung-woo Kim, Ju-hyung Kim
  • Patent number: 7602069
    Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: October 13, 2009
    Assignee: Universität Duisburg-Essen
    Inventors: Günter Schmid, Ulrich Simon, Dieter Jäger, Venugopal Santhanam, Torsten Reuter
  • Patent number: 7508039
    Abstract: Carbon nanotube (CNT) based devices include an actuator/switch that includes one or more fixed CNTs and a moveable CNT that can be urged toward or into contact with a selected fixed CNT with a magnetic field produced by a current in a control conductor. The control conductor can be formed of one or more CNTs, and the fixed and moveable CNTs can be retained by a support, and motion of the moveable CNT limited by a cavity defined in the support. In other examples, CNT FETS are used to form CNT transmission gates that are arranged to define circuits configured as multiplexers or to realize logical functions, addition, multiplication, or other operations such as Galois field arithmetic.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: March 24, 2009
    Assignee: State of Oregon Acting By and Through The State Board of Higher Education On Behalf of Portland State University
    Inventor: Anas N. Al-Rabadi
  • Patent number: 7427772
    Abstract: A substrate for semiconductor light emitting devices is provided. The substrate is characterized in that the substrate is a single crystal material and has a nanocrystal structure capable of diffracting an electromagnetic wave. The nanocrystal structure is disposed on a surface portion of the substrate and includes an etched region and an unetched region, wherein the etched region has a depth of 10-200 nm. Due to the periodicity of the nanocrystal structure, the semiconductor material grown on the substrate has fewer defects, and the material stress is reduced.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 23, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chang-Cheng Chuo, Chih-Ming Lai
  • Patent number: 7385262
    Abstract: A method to electronically modulate the energy gap and band-structure of semiconducting carbon nanotubes is proposed. Results show that the energy gap of a semiconducting nanotube can be narrowed when the nanotube is placed in an electric field perpendicular to the tube axis. Such effect in turn causes changes in electrical conductivity and radiation absorption characteristics that can be used in applications such as switches, transistors, photodetectors and polaron generation. By applying electric fields across the nanotube at a number of locations, a corresponding number of quantum wells are formed adjacent to one another. Such configuration is useful for Bragg reflectors, lasers and quantum computing.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: June 10, 2008
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: James O'Keeffe, Kyeongjae Cho
  • Publication number: 20080054253
    Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Staszewski, Renaldi Winoto, Dirk Leipold
  • Patent number: 7166858
    Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: January 23, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Christoph Wasshuber
  • Patent number: 7138651
    Abstract: A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: November 21, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Uchida, Junji Koga, Ryuji Ohba
  • Patent number: 6946703
    Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: September 20, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-il Ryu, Jo-won Lee, Se-wook Yoon, Chung-woo Kim
  • Patent number: 6888665
    Abstract: A molecule is wired into an electronic circuit by attaching a metal nanoparticle to the molecule and then electrically connecting a metal nanoparticle to the electric circuit. The metal nanoparticle interconnects can bridge the gap between small molecules and conventional electric circuits. An optical second harmonic also may be generated by impinging optical radiation having a first frequency on an array of molecularly bridged metal nanoparticles, to generate optical energy at a second frequency that is twice the first frequency. Red to blue light conversion thereby may be provided.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 3, 2005
    Assignee: North Carolina State University
    Inventors: Daniel Feldheim, Louis C. Brousseau, III, James P. Novak