Controllable By Only Signal Applied To Control Electrode (e.g., Base Of Bipolar Transistor, Gate Of Field-effect Transistor) (epo) Patents (Class 257/E29.169)

  • Patent number: 9018673
    Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 28, 2015
    Assignee: Freescale Semiconductor Inc.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8969869
    Abstract: An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: March 3, 2015
    Assignee: Raydium Semiconductor Corporation
    Inventor: Yao-Sheng Huang
  • Patent number: 8937296
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of III-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 20, 2015
    Assignee: The Regents of the University of California
    Inventor: John Edward Bowers
  • Patent number: 8772091
    Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 8, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Javier A Salcedo, David Hall Whitney
  • Publication number: 20140061715
    Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8642996
    Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill
  • Patent number: 8597968
    Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 3, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Cheng Chen, Chen-Yueh Li, Ching-Sang Chuang, Ching-Chieh Shih, An-Thung Cho
  • Patent number: 8592860
    Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: November 26, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Javier A Salcedo, David Hall Whitney
  • Publication number: 20130234213
    Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sivakumar KUMARASAMY, Clemens Fitz, Markus Lenski, Jochen Poth, Kristin Schupke
  • Publication number: 20130038380
    Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Divya Kumar, Anuwat Saetow, Robert B. Tremaine
  • Patent number: 8344381
    Abstract: A UV sensor comprises a silicon-rich dielectric layer with a refractive index in a range of about 1.7 to about 2.5 for serving as the light sensing material of the UV sensor. The fabrication method of the UV sensor can be integrated with the fabrication process of semiconductor devices or flat display panels.
    Type: Grant
    Filed: February 21, 2010
    Date of Patent: January 1, 2013
    Assignee: AU Optronics Corp.
    Inventors: An-Thung Cho, Chi-Hua Sheng, Ruei-Liang Luo, Wan-Yi Liu, Wei-Min Sun, Chi-Mao Hung, Chun-Hsiun Chen, Wei-Ming Huang
  • Publication number: 20120292735
    Abstract: The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Applicant: GLOBALFOUNDRIES Singapore Pte.Ltd.
    Inventors: Shyue Seng (Jason) Tan, Ying Keung Leung, Elgin Quek
  • Publication number: 20120235022
    Abstract: A solid-state imaging device that includes: a pixel array section configured by an array of a unit pixel, including an optoelectronic conversion section that subjects an incoming light to optoelectronic conversion and stores therein a signal charge, a transfer transistor that transfers the signal charge stored in the optoelectronic conversion section, a charge-voltage conversion section that converts the signal charge provided by the transfer transistor into a signal voltage, and a reset transistor that resets a potential of the charge-voltage conversion section; and voltage setting means for setting a voltage of a well of the charge-voltage conversion section to be negative.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: SONY CORPORATION
    Inventor: Fumihiko KOGA
  • Publication number: 20120205714
    Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, David Hall Whitney
  • Patent number: 8129719
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Publication number: 20120043622
    Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eduard A. CARTIER, Qingqing LIANG, Yue LIANG, Yanfeng WANG
  • Publication number: 20110278642
    Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.
    Type: Application
    Filed: April 7, 2011
    Publication date: November 17, 2011
    Applicant: GREAT POWER SEMICONDUCTOR CORP.
    Inventor: KAO-WAY TU
  • Publication number: 20110278696
    Abstract: A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 17, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Publication number: 20110198587
    Abstract: A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 18, 2011
    Applicant: C/O FUJI ELECTRIC SYSTEMS CO., LTD
    Inventor: Shigeyuki TAKEUCHI
  • Publication number: 20110169081
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer is formed with a trench. The second semiconductor layer is buried in the trench, and includes a hollow portion. A length of the hollow portion along depth direction of the trench is 5 ?m or less or 15 ?m or more.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 14, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hironori Ishikawa, Shinya Sato, Hiroyuki Sugaya, Tomoyuki Sakuma
  • Publication number: 20110114950
    Abstract: An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 19, 2011
    Inventor: Yao-Sheng Huang
  • Patent number: 7923730
    Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hidekazu Miyairi
  • Publication number: 20110062491
    Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.
    Type: Application
    Filed: April 23, 2009
    Publication date: March 17, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Shuhei Nakata
  • Patent number: 7888712
    Abstract: A semiconductor device includes a first conductive type SiC semiconductor substrate; a second conductive type well formed on the SiC semiconductor substrate; a first impurity diffusion layer formed by introducing a first conductive type impurity so as to be partly overlapped with the well in a region surrounding the well; a second impurity diffusion layer formed by introducing the first conductive type impurity in a region spaced apart for a predetermined distance from the impurity diffusion layer in the well; and a gate electrode opposed to a channel region between the first and the second impurity diffusion layers with gate insulating film sandwiched therebetween.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: February 15, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Mineo Miura
  • Publication number: 20110024805
    Abstract: A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 3, 2011
    Inventors: Thorsten Kammler, Ralf Richter, Markus Lenski, Gunter Grasshoff
  • Publication number: 20100327327
    Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes forming rows and columns, wherein: the electrodes extend, in rows, in successive grooves with insulated walls, disposed in the substrate thickness and parallel to the charge transfer direction.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • Patent number: 7851854
    Abstract: A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the channel; a gate electrode in the trench via a gate insulation film; a source electrode coupled with the source region; a drain electrode on the substrate opposite to the drift layer; and a bottom layer under the trench. An edge portion of the bottom layer under a corner of a bottom of the trench is deeper than a center portion of the bottom layer under a center portion of the bottom of the trench.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: December 14, 2010
    Assignee: DENSO CORPORATION
    Inventors: Eiichi Okuno, Naohiro Suzuki, Nobuyuki Kato
  • Patent number: 7851256
    Abstract: Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-soo Chung, Dong-ho Lee, Seong-deok Hwang, Sun-won Kang, Seung-duk Baek
  • Patent number: 7825449
    Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: November 2, 2010
    Assignee: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Yuuichi Takeuchi, Takeshi Endo, Eiichi Okuno, Toshimasa Yamamoto
  • Patent number: 7812376
    Abstract: Provided are a nonvolatile memory device and methods of fabricating and operating the same. The memory device may include a substrate, at least a first and a second electrode on the substrate to be spaced a distance from each other, a conductive nanotube between the first and second electrodes and selectively coming into contact with the first electrode or the second electrode due to an electrostatic force and a support supporting the conductive nanotube. The memory device may be an erasable nonvolatile memory device which may retain information even when no power is supplied and may ensure relatively high operating speed and relatively high integration density. Because the memory device writes and erases information in units of bits, the memory device may be applied to a large number of fields.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyoo Yoo, Soo-Il Lee
  • Publication number: 20100237434
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.
    Type: Application
    Filed: June 22, 2006
    Publication date: September 23, 2010
    Applicant: NXP B.V.
    Inventors: Wibo D. Van Noort, Jan Sonsky, Philippe Meunier-Beillard, Erwin Hijzen
  • Patent number: 7790487
    Abstract: A method for fabricating a photo sensor on an amorphous silicon thin film transistor panel includes forming a photo sensor with a bottom electrode, a silicon-rich dielectric layer, and a top electrode, such that the light sensor has a high reliability. The fabrication method is compatible with the fabrication process of a thin film transistor.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: September 7, 2010
    Assignee: AU Optronics Corp.
    Inventors: Ching-Chieh Shih, An-Thung Cho, Chia-Tien Peng, Kun-Chih Lin
  • Patent number: 7777222
    Abstract: Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends; positioning the conductive article between said first and second structures such that the first structure clamps the first and second ends of the article to the second structure, and such that the first and second output electrodes are opposite each other with the article positioned therebetween; providing at least one signal electrode in electrical communication with the conductive article; and providing at least one control electrode in spaced relation to the conductive article such that the control electrode may control the conductive article to form a conductive pathway between the signal electrode and the first output electrode.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 17, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Publication number: 20100181617
    Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 22, 2010
    Inventor: Il Kwan Lee
  • Publication number: 20100156511
    Abstract: A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Edward J. Nowak
  • Publication number: 20100127332
    Abstract: Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 27, 2010
    Inventors: Jun Liu, Albert Ratnakumar, Qi Xiang, Jeffrey Xiaoqi Tung
  • Patent number: 7701012
    Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30).
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongzhong Xu, Chai Ean Gill, James D. Whitfield, Jinman Yang
  • Publication number: 20090283833
    Abstract: In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 19, 2009
    Inventor: Lars Bach
  • Publication number: 20090267111
    Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 29, 2009
    Applicant: LAKOTA TECHNOLOGIES, INC.
    Inventors: Alexei ANKOUDINOV, Vladimir RODOV, Richard CORDELL
  • Publication number: 20090250727
    Abstract: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on the N+ substrate. The silicon dioxide layer is disposed between the N-type layer and the P-type layer. The P+ layer is disposed on the P-type layer and the N-type layer.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 8, 2009
    Applicant: INERGY TECHNOLOGY INC.
    Inventor: MING-JANG LIN
  • Publication number: 20090218624
    Abstract: An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer. An insulation layer is formed on the lower surfaces of the grooves and a second silicon layer is formed filling the grooves having the insulation layer formed thereon. Gates are formed on the second silicon layer and junction regions are formed in the first silicon layer on both sides of the gates to contact the insulation layer.
    Type: Application
    Filed: December 8, 2008
    Publication date: September 3, 2009
    Inventor: Bo Youn KIM
  • Publication number: 20090195723
    Abstract: An active matrix substrate according to one aspect of the present invention is a TFT array substrate including a TFT. The active matrix substrate includes a gate signal line electrically connected to a gate electrode of the TFT, a first insulating film formed above the gate signal line, an auxiliary capacitance electrode formed above the first insulating film and supplied with a common potential, a second insulating film formed above the auxiliary capacitance electrode, a source signal line formed above the second insulating film and electrically connected to a source electrode of the TFT, a third insulating film formed above the source signal line, and a pixel electrode formed above the third insulating film so that the pixel electrode overlaps with a part of the auxiliary capacitance electrode.
    Type: Application
    Filed: January 14, 2009
    Publication date: August 6, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Toshio Araki, Osamu Miyakawa, Nobuaki Ishiga, Shingo Nagano
  • Publication number: 20090184355
    Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
    Type: Application
    Filed: March 30, 2009
    Publication date: July 23, 2009
    Inventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rosner, Thomas Schulz
  • Publication number: 20090153056
    Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.
    Type: Application
    Filed: April 2, 2008
    Publication date: June 18, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Po-Lin Chen, Chun-Nan Lin, Shu-Feng Wu, Wen-Ching Tsai
  • Publication number: 20090134488
    Abstract: An immersion liquid is provided comprising an ion-forming component, e.g. an acid or a base, that has a relatively high vapor pressure. Also provided are lithography processes and lithography systems using the immersion liquid.
    Type: Application
    Filed: February 6, 2006
    Publication date: May 28, 2009
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Hans Jansen, Marco Koert Stavenga, Jacobus Johannus Leonardus Hendricus Verspay, Franciscus Johannes Joseph Janssen, Anthonie Kuijper
  • Publication number: 20090121289
    Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1 -x),where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.
    Type: Application
    Filed: January 13, 2009
    Publication date: May 14, 2009
    Inventor: Klaus Schruefer
  • Publication number: 20090114899
    Abstract: A resistance memory is manufactured using semiconductor processing to comprise planar dual-tip electrodes so that the electric field in the resistance memory is concentrated to reduce the number of fuses in the dielectric material and improve the device characteristics. The resistance memory comprises: a first memory cell including a first bottom electrode and a common top electrode; and a second memory cell including a second bottom electrode and the common top electrode shared with the first memory cell; wherein the first bottom electrode, the second bottom electrode and the common top electrode are disposed on the same plane and are separated by a resistive conversion layer; wherein the common top electrode is connected to the ground through a via, while the first bottom electrode and the second bottom electrode are connected to the source of a transistor through a plug, respectively.
    Type: Application
    Filed: June 19, 2008
    Publication date: May 7, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: HENG-YUAN LEE, CHING-CHIUN WANG, PANG-HSU CHEN, TAI-YUAN WU
  • Publication number: 20090114969
    Abstract: An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n?-type drift layer to extend into the n?-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 7, 2009
    Applicant: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Yuuichi Takeuchi, Takeshi Endo, Eiichi Okuno, Toshimasa Yamamoto
  • Publication number: 20090078962
    Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 26, 2009
    Applicant: LAKOTA TECHNOLOGIES, INC.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Publication number: 20080315246
    Abstract: A transistor switch circuit includes: a MOS transistor in which a channel is formed when a gate-source voltage is zero; and a voltage supply part which is connected to a gate of the MOS transistor to supply the gate with a voltage for turning off the MOS transistor.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Ueno, Shinji Ohtaki, Tomohiko Ito