Unipolar Device (epo) Patents (Class 257/E29.226)

  • Patent number: 8933492
    Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 13, 2015
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 8697527
    Abstract: A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 8633492
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8552474
    Abstract: A junction field effect transistor structure includes a grid electrode, a source electrode, a drain electrode and a substrate. The grid electrode includes a polysilicon layer and a P-type implanted layer. The source electrode includes an N-type implanted layer, an N-type well layer and a heavy-implanted N-type well layer. The drain electrode includes the N-type implanted layer, the N-type well layer and the heavy-implanted N-type well layer. The substrate is connected with a substrate connecting end by the P-type implanted layer, a P-type well layer, a heavy-implanted P-type well layer and a P-type buried layer. The junction field effect transistor structure of the present invention can be manufactured without adding any masking step based on the existing technologies, and has the high-voltage resistant characteristic to meet the requirements in practical applications. Furthermore, it has the compact structure and compatible technology.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 8, 2013
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventor: Rongwei Yu
  • Patent number: 8513033
    Abstract: A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naoyoshi Kawahara, Shinya Maruyama, Shinichi Miyake
  • Patent number: 8507957
    Abstract: A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: August 13, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chin Hou, Shyue-Shyh Lin, Li-Chun Tien, Shu-Min Chen, Pin-Dai Sue
  • Patent number: 8426868
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Publication number: 20130001656
    Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Inventors: BADIH EL-KAREH, Kyu Ok LEE, Joo Hyung KIM, Jung Joo KIM
  • Publication number: 20120280287
    Abstract: A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
    Type: Application
    Filed: May 2, 2011
    Publication date: November 8, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chin Hou, Shyue-Shyh Lin, Li-Chun Tien, Shu-Min Chen, Pin-Dai Sue
  • Publication number: 20120211816
    Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; plugging the smallest of the holes while shrinking the other holes by depositing a mask material; making contact holes by removing a prescribed number of the insulating films and a prescribed number of the electrode films in regions directly under the other holes by performing etching using the mask material and the hard mask as a mask; and filling conductive material into the contact holes.
    Type: Application
    Filed: September 2, 2011
    Publication date: August 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Katsunori YAHASHI
  • Patent number: 8138033
    Abstract: A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Francine Y. Robb, Prasad Venkatraman
  • Patent number: 8110873
    Abstract: A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 7, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sung-Gon Choi, Hee-Seog Jeon
  • Publication number: 20120007054
    Abstract: A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Publication number: 20120001240
    Abstract: A junction field effect transistor structure includes a grid electrode, a source electrode, a drain electrode and a substrate. The grid electrode includes a polysilicon layer and a P-type implanted layer. The source electrode includes an N-type implanted layer, an N-type well layer and a heavy-implanted N-type well layer. The drain electrode includes the N-type implanted layer, the N-type well layer and the heavy-implanted N-type well layer. The substrate is connected with a substrate connecting end by the P-type implanted layer, a P-type well layer, a heavy-implanted P-type well layer and a P-type buried layer. The junction field effect transistor structure of the present invention can be manufactured without adding any masking step based on the existing technologies, and has the high-voltage resistant characteristic to meet the requirements in practical applications. Furthermore, it has the compact structure and compatible technology.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Inventor: Rongwei Yu
  • Publication number: 20110241067
    Abstract: The invention relates to a method for producing a switch element. The invention is characterized in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 6, 2011
    Inventors: Thomas Schimmel, Fangqing Xie, Christian Obermair
  • Patent number: 8004035
    Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Publication number: 20110168968
    Abstract: Fluidic nanotube devices are described in which a hydrophilic, non-carbon nanotube, has its ends fluidly coupled to reservoirs. Source and drain contacts are connected to opposing ends of the nanotube, or within each reservoir near the opening of the nanotube. The passage of molecular species can be sensed by measuring current flow (source-drain, ionic, or combination). The tube interior can be functionalized by joining binding molecules so that different molecular species can be sensed by detecting current changes. The nanotube may be a semiconductor, wherein a tubular transistor is formed. A gate electrode can be attached between source and drain to control current flow and ionic flow. By way of example an electrophoretic array embodiment is described, integrating MEMs switches.
    Type: Application
    Filed: February 7, 2008
    Publication date: July 14, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Peidong Yang, Rongrui He, Joshua Goldberger, Rong Fan, Yiying Wu, Deyu Li, Arun Majumdar
  • Publication number: 20110133259
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7906807
    Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: March 15, 2011
    Assignee: Spansion LLC
    Inventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
  • Patent number: 7872311
    Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: January 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Suresh Venkatesan
  • Patent number: 7868388
    Abstract: In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal layer of the memory circuit. Numerous other aspects are provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 7829411
    Abstract: The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.
    Type: Grant
    Filed: January 20, 2003
    Date of Patent: November 9, 2010
    Assignee: NXP B.V.
    Inventors: Josine Johanna Gerarda Petra Loo, Youri Ponomarev, Robertus Theodorus Fransiscus Schaijk
  • Patent number: 7820552
    Abstract: An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 26, 2010
    Assignee: International Business Machines Corporation
    Inventors: Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Hongwen Yan, Vijay Narayanan, Vamsi K. Paruchuri, Bruce B. Doris
  • Patent number: 7811887
    Abstract: Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: October 12, 2010
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Rustom Irani, Amichai Givant
  • Publication number: 20100230731
    Abstract: An electrochemical transistor device is provided, comprising a source contact, a drain contact, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and said at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and said gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to said gate electrode(s).
    Type: Application
    Filed: February 26, 2010
    Publication date: September 16, 2010
    Inventors: Marten Armgarth, Miaioxiang M. Chen, David A. Nilsson, Rolf M. Berggren, Thomas Kugler, Tommi M. Remonen, Robert Forchheimer
  • Patent number: 7785946
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: August 31, 2010
    Assignee: Infineon Technologies AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Publication number: 20100200840
    Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.
    Type: Application
    Filed: April 22, 2010
    Publication date: August 12, 2010
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7772620
    Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: August 10, 2010
    Assignee: SuVolta, Inc.
    Inventor: Ashok K. Kapoor
  • Patent number: 7755112
    Abstract: A field effect transistor includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately arranged on the channel region with a gate electrode interposed between the source electrode and the drain electrode, a bonding pad to be connected with an external circuit; and an air-bridge connected with the bonding pad. The air-bridge includes an electrode contact terminal to be connected with the source electrode or the drain electrode and an aerial circuit line for connecting the electrode contact terminal with a contact terminal of the bonding pad, the widthwise cross sectional area of the electrode contact terminal being equal to or less than that of the aerial circuit line.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaki Kobayashi
  • Publication number: 20100157664
    Abstract: A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved.
    Type: Application
    Filed: July 22, 2009
    Publication date: June 24, 2010
    Inventor: Sung Woong Chung
  • Patent number: 7732880
    Abstract: A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 8, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryo Kanda, Iwao Takahashi, Yoshinori Sato
  • Publication number: 20100110759
    Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Christina Hutchinson, Richard Larson, Lance Stover, Jaewoo Nam, Andrew Habermas
  • Publication number: 20100096669
    Abstract: An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Applicant: QIMONDA AG
    Inventors: Martin Popp, Till Schloesser
  • Publication number: 20100078737
    Abstract: A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventor: Kao-Way Tu
  • Patent number: 7683403
    Abstract: A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: March 23, 2010
    Assignee: STMicroelectronics, Inc.
    Inventor: Anshuman Tripathi
  • Publication number: 20100066440
    Abstract: Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the channel region, and a conductive member disposed opposite of the channel region from the gate. The conductive member may not overlap the source, the drain, or both the source and the drain.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 18, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Werner Juengling
  • Publication number: 20100038683
    Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Inventors: Ajit Shanware, Srikanth Krishnan
  • Publication number: 20100006976
    Abstract: This invention provides a semiconductor device having a capacitor with reduced deterioration of dielectric constant and reduced leakage between upper and lower electrodes and a manufacturing method of such a semiconductor device. A capacity structure is configured by sequentially stacking a lower electrode, a capacitive insulation film, and an upper electrode on wiring or a contact plug. The capacity structure is of a thin-film capacitor structure having, at the interface between the lower electrode and the capacitive insulation film, a thin metal film having insulating properties and exhibiting a high dielectric constant.
    Type: Application
    Filed: February 27, 2008
    Publication date: January 14, 2010
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20090323387
    Abstract: A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug.
    Type: Application
    Filed: June 26, 2008
    Publication date: December 31, 2009
    Applicant: ART TALENT INDUSTRIAL LIMITED
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Publication number: 20090316463
    Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventor: Michael Sommer
  • Patent number: 7629616
    Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: December 8, 2009
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Kent Bertilsson, Andrei Konstantinov
  • Publication number: 20090261451
    Abstract: An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a first surface of the substrate and in electrical contact with the first terminal. A second conductive layer is disposed on a second surface of the substrate. A first electrically insulating layer is disposed on the second conductive layer and substantially covers the second conductive layer. The first electrically insulating layer includes an aperture. A fuse element is disposed on the first electrically insulating layer and is in electrical contact with the second conductive layer through the aperture and in electrical contact with the second terminal. The fuse element is in electrical series with the resistive material. A second electrically insulating layer is disposed over the fuse element.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: Littlefuse, Inc.
    Inventor: Stephen J. Whitney
  • Publication number: 20090250726
    Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 8, 2009
    Applicant: Sidense Corp.
    Inventor: Wlodek KURJANOWICZ
  • Publication number: 20090236636
    Abstract: A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 24, 2009
    Inventor: Hsiu-Wen Hsu
  • Patent number: 7592653
    Abstract: An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor gate. This may cause edges of the stress liner to be adjacent to and on either side of the channel, thus, increasing the stress effect. To produce this stress liner structure, the stress liner may be applied and then a portion of the stress liner is modified to reduce the stress in that portion, such as through ion implantation. The stress liner portion may be modified to have a reduced stress by, for example, implanting certain ions such as germanium or xenon ions therein.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 22, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Gaku Sudo
  • Patent number: 7586141
    Abstract: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a capacitor formed above the first silicide film and electrically connected to the first silicide film; and a second silicide film formed in an upper surface of the fourth impurity region and having a larger t
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 8, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Hiroki Shinkawata
  • Publication number: 20090218600
    Abstract: A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for numerous memory elements based on memory-specific parameters, and determining a layout for a front-end-of-line (FEOL) component of the integrated circuit based on electrical parameters. Once these two layouts are determined, the layouts are combined to produce a layout for a memory cell on the integrated circuit.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Human Park, Ulrich Klostermann
  • Publication number: 20090213660
    Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.
    Type: Application
    Filed: March 5, 2009
    Publication date: August 27, 2009
    Applicant: Tower Semiconductor Ltd.
    Inventors: Evgeny Pikhay, Yakov Roizin
  • Publication number: 20090189461
    Abstract: An integrated circuit includes a first transistor having a first gate and a first source and a second transistor having a second gate and a second source. The integrated circuit includes a first source contact adjacent the second transistor and coupled to the first source and the second source. The integrated circuit includes a first bond wire coupled to the first source contact.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow