Controllable By Variation Of Magnetic Field Applied To Device (epo) Patents (Class 257/E29.323)
  • Patent number: 8559214
    Abstract: A magnetic memory cell is provided with a magnetization record layer and a magnetic tunnel junction section. The magnetization record layer is a ferromagnetic layer having a perpendicular magnetic anisotropy. The magnetic tunnel junction section is used to read data from the magnetization record layer. The magnetization record layer has a plurality of domain wall motion regions.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: October 15, 2013
    Assignee: NEC Corporation
    Inventors: Shunsuke Fukami, Kiyokazu Nagahara, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Norikazu Ohshima
  • Patent number: 8557610
    Abstract: Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 15, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Wei-Chuan Chen, Xia Li, Seung H. Kang
  • Publication number: 20130264665
    Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Guenole Jan, Ru-Ying Tong
  • Publication number: 20130264620
    Abstract: A method of forming a barrier/liner for ferroelectric memory capacitors includes chemical vapor depositing 15 to 40 A of a first layer including a refractory metal nitride over a substrate having a plurality of metal-oxide-semiconductor (MOS) gate structures, ferroelectric memory (FeRAM) capacitors, and vias in a dielectric layer overlying the substrate. The first layer is treated using a first plasma treatment including exposing the first layer to a plasma in an atmosphere substantially-free of hydrogen. A 15 to 40 A thick second refractory metal nitride layer is chemical vapor deposited of over the first layer. The second layer is treated using a second plasma treatment including exposing the second layer to a plasma in an atmosphere substantially-free of hydrogen.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhiyi Yu, Ollen Harvey Mullis, John Paul Campbell
  • Patent number: 8547730
    Abstract: The method and system for providing a spin tunneling element are disclosed. The method and system include depositing a pinned layer, a barrier layer, and a free layer. The barrier layer has a first crystal structure and a texture. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The first ferromagnetic is adjacent to the second ferromagnetic layer and between the second ferromagnetic layer and the barrier layer. The first ferromagnetic layer has the first crystal structure and the texture, while the second ferromagnetic layer has a second crystal structure different from the first crystal structure.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 1, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yong Shen, Qunwen Leng
  • Patent number: 8546151
    Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Haruo Furuta, Shuichi Ueno, Ryoji Matsuda, Tatsuya Fukumura, Takeharu Kuroiwa, Lien-Chang Wang, Eugene Chen, Yiming Huai
  • Patent number: 8546896
    Abstract: A method and system for providing a magnetic substructure usable in a magnetic device, as well as a magnetic element and memory using the substructure are described. The magnetic substructure includes a plurality of ferromagnetic layers and a plurality of nonmagnetic layers. The plurality of ferromagnetic layers are interleaved with the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are immiscible with and chemically stable with respect to the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are substantially free of a magnetically dead layer-producing interaction with the plurality of nonmagnetic layers. Further, the plurality of nonmagnetic layers induce a perpendicular anisotropy in the plurality of ferromagnetic layers. The magnetic substructure is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic substructure.
    Type: Grant
    Filed: November 6, 2010
    Date of Patent: October 1, 2013
    Assignee: Grandis, Inc.
    Inventors: Daniel Lottis, Eugene Youjun Chen, Xueti Tang, Steven M. Watts
  • Publication number: 20130249026
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic film having a variable magnetization direction, a second magnetic film having an invariable magnetization direction, and a magnesium oxide film provided between the first magnetic film and the second magnetic film and being in contact with both the first magnetic film and the second magnetic film, and doped with at least one element selected from a first group consisting of copper, silver, and gold.
    Type: Application
    Filed: September 18, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eiji KITAGAWA, Tadaomi DAIBOU, Yushi KATO
  • Publication number: 20130250661
    Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Wayne I. Kinney
  • Patent number: 8541247
    Abstract: An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 24, 2013
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Antoine Khoueir, Brian Lee, Patrick J. Ryan
  • Patent number: 8542519
    Abstract: According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Takeshi Kajiyama, Kuniaki Sugiura
  • Patent number: 8541855
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: September 24, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Publication number: 20130241014
    Abstract: A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
  • Publication number: 20130240963
    Abstract: An STT MTJ cell is formed with a magnetic anisotropy of its free and reference layers that is perpendicular to their planes of formation. The reference layer of the cell is an SAF multilayered structure with a single magnetic domain to enhance the bi-stability of the magnetoresistive states of the cell. The free layer of the cell is etched back laterally from the reference layer, so that the fringing stray field of the reference layer is no more than 15% of the coercivity of the free layer and has minimal effect on the free layer.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Robert Beach, Guenole Jan, Yu-Jen Wang, Witold Kula, Po-Kang Wang
  • Publication number: 20130239702
    Abstract: One embodiment of the present invention relates to a device, such as a sensor device. The device includes a sensor die and a circuit die. The sensor die includes a sensor and a feedback component. The circuit die includes circuitry. The circuit die is varied from the sensor die, such as comprising a varied substrate material. The circuitry is coupled to the sensor and the feedback component. The circuitry and the feedback component can communicate correlation information.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Patent number: 8536668
    Abstract: A magnetic layer that includes a seed layer comprising at least tantalum and a free magnetic layer comprising at least iron. The free magnetic layer is grown on top of the seed layer and the free magnetic layer is perpendicularly magnetized. The magnetic layer may be included in a magnetic tunnel junction (MTJ) stack.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 8530988
    Abstract: Embodiments generally relate to a magnetic read sensor and a method for its manufacture. A multi-layer insulating material may be used to cover both the first shield layer and also the sidewalls of the sensor structure in the magnetic read sensor. The first insulating layer of the multi-layer insulating material may be deposited by an ion beam sputtering process in a chamber that does not have any oxygen gas flowing into it so that oxygen diffusion into the sensor structure is reduced or eliminated. Then, a second insulating layer of the multi-layer insulating material may be deposited by atomic layer deposition such that the second insulating layer has a greater quality than the first insulating layer. The higher quality increases the breakdown voltage for the magnetic read sensor. Thus, the magnetic read sensor of the present invention has an effective insulating portion that increases the breakdown voltage without sensor damage.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Liubo Hong, Guangli Liu
  • Patent number: 8530987
    Abstract: A magnetic memory includes a magnetoresistive element. The magnetoresistive element includes a reference layer having an invariable magnetization direction, a storage layer having a variable magnetization direction, and a spacer layer provided between the reference layer and the storage layer. The storage layer has a multilayered structure including first and second magnetic layers, the second magnetic layer is provided between the first magnetic layer and the spacer layer and has a magnetic anisotropy energy lower than that of the first magnetic layer, and an exchange coupling constant Jex between the first magnetic layer and the second magnetic layer is not more than 5 erg/cm2.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Aikawa, Tadashi Kai, Masahiko Nakayama, Sumio Ikegawa, Naoharu Shimomura, Eiji Kitagawa, Tatsuya Kishi, Jyunichi Ozeki, Hiroaki Yoda, Satoshi Yanagi
  • Patent number: 8531875
    Abstract: According to one embodiment, a magnetic memory includes at least one memory cell including a magnetoresistive element, and first and second electrodes. The element includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a third magnetic layer provided on the second magnetic layer and having a magnetization antiparallel to the magnetization direction of the second magnetic layer. A diameter of an upper surface of the first magnetic layer is smaller than that of a lower surface of the tunnel barrier layer. A diameter of a lower surface of the second magnetic layer is not more than that of an upper surface of the tunnel barrier layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Yanagi, Eiji Kitagawa, Masahiko Nakayama, Jyunichi Ozeki, Hisanori Aikawa, Naoharu Shimomura, Masatoshi Yoshikawa, Minoru Amano, Shigeki Takahashi, Hiroaki Yoda
  • Publication number: 20130228882
    Abstract: Methods and apparatuses for a magnetic tunnel junction (MTJ) which can be used in as a magnetic random access memory cell are disclosed. The MTJ comprises a free layer and an insulator layer. The MTJ further comprises a pinned layer with a first region, a second region, and a third region. The second region is of a first length and of a first thickness, and the first region and the third region are of a second length and of a second thickness. A ratio of the first thickness to the second thickness may be larger than 1.2. A ratio of the second length to the first length is larger than 0.5. The first thickness may be larger than a spin diffusion length of a material for the pinned layer. So formed MTJ results in increased tunneling magnetic resistance ratio and reduced critical switch current of the MTJ.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Wen Cheng, Chwen Yu, Chih-Ming Chen
  • Patent number: 8524511
    Abstract: A CMOS device is provided in a substrate. A magnetic tunnel junction (MTJ) is provided over the CMOS device and connected to the CMOS device by a metal ring contact wherein a dielectric or other filling material forms the center of the metal ring contact and wherein a bottom of the metal ring contact underlying said filling material is metal.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 3, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Tom Zhong, Vinh Lam, Zhongjian Teng
  • Patent number: 8524510
    Abstract: A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 um or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Misumi, Masahiro Shimizu, Tsuyoshi Koga, Tatsuhiko Akiyama, Tomohiro Murakami
  • Patent number: 8525280
    Abstract: An MRAM array of MTJ memory cells is provided wherein each such cell is a layered MTJ structure located at an intersection of a word and bit line and has a small circular horizontal cross-section of 1.0 microns or less in diameter and wherein the ferromagnetic free layer of each such cell has a magnetic anisotropy produced by a magnetic coupling with a thin antiferromagnetic layer that is formed on the free layer. The array of MTJ memory cells so provided is far less sensitive to shape irregularities and edge defects of individual cells than arrays of the prior art.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 3, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Tai Min, Cheng Horng, Po Kang Wang
  • Publication number: 20130221461
    Abstract: A ferromagnetic tunnel junction structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer includes a crystalline non-magnetic material having constituent elements that are similar to those of an crystalline oxide that has spinel structure as a stable phase structure; the non-magnetic material has a cubic structure having a symmetry of space group Fm-3m or F-43m in which atomic arrangement in the spinel structure is disordered; and an effective lattice constant of the cubic structure is substantially half of the lattice constant of the oxide of the spinel structure.
    Type: Application
    Filed: September 26, 2012
    Publication date: August 29, 2013
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventor: National Institute for Materials Science
  • Publication number: 20130221459
    Abstract: A magnetic element is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction (MTJ). The free layer may be a single layer or a composite and is comprised of one or more glassing agents that have a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. As a result, a CoFeB free layer, for example, selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Guenole Jan, Yu-Jen Wang, Tong Ru Ying
  • Publication number: 20130221460
    Abstract: A magnetic element in a spintronic device or serving as a propagation medium in a domain wall motion device is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction. The free layer may be a single layer or a composite and is comprised of a glassing agent that has a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. A CoFeB free layer selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region.
    Type: Application
    Filed: July 13, 2012
    Publication date: August 29, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Guenole Jan, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 8518562
    Abstract: A magnetic storage device stable in write characteristic is provided. A first nonmagnetic film is provided over a recording layer. A first ferromagnetic film is provided over the first nonmagnetic film and has a first magnetization and a first film thickness. A second nonmagnetic film is provided over the first ferromagnetic film. A second ferromagnetic film is provided over the second nonmagnetic film, is coupled in antiparallel with the first ferromagnetic film, and has a second magnetization and a second film thickness. An antiferromagnetic film is provided over the second ferromagnetic film. The sum of the product of the first magnetization and the first film thickness and the product of the second magnetization and the second film thickness is smaller than the product of the magnetization of the recording layer and the film thickness of the recording layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: August 27, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Takenaga, Takeharu Kuroiwa, Hiroshi Takada, Ryoji Matsuda, Yosuke Takeuchi
  • Patent number: 8519498
    Abstract: A magnetic cell includes a ferromagnetic free layer having a free magnetization orientation direction and a first ferromagnetic pinned reference layer having a first reference magnetization orientation direction that is parallel or anti-parallel to the free magnetization orientation direction. A first oxide barrier layer is between the ferromagnetic free layer and the first ferromagnetic pinned reference layer. The magnetic cell further includes a second ferromagnetic pinned reference layer having a second reference magnetization orientation direction that is orthogonal to the first reference magnetization orientation direction. The ferromagnetic free layer is between the first ferromagnetic pinned reference layer and the second ferromagnetic pinned reference layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 27, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Zheng Gao, Wenzhong Zhu, Wonjoon Jung, Haiwen Xi
  • Patent number: 8519497
    Abstract: A device comprising a diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and the diblock copolymer mask, the diblock copolymer mask comprising a first plurality of uniform shapes formed on and registered to the template.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventor: Michael C. Gaidis
  • Publication number: 20130214365
    Abstract: An assembly (20) includes a MEMS die (22) having a pressure transducer device (40) formed on a substrate (44) and a cap layer (38). A packaging process (74) entails forming the device (40) on the substrate, creating an aperture (70) through a back side (58) of the substrate (44) underlying a diaphragm (46) of the device (40), and coupling a cap layer (38) to the front side of the substrate (44) overlying the device (40). A trench (54) is produced extending through both the cap layer (38) and the substrate (44), and surrounds a cantilevered platform (48) at which the diaphragm (46) resides. The die (22) is suspended above a substrate (26) so that a clearance space (60) is formed between the platform (48) and the substrate (26). The diaphragm (46) is exposed to an external environment (68) via the aperture (70) and the space (60), and an external port.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mark E. Schlarmann, Yizhen Lin
  • Patent number: 8514608
    Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 20, 2013
    Assignee: Seagate Technology LLC
    Inventor: Maroun Georges Khoury
  • Patent number: 8513748
    Abstract: A magnetic film stack is composed of a synthetic antiferromagnet including a plurality of ferromagnetic layers, adjacent two of which are antiferromagnetically coupled through a non-magnetic layer; and a reversal inducing layer exhibiting ferromagnetism. The reversal inducing layer is ferromagnetically coupled to the synthetic antiferromagnet, and designed to have a coercive field smaller than a magnetic field at which antiferromagnetic coupling within the synthetic antiferromagnet starts to be decoupled.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: August 20, 2013
    Assignee: NEC Corporation
    Inventor: Yoshiyuki Fukumoto
  • Patent number: 8513752
    Abstract: A magnetic tunnel junction includes an amorphous ferromagnetic reference layer having a first reference layer side and an opposing second reference layer side. The first reference layer side has a greater concentration of boron than the second reference layer side. A magnesium oxide tunnel barrier layer is disposed on the second side of the amorphous ferromagnetic reference layer. The magnesium oxide tunnel barrier layer has a crystal structure. An amorphous ferromagnetic free layer is disposed on the magnesium oxide tunnel barrier layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 20, 2013
    Assignee: Seagate Technology LLC
    Inventors: Xilin Peng, Konstantin Nikolaev, Taras Pokhil, Victor Sapazhnikov, Yonghua Chen
  • Patent number: 8514616
    Abstract: A magnetoresistive effect element includes: a magnetization free layer; a non-magnetic insertion layer provided adjacent to the magnetization free layer; a magnetic insertion layer provided adjacent to the non-magnetic insertion layer and opposite to the magnetization free layer with respect to the non-magnetic insertion layer; a spacer layer provided adjacent to the magnetic insertion layer and opposite to the non-magnetic insertion layer with respect to the magnetic insertion layer; and a first magnetization fixed layer provided adjacent to the spacer layer and opposite to the magnetic insertion layer with respect to the spacer layer. The magnetization free layer and the first magnetization fixed layer have magnetization components in directions approximately perpendicular to a film surface. The magnetization free layer includes two magnetization fixed portions and a domain wall motion portion arranged between the two magnetization fixed portions.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: August 20, 2013
    Assignee: NEC Corporation
    Inventors: Nobuyuki Ishiwata, Norikazu Ohshima, Shunsuke Fukami, Kiyokazu Nagahara, Tetsuhiro Suzuki
  • Publication number: 20130207209
    Abstract: A top-pinned magnetic tunnel junction device with perpendicular magnetization, including a bottom electrode, a non-ferromagnetic spacer, a free layer, a tunneling barrier, a synthetic antiferromagnetic reference layer and a top electrode, is provided. The non-ferromagnetic spacer is located on the bottom electrode. The free layer is located on the non-ferromagnetic spacer. The tunnel insulator is located on the free layer. The synthetic antiferromagnetic reference layer is located on the tunneling barrier. The synthetic antiferromagnetic reference layer includes a top reference layer located on the tunneling barrier, a middle reference layer located on the bottom reference layer and a bottom reference layer located on the tunneling barrier. The magnetization of the top reference layer is larger than that of the bottom reference layer. The top electrode is located on the synthetic antiferromagnetic reference layer.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 15, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yung-Hung Wang, Kuei-Hung Shen, Ding-Yeong Wang, Shan-Yi Yang
  • Patent number: 8508006
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: August 13, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8507385
    Abstract: A method for processing a thin film micro device on a substrate includes: 1) depositing a carbon film on the substrate as a sacrificial layer; 2) photolithographically defining a first predetermined pattern in the carbon film; 3) etching an unwanted portion of the carbon film outside the first predetermined pattern; 4) depositing a structural film including a single or multiple layers of solid state materials; 5) photolithographically defining a second predetermined pattern in the structural film; 6) etching the discarded portion of the structural film outside the second predetermined pattern; 7) selectively removing the remaining portion of the sacrificial carbon film by using a selective etch process gas in a reactor chamber, so that the overlapped portion of the remaining structural element with the first predetermined pattern is suspended above an underneath cavity above the substrate.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: August 13, 2013
    Assignee: Shanghai Lexvu Opto Microelectronics Technology Co., Ltd.
    Inventor: Deming Tang
  • Publication number: 20130201757
    Abstract: A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.
    Type: Application
    Filed: August 16, 2012
    Publication date: August 8, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Wenqing Wu, Jung Pill Kim, Xiaochun Zhu, Seung H. Kang, Raghu Sagar Madala, Kendrick H. Yuen
  • Publication number: 20130200475
    Abstract: A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Wei Chiang, Chwen Yu, Ya-Chen Kao
  • Patent number: 8502186
    Abstract: A semiconductor memory device includes an isolation layer formed in a substrate and defining an active region, a trench formed in the substrate and defining a part of the active region as an active pillar; a word line formed inside the trench, a sub-source line formed under the trench and crossing the word line, a main source line formed over the substrate, coupled to the sub-source line, and crossing the word line, a variable resistor pattern formed over the active pillar, and a bit line contacting the variable resistor pattern and crossing the word line.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: August 6, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Woong Chung
  • Patent number: 8502332
    Abstract: A magnetic sensor 1 comprises a main channel layer 7a having first, second, and third regions 71, 72, 73 and extending in a first direction; a first ferromagnetic layer 12A mounted on the first region 71; a second ferromagnetic layer 12B mounted on the second region 72; a projection channel layer 7b projecting in a direction perpendicular to a thickness direction of the main channel layer 7a from a side face of the third region 73 between the first and second regions 71, 72 in the main channel layer 7a; and a magnetic shield S covering both sides in the thickness direction of the projection channel layer 7b and both sides in the first direction of the projection channel layer 7b and exposing an end face 7c in the projecting direction of the projection channel layer 7b.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 6, 2013
    Assignee: TDK Corporation
    Inventors: Tomoyuki Sasaki, Tohru Oikawa
  • Patent number: 8502331
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Tadaomi Daibou, Yutaka Hashimoto, Masaru Tokou, Tadashi Kai, Makoto Nagamine, Toshihiko Nagase, Katsuya Nishiyama, Koji Ueda, Hiroaki Yoda, Kay Yakushiji, Shinji Yuasa, Hitoshi Kubota, Taro Nagahama, Akio Fukushima, Koji Ando
  • Patent number: 8497139
    Abstract: A magnetic memory device including a memory layer having a vertical magnetization on the layer surface, of which the direction of magnetization is changed according to information; and a reference layer provided against the memory layer, and being a basis of information while having a vertical magnetization on the layer surface, wherein the memory device memorizes the information by reversing the magnetization of the memory layer by a spin torque generated when a current flows between layers made from the memory layer, the nonmagnetization layer and the reference layer, and a coercive force of the memory layer at a memorization temperature is 0.7 times or less than a coercive force at room temperature, and a heat conductivity of a center portion of an electrode formed on one side of the memory layer in the direction of the layer surface is lower than a heat conductivity of surroundings thereof.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20130187247
    Abstract: A spin-torque transfer (STT) magnetic tunnel junction (MTJ) memory includes a unitary fixed magnetic layer, a magnetic barrier layer on the unitary fixed magnetic layer, a free magnetic layer having a plurality of free magnetic islands on the magnetic barrier layer, and a cap layer overlying the free magnetic layer. Also a method of forming an STT-MTJ memory.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Wenqing WU, Sean Li, Xiaochun Zhu, Raghu Sagar Madala, Seung H. Kang, Kendrick H. Yuen
  • Publication number: 20130188418
    Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Wei CHIANG, Kai-Chun LIN, Ya-Chen KAO, Hung-Chang YU
  • Patent number: 8492809
    Abstract: The present invention provides a spin injection electrode structure, a spin transport element, and a spin transport device which enable effective spin injection in a silicon channel layer at room temperature. A spin injection electrode structure IE comprises a silicon channel layer 12, a first magnesium oxide film 13A disposed on a first part of the silicon channel layer 12, and a first ferromagnetic layer 14A disposed on the first magnesium oxide film 13A. The first magnesium oxide film 13A partly includes a first lattice-matched part P lattice-matched with both of the silicon channel layer 12 and the first ferromagnetic layer 14A.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 23, 2013
    Assignees: TDK Corporation, Akita Prefecture
    Inventors: Tomoyuki Sasaki, Tohru Oikawa, Kiyoshi Noguchi, Toshio Suzuki
  • Patent number: 8492858
    Abstract: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer over the MTJ cap layer. The top electrode layer includes a first nitrified metal.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: July 23, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang
  • Patent number: 8492859
    Abstract: A magnetic tunnel junction (MTJ) includes first and second magnetic layers; a tunnel barrier located between the first and second magnetic layers; a first spacer layer located between the first magnetic layer and the tunnel barrier, the first spacer layer comprising a non-magnetic material; and a first interfacial layer located between the first spacer layer and the tunnel barrier.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventor: Guohan Hu
  • Publication number: 20130181304
    Abstract: Methods and apparatus to provide an integrated circuit package having a conductive leadframe, a non-conductive die paddle mechanically coupled to the leadframe, and a die disposed on the die paddle and electrically connected to the leadframe. With this arrangement, eddy currents are reduced near the magnetic field transducer to reduce interference with magnetic fields.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: ALLEGRO MICROSYSTEMS, INC.
    Inventors: Shaun D. Milano, Michael C. Doogue, William P. Taylor
  • Patent number: 8487390
    Abstract: A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: July 16, 2013
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Ivan Petrov Ivanov, Shuiyuan Huang, Antoine Khoueir, Brian Lee, John Daniel Stricklin, Olle Gunnar Heinonen, Insik Jin