Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.

Abstract: A power semiconductor device includes a substrate, including an active region and edge regions, including a semiconductor layer of a first conductive type including silicon carbide (SiC); an insulating film disposed on the edge regions; a field plate pattern disposed on the insulating film; a first doped region of a second conductive type disposed inside the substrate to extend downward from a top surface of the edge regions; a second doped region of the second conductive type, buried in the edge regions, extends in a direction having a vector component parallel to the top surface of the substrate; and a third doped region of the first conductive type is disposed on the second doped region and at a side portion of the first doped region.

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by forming an array of transistors, where a column of the array includes a source line contacting the source contact of each transistor of the column, forming a spin-orbit-torque (SOT) line contacting the drain contacts of the transistors of the row, and forming an array of unit cells, each unit cell including a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, where the SOT-MRAM cell stack includes a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure.

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: An integrated circuit structure includes: a well region having a first conductivity type; a semiconductor structure extending away from the well region from a major surface of the well region, the semiconductor structure having the first conductivity type; a source/drain feature disposed on the semiconductor structure, the source/drain feature having a second conductivity type different from the first conductivity type; an isolation layer laterally surrounding at least a portion of the semiconductor structure; a dielectric layer disposed on the isolation layer, where at least a portion of the source/drain feature is disposed in the dielectric layer; and a conductive plug continuously extending through the dielectric layer and the isolation layer to physically contact the major surface of the well region, wherein the conductive plug is coupled to a power supply line to bias the well region.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A temperature-sensing device configured to monitor a temperature is disclosed. The temperature-sensing device includes: a first capacitor comprising a first oxide layer with a first thickness; a second capacitor comprising a second oxide layer with a second thickness, wherein the second thickness of the second oxide layer is different from the first thickness of the first oxide layer; and a control logic circuit, coupled to the first and second capacitors, and configured to determine whether the monitored temperature is equal to or greater than a threshold temperature based on whether at least one of the first and second oxide layers breaks down.

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

Abstract: A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material.

Abstract: A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate.

Abstract: A method of forming a stacked low temperature diode and related devices. At least some of the illustrative embodiments are methods comprising forming a metal interconnect disposed within an inter-layer dielectric. The metal interconnect is electrically coupled to at least one underlying integrated circuit device. A barrier layer is deposited on the metal interconnect and the inter-layer dielectric. A semiconductor layer is deposited on the barrier layer. A metal layer is deposited on the semiconductor layer. The barrier layer, the semiconductor layer, and the metal layer are patterned. A low-temperature anneal is performed to induce a reaction between the patterned metal layer and the patterned semiconductor layer. The reaction forms a silicided layer within the patterned semiconductor layer. Moreover, the reaction forms a P-N junction diode.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner, wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.

Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.

Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A novel electrical circuit protection design with dielectrically-isolated diode configuration and architecture is disclosed. In one embodiment of the invention, a plurality of diodes connected in series is monolithically integrated in a single piece of semiconductor substrates by utilizing dielectrically-isolated trenching and silicon-on-insulator substrates, which enable formation of “silicon islands” to insulate a diode structure electrically from adjacent structures. In one embodiment of the invention, the plurality of diodes connected in series includes at least one Zener diode, which provides a clamping voltage approximately equal to its breakdown voltage value in case of a voltage spike or a power surge event.

Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.

Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.

Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.

Abstract: The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices.

Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract: The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity.

Abstract: To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.

Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.

Abstract: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

Abstract: A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.

Abstract: A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body between a first and a second doped terminal zone. At least one field electrode is provided, which is arranged in the drift zone, extends into the drift zone proceeding from the first side and is configured in a manner electrically insulated from the semiconductor body.

Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.

Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.

Abstract: Various circuit devices, including diodes, and methods manufacturing therefor are provided. In one aspect, a method manufacturing is provided that includes forming a gate structure on a semiconductor portion of a substrate. The semiconductor portion has a first conductivity type. First and spacer structures are formed on opposite sides of the gate structure. A first impurity region of a second conductivity type is formed proximate the first spacer structure while the semiconductor portion lateral to the second spacer structure is masked. The first impurity region and the semiconductor portion define a junction. A width of the second spacer structure is reduced while the second spacer structure and the first impurity region are masked. A second impurity region of the first conductivity type is formed in the semiconductor portion proximate the second spacer structure. The method provides a diode with reduced series resistance.