Diode (epo) Patents (Class 257/E29.327)
  • Patent number: 11705486
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Patent number: 9035434
    Abstract: A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 9006702
    Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Swapnil A. Lengade
  • Patent number: 8975661
    Abstract: An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Benjamin Morillon
  • Patent number: 8946038
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8941191
    Abstract: A radio frequency microelectromechanical (RF MEMS) device can comprise an actuation p-n junction and a sensing p-n junction formed within a semiconductor substrate. The RF MEMS device can be configured to operate in a mode in which an excitation voltage is applied across the actuation p-n junction varying a non-mobile charge within the actuation p-n junction to modulate an electric field acting upon dopant ions and creating electrostatic forces. The electrostatic forces can create a mechanical motion within the actuation p-n junction. The mechanical motion can modulate a depletion capacitance of the sensing p-n junction, thereby creating a motional current. At least one of the p-n junctions can be located at an optimal location to maximize the efficiency of the RF MEMS device at high resonant frequencies.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 27, 2015
    Assignee: Cornell University
    Inventors: Eugene Hwang, Sunil Ashok Bhave
  • Patent number: 8933532
    Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Patent number: 8896084
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: November 25, 2014
    Assignees: Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8890186
    Abstract: A molded resin product or the like that is provided with a phosphor layer made of gel-like or rubber-like resin that can maintain its shape for a long period and that can be implemented easily. The molded resin product (phosphor layer 7) includes a resin member 17 made of a gel-like or rubber-like translucent resin including a phosphor material. The resin member 17 includes a shape maintaining member 19 that is formed in a lattice shape by line-like members 20 that are made of a material having a higher elasticity modulus than the resin member 17. The molded resin product (phosphor layer 7) is in the shape of a dome. The translucent resin is made of, for example, silicon resin, and the resin member 17 is gel-like.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshifumi Ogata, Nobuyuki Matsui, Masumi Abe
  • Patent number: 8860025
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans-Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8823139
    Abstract: A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8822978
    Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 2, 2014
    Assignee: The State of Oregon Acting by and through...
    Inventors: E. William Cowell, III, John F. Wager, Brady J. Gibbons, Douglas A. Keszler
  • Patent number: 8759878
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Akira Yoshioka, Wataru Saito
  • Patent number: 8759935
    Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8742506
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 8742534
    Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 3, 2014
    Assignee: DENSO CORPORATION
    Inventors: Takao Yamamoto, Norihito Tokura, Hisato Kato, Akio Nakagawa
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Publication number: 20140110814
    Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8698194
    Abstract: A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 15, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takuo Nagase, Junichi Sakano
  • Patent number: 8686470
    Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventor: Hans-Martin Ritter
  • Patent number: 8669554
    Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily p-type doped thin film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: March 11, 2014
    Inventor: Ho-Yuan Yu
  • Patent number: 8664699
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 4, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Publication number: 20140043096
    Abstract: Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Inventor: Adrian FINNEY
  • Patent number: 8643085
    Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Frank Pfirsch
  • Publication number: 20130334648
    Abstract: High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 8610241
    Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • Patent number: 8581242
    Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 12, 2013
    Assignee: Atomic Energy Council—Institute of Nuclear Energy Research
    Inventors: Yueh-Mu Lee, Zun-Hao Shih, Hwen-Fen Hong
  • Patent number: 8581367
    Abstract: A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: November 12, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Tadahiro Okazaki
  • Publication number: 20130285208
    Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodorus Eduardus Standaert, Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Tenko Yamashita
  • Patent number: 8552530
    Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Amazing Microelectronics Corp.
    Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang, Ryan Hsin-Chin Jiang
  • Publication number: 20130241056
    Abstract: A well-through type diode element/component manufacturing method which has a pair (pairs) of first and said second electrodes of a diode element/component built on same plane by a process of metallization after a mode of well-through type to penetrate a PN junction depletion region/barrier region, and leads electrons of one of the electrodes to flow through the Depletion/Barrier region without hindrance; the present invention directly conduct the operations of insulation protecting, metallization and the process of elongate welding ball etc., it can independently complete a novel technique of Chip-Scale Package (CSP); it has the features of: grains being exactly the article produced, no need of connecting lines, low energy consumption, low cost and light, thin and small etc.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: FORMOSA MICROSEMI CO., Ltd.
    Inventors: Wen-Ping HUANG, Wen-Hu Wu, His-Piao Lai, Chien-Wu Chen
  • Patent number: 8531005
    Abstract: Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Whitfield, Changsoo Hong
  • Publication number: 20130187238
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.
    Type: Application
    Filed: June 11, 2012
    Publication date: July 25, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koji Shirai, Mariko Shimizu
  • Patent number: 8476721
    Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yang Li, Insik Jin, Harry Liu, Song S. Xue, Shuiyuan Huang, Michael X. Tang
  • Patent number: 8476736
    Abstract: A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8436337
    Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 7, 2013
    Assignee: The State of Oregon Acting By and Through The State Board of Higher Education on Behalf of Oregon State Unitiversity
    Inventors: E. William Cowell, III, John F. Wager, Brady J. Gibbons, Douglas A. Keszler
  • Publication number: 20130093038
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8421087
    Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kiyoshi Arai, Gourab Majumdar
  • Patent number: 8415773
    Abstract: A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration of a second dopant, a subsequent buffer layer, the third zone, also having the second dopant and a subsequent fourth zone having a high concentration of the second dopant. The fourth zone faces a second main area. In this case, the concentration of the second doping of the buffer layer is higher at the first interface of the barrier layer with the second zone than at the second interface with the fourth zone. According to the invention, the buffer layer is produced by ion implantation.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: April 9, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Bernhard Koenig
  • Publication number: 20130075877
    Abstract: A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×1018 cm?3.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: DENSO CORPORATION
    Inventors: Takeshi SAKAI, Akira Yamada, Shigeki Takahashi, Youichi Ashida, Satoshi Shiraki
  • Publication number: 20130056731
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8384186
    Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 26, 2013
    Assignee: ABB Technology AG
    Inventors: Sven Matthias, Arnost Kopta
  • Patent number: 8378382
    Abstract: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 19, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chao-I Wu, Ming Hsiu Lee
  • Patent number: 8377757
    Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 19, 2013
    Assignee: Shanghai SIM-BCD Semiconductor Manufacturing Limited
    Inventors: Francis Edward Hawe, Jinsui Liang, Xiaoqiang Cheng, Xianfeng Liu
  • Publication number: 20130039116
    Abstract: A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such that the free end is electrically connected to either the storage electrode or an opposite release electrode.
    Type: Application
    Filed: July 24, 2012
    Publication date: February 14, 2013
    Inventors: Holger Kropp, Meinolf Blawat
  • Publication number: 20130037852
    Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.
    Type: Application
    Filed: July 13, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro TAMAKI
  • Patent number: 8373253
    Abstract: A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: February 12, 2013
    Assignee: System General Corp.
    Inventors: Han-Chung Tai, Hsin-Chih Chiang
  • Patent number: 8368178
    Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Patent number: 8350289
    Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanori Tsukuda
  • Publication number: 20120319283
    Abstract: A semiconductor device includes a semiconductor element including an anode electrode and a cathode electrode, an encapsulating material which covers the semiconductor element, a first external electrode which is electrically connected to the cathode electrode and is at least partially exposed outside of the encapsulating material, a second external electrode which is electrically connected to the anode electrode and is at least partially exposed outside of the encapsulating material, and a sacrificial metallic body which is arranged outside of the encapsulating material so as to be in direct contact with the first external electrode or to be electrically connected to the first external electrode through saltwater, and contains metal having larger ionization tendency than any metal contained in the first external electrode.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: Sanken Electric Co., Ltd.
    Inventor: Toru KANNO