Controllable Only By Variation Of Electric Current Supplied Or Only Electric Potential Applied To Electrode Carrying Current To Be Rectified, Amplified, Oscillated, Or Switched (epo) Patents (Class 257/E29.325)
  • Patent number: 9577032
    Abstract: A groove for air ventilation is formed in a rib with a substantially rectangular ring shape which is provided so as to surround a concave portion provided in a rear surface of a semiconductor chip. The groove is provided in each side or at each corner of the rib so as to traverse the rib from the inner circumference to the outer circumference of the rib. The depth of the groove is equal to or less than the depth of the concave portion provided in the rear surface of the chip. In this way, it is possible to reliably solder a semiconductor device, in which the concave portion is provided in the rear surface of the semiconductor chip and the rib is provided in the outer circumference of the concave portion, to a base substrate, without generating a void in a drain electrode provided in the concave portion.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenichi Iguchi
  • Patent number: 9035273
    Abstract: A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 19, 2015
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Sakyo Hirose
  • Patent number: 8975612
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Renate Hofmann, Carsten Ahrens, Wolfgang Klein, Alexander Glas
  • Patent number: 8963285
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Anton Steltenpohl
  • Patent number: 8951818
    Abstract: The present invention discloses a method for preparing switch transistor comprising: sequentially forming a control electrode, an insulation layer, an active layer, and a source/drain metal layer of the switch transistor on a glass substrate; patterning the source/drain metal layer to expose the active layer; and proceeding an etching process to the exposed active layer in a way of gradually reducing etching rate to form a channel of the switch transistor. The present invention further discloses an equipment for etching the switch transistor. In the way mentioned above, the present invention can minimize the damages to the switch transistor and improve the reliability of the switch transistor.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: February 10, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiangdeng Que
  • Patent number: 8907315
    Abstract: A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8907448
    Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 9, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Baoxing Chen
  • Patent number: 8853799
    Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Alan J. O'Donnell, Santiago Iriarte, Mark J. Murphy, Colin G. Lyden, Gary Casey, Eoin Edward English
  • Patent number: 8816473
    Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Arvind Kumar, Anthony I-Chih Chou, Renee T. Mo, Shreesh Narasimha
  • Patent number: 8816452
    Abstract: There is provided an electric device including a base member, a beam elastically deformable to bend upward and having an outline partially defined by a slit formed in the base member, a conductive pattern provided on a top surface of the beam, a contact electrode provided above the conductive pattern, the contact electrode coming into contact with the conductive pattern, and a bridge electrode elastically deformable, the bridge electrode connecting the conductive pattern and a portion of the base member outside the outline.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Tadashi Nakatani, Hisao Okuda, Takashi Katsuki
  • Patent number: 8779537
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 15, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger Klas Malmhall, Yuchen Zhou
  • Patent number: 8766400
    Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: July 1, 2014
    Inventor: Ching-Yu Ni
  • Patent number: 8766335
    Abstract: A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx>n is satisfied.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 1, 2014
    Assignee: Panasonic Corporation
    Inventor: Yoshiya Moriyama
  • Patent number: 8736021
    Abstract: In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: May 27, 2014
    Assignee: X-FAB Semiconductor Foundries AG
    Inventors: Tsui Ping Chu, Hyung Sun Yook, Poh Ching Sim
  • Patent number: 8710599
    Abstract: Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: April 29, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: David Lambe Marx, Cenk Acar, Sandeep Akkaraju, Janusz Bryzek
  • Publication number: 20140110821
    Abstract: A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Barry, Robert A. Groves, Venkata N.R. Vanukuru
  • Patent number: 8674451
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
  • Patent number: 8669638
    Abstract: A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: March 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Marie Boulay, Ayad Ghannam
  • Publication number: 20140061853
    Abstract: Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventor: Bucknell C. Webb
  • Patent number: 8659122
    Abstract: To provide a semiconductor device having a structure free from variations in resistance even when a stress is applied thereto; and a manufacturing method of the device. The semiconductor device has a metal resistor layer in a region between a passivation film and an uppermost level aluminum interconnect. This makes it possible to realize a high-precision resistor having few variations in resistance due to a mold stress that occurs in a packaging step or thereafter and therefore, makes it possible to form a high-precision analog circuit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Matsumura
  • Publication number: 20140035097
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Sheng-Jian Jou, Han-Chee Yen
  • Patent number: 8642460
    Abstract: A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephen A Cohen, Baozhen Li
  • Patent number: 8633565
    Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Ju Song, Seong-Ho Kim, Won-Mo Park, Gil-Sub Kim
  • Publication number: 20130313678
    Abstract: A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Publication number: 20130316646
    Abstract: In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Inventor: Peter Gerard Steeneken
  • Publication number: 20130307117
    Abstract: A thin-contour semiconductor device with a solenoid and iron core integrated into the device package. The solenoid windings are constructed by a stripe-shaped layer portion, deposited on the chip surface, and an arced wire portion welded to the layer portion by low-cost standard wire bonding technique. The stripes are arrayed parallel to each other, spaced apart respective insulating gaps. The arced wires span from one stripe to the adjacent next stripe by bridging the gap and keeping the clock direction constant. The arced solenoid windings are then integrated into the encapsulating device package. The ferromagnetic core may be shaped as a ring to allow the formation of a strong and nearly homogeneous magnetic field inside the solenoid, providing reliable energy storage for power supply circuits.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan KODURI
  • Patent number: 8587028
    Abstract: A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to adjust the switch between on and off operating states. The switch can be implemented as a radio frequency switch in a circuit.
    Type: Grant
    Filed: January 3, 2010
    Date of Patent: November 19, 2013
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 8564092
    Abstract: In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 22, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Lajos Burgyan, Marc Davis-Marsh
  • Patent number: 8558344
    Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: October 15, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Baoxing Chen
  • Publication number: 20130264679
    Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
    Type: Application
    Filed: April 5, 2012
    Publication date: October 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Arvind Kumar, Anthony I. Chou, Renee T. Mo, Shreesh Narasimha
  • Publication number: 20130221487
    Abstract: A resistor in a semiconductor memory device is formed by the steps of, inter alia: forming a first helical resistor extending from a first point toward a center in a clockwise or counterclockwise direction, forming a second helical resistor extending from the center to a second point in an opposite direction, wherein the first and second helical resistors are connected to each other at the center, and wherein the first and second helical resistors do not overlap.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 29, 2013
    Applicant: SK hynix Inc.
    Inventor: Jeong Guen PARK
  • Patent number: 8513771
    Abstract: A semiconductor package includes a semiconductor chip. An inductor is applied to the semiconductor chip. The inductor has at least one winding. An encapsulation body is formed of an encapsulation material. The encapsulation material contains a magnetic component and fills a space within the winding to form a magnetic winding core.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: August 20, 2013
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss, Georg Meyer-Berg
  • Patent number: 8476672
    Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.
    Type: Grant
    Filed: April 2, 2011
    Date of Patent: July 2, 2013
    Assignee: Peking University
    Inventors: Ru Huang, Lijie Zhang
  • Patent number: 8471358
    Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: June 25, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Hsien-Pin Hu, Sally Liu, Ming-Fa Chen, Jhe-Ching Lu
  • Patent number: 8470683
    Abstract: The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Christoph Dirnecker, Wolfgang Ploss
  • Publication number: 20130134558
    Abstract: A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Robert K. Speck, Kenneth B. Tull, Marjorie L. Miller
  • Publication number: 20130127011
    Abstract: Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Publication number: 20130127009
    Abstract: An spiral inductor (300) formed on a semiconductor substrate (102). One or more insulating layers (104, 303) is disposed on a first surface of the semiconductor substrate. A spiral structure (106) is formed of a first conductive material layer disposed on the insulating layer. The spiral structure has a terminal end (105) at a location enclosed by one or more coils of the spiral. A ground plane (302) is formed of a second conductive material and disposed on a second surface located on a side of the substrate opposed from the first surface. The ground plane is defected so as to define a signal trace (308) formed from a portion of the ground plane. A conductive via (304) extends through the one or more insulating layers, and through the semiconductor substrate, to form an electrical connection between the ground plane and the terminal end.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 23, 2013
    Applicant: HARRIS CORPORATION
    Inventor: David M. Smith
  • Publication number: 20130113074
    Abstract: A capacitor system and a method for producing a capacitor system. The capacitor system may be used in a power semiconductor module. In one embodiment, the capacitor system comprises a metal shaped body having a depression; a capacitor arranged at least partly in the depression; a spacer composed of electrically insulating material, the spacer being arranged at least partly between the capacitor and the metal shaped body in the depression; and an electrically insulating potting material provided in the depression, wherein the potting material fixes the capacitor in the depression so that the capacitor does not touch the metal shaped body.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: Semikron Elektronik GmbH & Ko. KG
    Inventors: Frank Ebersberger, Peter Beckedahl, Hartmut Kulas, Peter Schott
  • Patent number: 8426226
    Abstract: A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: April 23, 2013
    Assignee: National Central University
    Inventors: Jen-Inn Chyi, Geng-Yen Lee, Wei-Sheng Lin
  • Patent number: 8421187
    Abstract: A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Teramikros, Inc.
    Inventor: Syouichi Kotani
  • Publication number: 20130062726
    Abstract: Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-?/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-? dielectric layer on the STI region, forming a metal gate on the high-? dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Andreas Kurz, Maciej Wiatr
  • Publication number: 20130062728
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicant: GLOBALFOUNDERS Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Publication number: 20130056847
    Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.
    Type: Application
    Filed: October 14, 2011
    Publication date: March 7, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Baoxing CHEN
  • Patent number: 8391017
    Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: March 5, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: David Ross McGregor, Cheong-Wo Hunter Chan, Lynne E. Dellis, Fuhan Liu, Deepukumar M. Nair, Venkatesh Sundaram
  • Publication number: 20130043555
    Abstract: An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region and a first N type doped region. The covered shape of the first P type doped region is a polygon having at least eight edges, wherein the polygon is bilateral symmetry, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and uniformly drains it away.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Ching-Ling Tsai
  • Patent number: 8378455
    Abstract: An electric component arrangement is described, comprising a semiconductor component (1) and a varistor body (2), which is contact-connected to the semiconductor component in order to protect the latter against electrostatic discharges. The semiconductor component and the varistor body are arranged on a common carrier (3) containing a highly thermally conductive ceramic.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: February 19, 2013
    Assignee: Epcos AG
    Inventors: Thomas Feichtinger, Guenter Engel, Axel Pecina
  • Patent number: 8373250
    Abstract: The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 12, 2013
    Assignee: National Chiao Tung University
    Inventors: Tzu-Yuan Chao, Ming-Chieh Hsu, Yu-Ting Cheng, Chih Chen, Chien-Min Lin
  • Patent number: 8373251
    Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: February 12, 2013
    Assignees: Renesas Electronics Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinichi Uchida, Masayuki Furumiya, Hiroshi Sakakibara, Takashi Iwadare, Yoshiyuki Sato, Makoto Eguchi, Masato Taki, Hidetoshi Morishita, Kozo Kato, Jun Morimoto
  • Publication number: 20130015554
    Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 17, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang, Kang Chen, Jianmin Fang