Mesa Pn Junction Diode (epo) Patents (Class 257/E29.329)
  • Patent number: 8987865
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 24, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8975090
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8829629
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8803261
    Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane. The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 12, 2014
    Assignee: Wolfson Microelectronics plc
    Inventors: Anthony Bernard Traynor, Richard Ian Laming, Tsjerk H. Hoekstra
  • Patent number: 8772911
    Abstract: A semiconductor diode has a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer of a second conductivity type having a doping. The second semiconductor layer has a vertical electrical via region (106) which is connected to the first semiconductor layer and in which the doping is modified in such a way that the electrical via region (106) has the first conductivity type. A method for producing such a semiconductor diode is described.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: July 8, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tony Albrecht, Markus Maute, Martin Reufer, Heribert Zull
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8513746
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: August 20, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Patent number: 8466045
    Abstract: A method for forming strained epitaxial carbon-doped silicon (Si) films, for example as raised source and drain regions for electronic devices. The method includes providing a structure having an epitaxial Si surface and a patterned film, non-selectively depositing a carbon-doped Si film onto the structure, the carbon-doped Si film containing an epitaxial carbon-doped Si film deposited onto the epitaxial Si surface and a non-epitaxial carbon-doped Si film deposited onto the patterned film, and non-selectively depositing a Si film on the carbon-doped Si film, the Si film containing an epitaxial Si film deposited onto the epitaxial carbon-doped Si film and a non-epitaxial Si film deposited onto the non-epitaxial carbon-doped Si film. The method further includes dry etching away the non-epitaxial Si film, the non-epitaxial carbon-doped Si film, and less than the entire epitaxial Si film to form a strained epitaxial carbon-doped Si film on the epitaxial Si surface.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 18, 2013
    Assignee: Tokyo Electron Limited
    Inventors: John Gumpher, Seungho Oh, Anthony Dip
  • Patent number: 8426949
    Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: April 23, 2013
    Assignees: SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsuyuki Seki, Akira Suzuki, Keita Odajima
  • Patent number: 8350366
    Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 8, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Bernhard Koenig
  • Patent number: 8217423
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R Holt, Renee T Mo, Kern Rim
  • Patent number: 8212327
    Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 3, 2012
    Assignee: SiOnyx, Inc.
    Inventors: Neal T. Kurfiss, James E. Carey, Xia Li
  • Publication number: 20110304020
    Abstract: A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Patent number: 8053885
    Abstract: A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 8, 2011
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Sung-Yi Hsiao, Jack Chen
  • Patent number: 7989827
    Abstract: A multichip light emitting diode package is provided. The multichip light emitting diode (LED) package includes a substrate having a non-plane surface including a plurality of sectioned-surfaces, a plurality of light emitting diode chips and a transparent molding material. Each of the light emitting diode chips is disposed on one of the sectioned-surfaces of the substrate. The transparent molding material is formed on the substrate for encapsulating the light emitting diode chips. By way of the configurations of the non-plane surface of the substrate and the transparent molding material, the multichip light emitting diode package emits converging light in accordance with the Snell's law. The purposes of evenly mixing emitting lights and improving brightness are achieved. The present invention can provide a single color, multi-color or full-color multichip LED package with uniform brightness and hues.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: August 2, 2011
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventor: Chih-Peng Hsu
  • Publication number: 20110162687
    Abstract: Disclosed herein, in certain instances, is a novel photovoltaic cell that uses unique microarchitectural and multi-layer functional designs. Further disclosed herein, in certain instances, is a 3-dimensional electrode.
    Type: Application
    Filed: June 9, 2009
    Publication date: July 7, 2011
    Inventors: Kee Suk Moon, Khaled Morsi, Samuel Kassegne
  • Patent number: 7952172
    Abstract: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a semiconductor layer and a second electrode (n-side electrode 121) provided over the semiconductor layer; and a third mesa 13 provided over the semiconductor substrate 101, and having a semiconductor layer, wherein the third mesa 13 is arranged so as to surround the first mesa 11.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: May 31, 2011
    Assignee: NEC Corporation
    Inventors: Sawaki Watanabe, Kazuhiro Shiba, Takeshi Nakata
  • Patent number: 7936034
    Abstract: A MESA-type photonic detection device, including at least one first junction, which itself includes a first receiving layer and sides formed or etched in the receiving layer. These sides at least partially include a layer with a doping opposite the doping of the first receiving layer.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: May 3, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Johan Rothman
  • Patent number: 7791176
    Abstract: A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: September 7, 2010
    Assignee: SEMIKRON Elektronik GmbH & Co. KG
    Inventor: Bernhard K├Ânig
  • Publication number: 20100072573
    Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.
    Type: Application
    Filed: December 3, 2009
    Publication date: March 25, 2010
    Inventors: David D. Marreiro, Sudhama C. Shastri, Gordon M. Grivna, Earl D. Fuchs
  • Publication number: 20090189257
    Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 30, 2009
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd.
    Inventors: Katsuyuki SEKI, Akira Suzuki, Keita Odajima
  • Publication number: 20090085163
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 7507620
    Abstract: A vertical diode of low capacitance formed in a front surface of a semiconductor substrate, including a first area protruding from the substrate surface including at least one doped semiconductor layer of a conductivity type opposite to that of the substrate, the upper surface of the semiconductor layer supporting a first welding ball. The diode includes a second area including on the substrate a thick conductive track supporting at least two second welding balls, said first and second welding balls defining a plane parallel to the substrate plane.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: March 24, 2009
    Assignee: STMicroelectronics S.A.
    Inventors: Emmanuel Collard, Patrick Poveda
  • Patent number: 7381997
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Patent number: 7335927
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: February 26, 2008
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Publication number: 20070278626
    Abstract: Semiconductor component that contains AlxGayIn1?x?yAszSb1?z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a passivation layer containing AlnGa1?nAsmSb1?m is applied at least partially on at least one lateral surface of the structuring, and the parameter n is selected in the range of 0.4 to 1 and the parameter m in the range of 0 to 1.
    Type: Application
    Filed: July 25, 2005
    Publication date: December 6, 2007
    Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Frank Fuchs, Robert Rehm, Martin Walther
  • Patent number: 7288828
    Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: October 30, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Huan-Shun Lin, Chen-Hua Tsai, Wei-Tsun Shiau, Hsien-Liang Meng, Hung-Lin Shih