Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: The solid-state imaging device of the present invention includes: a plurality of photodetectors that are arranged in a two-dimensional matrix; a plurality of vertical transfer portions that transfer, in a vertical direction, signal electric charges which are read out from the respective photodetectors; a horizontal transfer portion that receives the signal electric charges transferred by the vertical transfer portions, and transfers the signal electric charges in a horizontal direction; a barrier region that is adjacent to the horizontal transfer portion, and allows an excess electric charge in the horizontal transfer portion to pass through; and a drain region that is adjacent to the barrier region and drains the excess electric charge which has passed through the barrier region; and bus lines that are disposed in parallel with the drain region, and apply control voltages to electrodes of the horizontal transfer portion.