Shape Of Body (epo) Patents (Class 257/E31.038)
  • Patent number: 11869919
    Abstract: A sensor device includes: a semiconductor substrate having a sensing region which extends vertically below a main surface region of the semiconductor substrate into the substrate; a semiconductor capping layer that extends vertically below the main surface region into the substrate; a buried deep trench structure that extends vertically below the capping layer into the substrate and laterally relative to the sensing region, the buried deep trench structure including a doped semiconductor layer that extends from a surface region of the buried deep trench structure into the substrate; a trench doping region that extends from the doped semiconductor layer of the buried deep trench structure into the substrate; and electronic circuitry for the sensing region in a capping region of the substrate vertically above the buried deep trench structure. Methods of manufacturing the sensor device are also provided.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Magali Glemet, Boris Binder, Henning Feick, Dirk Offenberg
  • Patent number: 11869728
    Abstract: We disclose herein a hetero-structure comprising: a curved material; at least one layer of a first material rolled around the curved material; at least one intermediate layer rolled on the at least one layer of the first material; and at least one layer of a second material rolled around the at least one intermediate layer.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: January 9, 2024
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Shahab Akhavan, Amin Taheri Najafabadi, Ilya Goykhman, Luigi Occhipinti, Andrea Carlo Ferrari
  • Patent number: 11804503
    Abstract: A photoelectric conversion device includes: a substrate; a photoelectric conversion element provided on the substrate; a first protective layer provided on the photoelectric conversion element; and a second protective layer provided above the substrate and surrounding the photoelectric conversion element and the first protective layer, the second protective layer being lower in water vapor transmittance than the first protective layer. The second protective layer has an upper end positioned above an upper end of the first protective layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: October 31, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 11757050
    Abstract: A system includes a substrate. The system also includes a detector array disposed over the substrate, where the detector array includes multiple detector pixels. The system further includes multiple plasmonic gratings disposed over top surfaces of the detector pixels, where each plasmonic grating includes multiple convex polyhedrons separated by valleys. Each detector pixel may have a mesa shape, and the convex polyhedrons of the plasmonic gratings may have a smaller size than the mesa shape of the detector pixels. A dimension across a base of each convex polyhedron of the plasmonic gratings may be selected based on a desired resonance wavelength of the plasmonic gratings.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 12, 2023
    Assignee: Raytheon Company
    Inventor: Jamal I. Mustafa
  • Patent number: 11675315
    Abstract: There is provided a solar panel including: a plurality of solar cells each of which is formed in a belt-shape extending in a predetermined direction on a plate-shaped surface and which is disposed in rows in a cell-width direction perpendicular to an extending direction of the plurality of solar cells; and a partition area that divides the plurality of solar cells from each other. The plurality of solar cells has, across at least two of the plurality of solar cells, a transparent power generation area which corresponds at least to a visible area seen from an outside and in which a power generation area and a transparent area that transmits light are alternately disposed and extend in the extending direction. In the transparent power generation area, the partition area is formed in a belt-shape having a width equal to a width of the transparent area.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 13, 2023
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Yuta Saito
  • Patent number: 11637212
    Abstract: An apparatus includes a first processing line. The first processing line includes a cleaving station adapted for separating a solar cell into two or more solar cell pieces. The apparatus includes a second processing line. The second processing line includes a storing station adapted for storing a plurality of solar cell pieces. The second processing line includes a transportation system adapted for transporting a solar cell piece from the storing station to the first processing line.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 25, 2023
    Assignee: APPLIED MATERIALS ITALIA S.R.L.
    Inventors: Marco Galiazzo, Luigi De Santi
  • Patent number: 11569189
    Abstract: The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 31, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yu-Han Hsueh
  • Patent number: 11522005
    Abstract: Methods of forming trench structures of different depths in a semiconductor substrate are provided. A first mask forming a first opening and a second opening is provided on the semiconductor substrate. The semiconductor substrate is etched through the first and second openings, thereby forming a first trench and a second trench. Trench structure material is deposited in the first and second trenches, thereby forming first and second trench structures. A second mask is provided on the first mask, wherein the second mask covers the first opening and has a third opening superimposed over the second opening of the first mask. The second trench structure is etched through the second opening of the first mask and through the third opening of the second mask.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: December 6, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventor: Hui Zang
  • Patent number: 11513283
    Abstract: The disclosed embodiments generally relate to extruding multiple layers of micro- to nano-polymer layers in a tubular shape. In particular, the aspects of the disclosed embodiments are directed to a method for producing a Bragg reflector comprising co-extrusion of micro- to nano-polymer layers in a tubular shape.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 29, 2022
    Assignee: Guill Tool & Engineering Co., Inc.
    Inventors: Richard Guillemette, Robert Peters, Christopher Hummel
  • Patent number: 11430822
    Abstract: A photoelectric conversion apparatus includes an element isolating portion that is disposed on a side of a front surface of a semiconductor layer and constituted by an insulator, and a pixel isolating portion. The pixel isolating portion includes a part that overlaps an isolating region in a normal direction. The semiconductor layer is continuous across semiconductor regions in an intermediate plane. The part is located between a semiconductor region and another semiconductor region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 30, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobutaka Ukigaya, Hideshi Kuwabara
  • Patent number: 11107938
    Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 31, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris Rodrigues Goncalves, Arnaud Tournier
  • Patent number: 10872995
    Abstract: An embodiment method of manufacturing an avalanche diode includes forming a first trench in a substrate material, filling the first trench with a first material that comprises a dopant, and causing the dopant to diffuse from the first trench to form part of a PN junction. An avalanche diode array can be formed to include a number of the avalanche diodes.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 22, 2020
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Laurence Stark
  • Patent number: 10476232
    Abstract: Provided are an optical apparatus, a manufacturing method of a distributed Bragg reflector laser diode, and a manufacturing method of the optical apparatus, the an optical apparatus including a cooling device, a distributed Bragg reflector laser diode having a lower clad including a recess region on one side of the cooling device and connected to another side of the cooling device, and an air gap between the cooling device and the distributed Bragg reflector laser diode, wherein the air gap is defined by a bottom surface of the lower clad in the recess region and a top surface of the cooling device.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 12, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: OH Kee Kwon, Su Hwan Oh, Chul-Wook Lee, Kisoo Kim
  • Patent number: 10042174
    Abstract: A display device has an NTSC ratio of higher than or equal to 80% and a contrast ratio of higher than or equal to 500 and includes a display portion. In the display portion, a pixel is provided at a resolution of greater than or equal to 80 ppi, and the pixel includes a light-emitting module capable of emitting light with a spectral line half-width of less than or equal to 60 nm. Further, the light emission of the light-emitting module is raised to a desired luminance with a gradient of greater than or equal to 0 in response to an input signal within a response time of longer than or equal to 1 ?s and shorter than 1 ms.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9780257
    Abstract: A method of preparing a quantum dot layer, including: placing an anodic aluminum oxide sheet with a plurality of through holes on a substrate; dispersing quantum dots into the plurality of through holes of the anodic aluminum oxide sheet; and removing the anodic aluminum oxide sheet to form a quantum dot layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 3, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaona Xu, Tian Yang, Biao Tian, Zhao Kang, Xiaoyan Zhu, Ning Chen, Xiang Zhou
  • Patent number: 9716242
    Abstract: Provided are a substrate for an organic electronic device (OED), an organic electronic device, a method of manufacturing the substrate or OED, and lighting. The substrate for an OED may be increased in durability by preventing penetration of external materials such as moisture or oxygen, and thus form an OED having excellent light extraction efficiency. In addition, since the substrate may be stably attached to an encapsulating structure sealing the OED, the device may have excellent durability with respect to abrasion of an electrode layer or pressure applied from an external environment. In addition, a surface hardness of an external terminal of the OED may be maintained at a suitable level.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 25, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Young Eun Kim, Jong Seok Kim, Young Kyun Moon, Jin Ha Hwang, Yeon Keun Lee, Sang Jun Park, Yong Nam Kim
  • Patent number: 9711110
    Abstract: A dark portion in an image seen by a viewer is expressed more precisely, whereby the image given a greater sense of depth is displayed. A display device in which pixels each include a light-emitting module capable of emitting light having a spectral line half-width of less than or equal to 60 nm in a response time of less than or equal to 100 ?s and are provided at a resolution of higher than or equal to 80 ppi; the NTSC ratio is higher than or equal to 80%; and the contrast ratio is higher than or equal to 500, is provided with a circuit converting an image signal having a given grayscale into an image signal capable of representing an image on the low luminance side by high-level grayscale.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9698366
    Abstract: Provided are a substrate for an organic electronic device (OED), an organic electronic system, a method of manufacturing the system or substrate, and lighting. The substrate for an OED may be increased in durability by preventing penetration of an external material such as moisture or oxygen, and thus an organic electronic system having excellent light extraction efficiency may be formed. In addition, since the substrate may be stably attached to an encapsulating structure sealing the organic electronic system, the device may have excellent durability with respect to abrasion of an electrode layer or pressure applied from an external environment. In addition, surface hardness of an external terminal of the organic electronic system may be maintained at a suitable level.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 4, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Young Eun Kim, Jong Seok Kim, Young Kyun Moon, Jin Ha Hwang
  • Patent number: 9576552
    Abstract: A dark portion in an image seen by a viewer is expressed more precisely, whereby the image given a greater sense of depth is displayed. A display device in which pixels each include a light-emitting module capable of emitting light having a spectral line half-width of less than or equal to 60 nm in a response time of less than or equal to 100 ?s and are provided at a resolution of higher than or equal to 80 ppi; the NTSC ratio is higher than or equal to 80%; and the contrast ratio is higher than or equal to 500, is provided with a circuit converting an image signal having a given grayscale into an image signal capable of representing an image on the low luminance side by high-level grayscale.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9035410
    Abstract: An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 19, 2015
    Assignee: THE BOEING COMPANY
    Inventors: Ping Yuan, Joseph C. Boisvert, Dmitri D. Krut, Rengarajan Sudharsanan
  • Patent number: 9000492
    Abstract: In a back-illuminated solid-state image pickup device including a semiconductor substrate 4 having a light incident surface at a back surface side and a charge transfer electrode 2 disposed at a light detection surface at an opposite side of the semiconductor substrate 4 with respect to the light incident surface, the light detection surface has an uneven surface. By the light detection surface having the uneven surface, etaloning is suppressed because lights reflected by the uneven surface have scattered phase differences with respect to a phase of incident light and resulting interfering lights offset each other. A high quality image can thus be acquired by the back-illuminated solid-state image pickup device.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 7, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hisanori Suzuki, Yasuhito Yoneta, Yasuhito Miyazaki, Masaharu Muramatsu, Koei Yamamoto
  • Patent number: 8946839
    Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
  • Patent number: 8895350
    Abstract: A method for forming a nanostructure according to one embodiment includes creating a hole in an insulating layer positioned over an electrically conductive layer; and forming a nanocable in the hole such that the nanocable extends through the hole in the insulating layer and protrudes therefrom, the nanocable being in communication with the electrically conductive layer. Additional systems and methods are also presented.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: November 25, 2014
    Assignees: Q1 Nanosystems, Inc, The Regents of the University of California
    Inventors: Brian Argo, Ruxandra Vidu, Pieter Stroeve, John Argo, Saif Islam, Jie-Ren Ku, Michael Chen
  • Patent number: 8871619
    Abstract: Solar cells and other semiconductor devices are fabricated more efficiently and for less cost using an implanted doping fabrication system. A system for implanting a semiconductor substrate includes an ion source (such as a single-species delivery module), an accelerator to generate from the ion source an ion beam having an energy of no more than 150 kV, and a beam director to expose the substrate to the beam. In one embodiment, the ion source is single-species delivery module that includes a single-gas delivery element and a single-ion source. Alternatively, the ion source is a plasma source used to generate a plasma beam. The system is used to fabricate solar cells having lightly doped photo-receptive regions and more highly doped grid lines. This structure reduces the formation of “dead layers” and improves the contact resistance, thereby increasing the efficiency of a solar cell.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Intevac, Inc.
    Inventors: Babak Adibi, Edward S. Murrer
  • Patent number: 8871533
    Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell preform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 28, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8860164
    Abstract: A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8766393
    Abstract: A photodetector is formed from a body of semiconductor material substantially surrounded by dielectric surfaces. A passivation process is applied to at least one surface to reduce the rate of carrier generation and recombination on that surface. Photocurrent is read out from at least one electrical contact, which is formed on a doped region whose surface lies entirely on a passivated surface. Unwanted leakage current from un-passivated surfaces is reduced through one of the following methods: (a) The un-passivated surface is separated from the photo-collecting contact by at least two junctions; (b) The un-passivated surface is doped to a very high level, at least equal to the conduction band or valence band density of states of the semiconductor; (c) An accumulation or inversion layer is formed on the un-passivated surface by the application of an electric field.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 1, 2014
    Assignee: Infrared Newco, Inc.
    Inventors: Conor S. Rafferty, Clifford A. King
  • Patent number: 8749010
    Abstract: According to one embodiment, an infrared imaging device includes a substrate, a detecting section, an interconnection, a contact plug and a support beam. The detecting section is provided above the substrate and includes an infrared absorbing section and a thermoelectric converting section. The interconnection is provided on an interconnection region of the substrate and is configured to read the electrical signal. The contact plug is extends from the interconnection toward a connecting layer provided in the interconnection region. The contact plug is electrically connected to the interconnection and the connecting layer. The support beam includes a support beam interconnection and supports the detecting section above the substrate. The support beam interconnection transmits the electrical signal from the thermoelectric converting section to the interconnection.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ikuo Fujiwara, Hitoshi Yagi, Keita Sasaki
  • Patent number: 8742527
    Abstract: According to one embodiment, a solid state imaging device includes a sensor substrate curved such that an upper face having a plurality of pixels formed is recessed and an imaging lens provided on the upper face side.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Suzuki, Risako Ueno, Honam Kwon, Mitsuyoshi Kobayashi, Hideyuki Funaki
  • Patent number: 8669632
    Abstract: A solid-state imaging device and a method for manufacturing the same are provided. The solid-state imaging device includes a structure that provides a high sensitivity and high resolution without variations in spectral sensitivity and without halation of colors, and prevents light from penetrating into an adjacent pixel portion. A plurality of photodiodes are formed inside a semiconductor substrate. A wiring layer includes a laminated structure of an insulating film and a wire and is formed on the semiconductor substrate. A plurality of color filters are formed individually in a manner corresponding to the plurality of photodiodes above the wiring layer. A planarized film and a microlens are sequentially laminated on each of the color filters. In the solid-state imaging device, each of the color filters has an refraction index higher than that of the planarized film and has, in a Z-axis direction, an upper surface in a concave shape.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Tetsuya Nakamura, Motonari Katsuno, Masayuki Takase, Masao Kataoka
  • Patent number: 8580599
    Abstract: Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 12, 2013
    Assignee: SunPower Corporation
    Inventors: Seung Bum Rim, Taeseok Kim, David D. Smith, Peter J. Cousins
  • Patent number: 8569853
    Abstract: A semiconductor light-receiving device includes a semiconductor light-receiving element that has a first electrode and a second electrode, a first wiring coupled to the first electrode, and a second wiring coupled to the second electrode, a width of the second wiring being smaller than a width of the first wiring.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 29, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Yuji Koyama
  • Patent number: 8551866
    Abstract: A method for the fabrication of a three-dimensional thin-film semiconductor substrate with selective through-holes is provided. A porous semiconductor layer is conformally formed on a semiconductor template comprising a plurality of three-dimensional inverted pyramidal surface features defined by top surface areas aligned along a (100) crystallographic orientation plane of the semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls aligned along the (111) crystallographic orientation plane of the semiconductor template. An epitaxial semiconductor layer is conformally formed on the porous semiconductor layer. The epitaxial semiconductor layer is released from the semiconductor template. Through-holes are selectively formed in the epitaxial semiconductor layer with openings between the front and back lateral surface planes of the epitaxial semiconductor layer to form a partially transparent three-dimensional thin-film semiconductor substrate.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: October 8, 2013
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
  • Patent number: 8525236
    Abstract: In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a top surface of the semiconductor layer. The image sensor also includes color filters disposed below a bottom surface of the semiconductor layer and lenses disposed below the color filters. Each lens is arranged to concentrate incoming light into an area spanned by a corresponding photoelectric converter.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joon-Young Choi
  • Publication number: 20130171758
    Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell perform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.
    Type: Application
    Filed: July 24, 2012
    Publication date: July 4, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
  • Patent number: 8450720
    Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 28, 2013
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter
  • Publication number: 20130126824
    Abstract: Disclosed are a semiconductor nanowire solid state optical device and a control method thereof. The device comprises a nanowire, a first electrode, a second electrode, an electrical circuit and a mechanical micro device. The nanowire has a first end and a second end. The first electrode is coupled to the first end. The second electrode is coupled to the second end. The electrical circuit is coupled to the first electrode and the second electrode. The mechanical micro device is conjuncted with the nanowire for applying an external force to the nanowire to form highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) in the nanowire. The HOMO and LUMO are employed as an n-type semiconductor and a p-type semiconductor, respectively. The nanowire is a semiconductor when an external force is applied thereto.
    Type: Application
    Filed: June 19, 2012
    Publication date: May 23, 2013
    Applicant: National Applied Research Laboratories
    Inventors: YU-CHING SHIH, Jiunn-horng Lee, Chia-chin Chen, Chi-feng Lin, Yu-bin Fang, Ming-hsiao Lee, Heng-chuan Kan
  • Patent number: 8399950
    Abstract: A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: March 19, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Noriyuki Miura
  • Patent number: 8378465
    Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yurii A. Vlasov, Fengnian Xia
  • Publication number: 20130026595
    Abstract: A semiconductor light-receiving device includes a semiconductor light-receiving element that has a first electrode and a second electrode, a first wiring coupled to the first electrode, and a second wiring coupled to the second electrode, a width of the second wiring being smaller than a width of the first wiring.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yuji Koyama
  • Patent number: 8362494
    Abstract: An electro-optic device is disclosed. The electro-optic device includes an insulating layer, a first semiconducting region disposed above the insulating layer and being doped with doping atoms of a first conductivity type, a second semiconducting region disposed above the insulating layer and being doped with doping atoms of a second conductivity type and an electro-optic active region disposed above the insulating layer and between the first semiconducting region and the second semiconducting region. The electro-optic active region includes a first partial active region and a second partial active region and an insulating structure in between. The insulating structure extends perpendicular to the surface of the insulating layer such that there is no overlap of the first partial active region and the second partial active region in the direction perpendicular to the surface of the insulating layer. A method for manufacturing is also disclosed.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: January 29, 2013
    Assignee: Agency for Science, Technology and Research
    Inventors: Guo-Qiang Patrick Lo, Kee-Soon Darryl Wang, Wei-Yip Loh, Mingbin Yu, Junfeng Song
  • Patent number: 8338902
    Abstract: An uncooled infrared image sensor according to an embodiments includes: a plurality of pixel cells formed in a first region on a semiconductor substrate; a reference pixel cell formed in a second region on the semiconductor substrate and corresponding to each row or each column of the pixel cells; a supporting unit formed for each of the pixel cell and supporting a corresponding pixel cell; and an interconnect unit formed for each reference pixel cell. Each of the pixel cells includes: a first infrared absorption film and a first heat sensitive element. The reference pixel cell includes: a second infrared absorption film and a second heat sensitive element, the second heat sensitive element having the same characteristics as characteristics of the first heat sensitive element. The third and fourth interconnects of the interconnect unit have the same electrical resistance as electrical resistance of the first and second interconnects of the supporting unit.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Honam Kwon, Hideyuki Funaki, Hiroto Honda, Hitoshi Yagi, Ikuo Fujiwara, Masaki Atsuta, Kazuhiro Suzuki, Keita Sasaki, Koichi Ishii
  • Patent number: 8338200
    Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 25, 2012
    Assignee: L-3 Communications Cincinnati Electronics Corporation
    Inventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter
  • Publication number: 20120222724
    Abstract: This solar cell module (1) comprises a plurality of solar cell arrays (11). Each solar cell array (11) includes a plurality of spherical semiconductor elements (20) arranged in a row, at least a pair of bypass diodes (40), and a pair of lead members (14) that connect the plurality of spherical semiconductor elements (20) and the plurality of bypass diodes (40) in parallel. Each of the lead members (14) includes one or plural lead strings (15) to which the plurality of spherical semiconductor elements (20) are electrically connected and having a width less than or equal to the radius of the spherical semiconductor element (20), and plural lead pieces (16) formed integrally with the lead strings (15) at least at both end portions of the lead member (14), on which the bypass diodes (40) are electrically connected in reverse parallel to the spherical semiconductor elements (20), and having width larger than or equal to the width of the bypass diodes (40).
    Type: Application
    Filed: December 19, 2008
    Publication date: September 6, 2012
    Applicant: KYOSEMI CORPORATION
    Inventor: Josuke Nakata
  • Publication number: 20120217606
    Abstract: A method of manufacturing a solid-state imaging element includes: manufacturing an element chip in which photoelectric conversion units are arranged on a main surface side; preparing a base configured using a material with an expansion coefficient greater than the element chip and having an opening of which the periphery of the opening is shaped as a flat surface; expanding the base by heating, mounting the element chip on the flat surface of the base in a state where the opening of the base is covered; and three-dimensionally curving a portion corresponding to the opening in the element chip by cooling and contracting the base in a state where the element chip is fixed to the flat surface of the expanded base.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 30, 2012
    Applicant: SONY CORPORATION
    Inventor: Kazuichiro ITONAGA
  • Patent number: 8227885
    Abstract: A selective light absorbing semiconductor surface is disclosed. Said semiconductor surface is characterized by the presence of indentations or protrusions comprising a grating of dimensions such as to enhance the absorption of selected frequencies of radiation. In a preferred embodiment of the present invention, said grating is formed on the surface of a doped semiconductor for the purposes of optical frequency down conversion. The semiconductor is doped so as to create energy levels within the forbidden zone between the conduction and valence bands. Incident radiation excites electrons from the valence to conduction band from where they decay to the meta-stable newly created energy level in the forbidden zone. From there, electrons return to the valence band, accompanied by the emission of radiation of lower frequency than that of the incident radiation. Optical frequency down-conversion is thus efficiently and rapidly accomplished.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: July 24, 2012
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Amiran Bibilashvili, Zaza Taliashvili
  • Patent number: 8222061
    Abstract: An example quantum dot (QD) device comprises a QD layer on a substrate, and may be fabricated by aerosol deposition, for example by mist deposition. An example approach includes providing a liquid precursor including QDs dispersed in a liquid carrier, generating a mist of droplets of the liquid precursor, directing the droplets towards the substrate so as to form a liquid precursor film on the substrate, and removing the liquid carrier from the liquid precursor film to form the quantum dot layer on the substrate. Example devices include multi-color QD-LED (light emitting diode) displays, and other devices.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: July 17, 2012
    Assignee: The Penn State Research Foundation
    Inventors: Jian Xu, Jerzy Ruzyllo, Karthikeyan Shanmugasundaram, Ting Zhu, Fan Zhang
  • Publication number: 20120147207
    Abstract: A solid-state imaging device includes a supporting substrate that includes a concave portion, a solid-state imaging chip that is bonded on the supporting substrate so as to seal the concave portion in a view-angle region, a stress film that is formed on the surface of the solid-state imaging chip, and an imaging surface curved toward the concave portion at least in the view-angle region.
    Type: Application
    Filed: November 18, 2011
    Publication date: June 14, 2012
    Applicant: SONY CORPORATION
    Inventor: Kazuichiroh Itonaga
  • Patent number: 8193601
    Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 5, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, William S. Wong, Rene A. Lujan, Scott J. Limb
  • Patent number: 8164151
    Abstract: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises a photodiode array and method of manufacturing a photodiode array that provides for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 24, 2012
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja