Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.

Abstract: A semiconductor structure is disclosed. The semiconductor substrate includes: a front surface and a back surface; and a heterogeneous radiation-sensing region in the semiconductor substrate, the heterogeneous radiation-sensing region including a top surface, a bottom surface and sidewalls, the top surface being adjacent to the front surface of the semiconductor substrate, the sidewalls being perpendicular to the front surface of the semiconductor substrate, and the bottom surface being parallel to the front surface of the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region.

Abstract: A light-receiving element includes a group III-V compound semiconductor stacked structure that includes an absorption layer having a pn-junction therein. The stacked structure is formed on a group III-V compound semiconductor substrate. The absorption layer has a multiquantum well structure composed of group III-V compound semiconductors, and the pn-junction is formed by selectively diffusing an impurity element into the absorption layer. A diffusion concentration distribution control layer composed of a III-V group semiconductor is disposed in contact with the absorption layer on a side of the absorption layer opposite the side adjacent to the group III-V compound semiconductor substrate. The bandgap energy of the diffusion concentration distribution control layer is smaller than that of the group III-V compound semiconductor substrate. The concentration of the impurity element selectively diffused in the diffusion concentration distribution control layer is 5×1016/cm3 or less toward the absorption layer.

Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).

Abstract: A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method for manufacturing the photodiode array, and an optical measurement system are provided. The steps of forming a mask layer 2 having a plurality of openings on a first-conductive-type or semi-insulating semiconductor substrate 1, the openings being arranged in one dimension or two dimensions, and selectively growing a plurality of semiconductor layers 3a, 3b, and 3c including an absorption layer 3b in the openings are included.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A spin-polarized electron generating device includes a substrate, a buffer layer, a strained superlattice layer formed on the buffer layer, and an intermediate layer formed of a crystal having a lattice constant greater than a lattice constant of a crystal of the buffer layer, the intermediate layer intervening between the substrate and the buffer layer. The buffer layer includes cracks formed in a direction perpendicular to the substrate by tensile strain.

Abstract: An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InxGa1-xSb with 0?x?0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa structure to isolate each photodetector element and instead uses impurity-doped regions formed in or about each photodetector for electrical isolation. This results in a substantially-planar structure in which the SLS is unbroken across the entire width of a 2-D array of the photodetector elements which are capped with an epitaxially-grown passivation layer to reduce or eliminate surface recombination. The FPA has applications for use in the wavelength range of 3-25 ?m.

Abstract: A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A semiconductor detector has a tunable spectral response. These detectors may be used with processing techniques that permit the creation of “synthetic” sensors that have spectral responses that are beyond the spectral responses attainable by the underlying detectors. For example, the processing techniques may permit continuous and independent tuning of both the center wavelength and the spectral resolution of the synthesized spectral response. Other processing techniques can also generate responses that are matched to specific target signatures.

Abstract: A semiconductor light receiving device includes: a substrate having a rectangular shape with first through fourth corners, a multilayer structure formed on the substrate, a light receiving part having a mesa structure positioned at a first corner side from a center part of the rectangular shape of the substrate, a first electrode pad provided on the semiconductor substrate, and a second electrode pad provided on the semiconductor substrate so as to be close to a second corner diagonally opposite to the first corner, a first minimum distance between the second electrode pad and an edge of the substrate being longer than a second minimum distance between the first electrode pad and the edge of the substrate.

Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.

Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.

Abstract: A semiconductor light detecting element comprises: a semiconductor substrate having a first major surface and a second major surface opposite each other; a first reflective layer, an absorptive layer, a phase adjusting layer, and a second reflective layer sequentially disposed, from the semiconductor substrate, on the first major surface of the semiconductor substrate; and an anti-reflection film on the second major surface of the semiconductor substrate. The first reflective layer is a multilayer reflective layer including laminated semiconductor layers having different refractive indices; the absorptive layer has a band gap energy smaller than band gap energy of the semiconductor substrate; the phase adjusting layer has a band gap energy larger than the band gap energy of the absorptive layer; and the first reflective layer contacts the absorptive layer, without intervention of other layers.

Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

Abstract: An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InxGa1?xSb with 0?x?0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa structure to isolate each photodetector element and instead uses impurity-doped regions formed in or about each photodetector for electrical isolation. This results in a substantially-planar structure in which the SLS is unbroken across the entire width of a 2-D array of the photodetector elements which are capped with an epitaxially-grown passivation layer to reduce or eliminate surface recombination. The FPA has applications for use in the wavelength range of 3-25 ?m.

Abstract: A semiconductor light receiving device is disclosed which is capable of receiving a first wavelength band light beam and a second wavelength band light beam having a shorter wavelength than that of the first wavelength band light beam. The device has a light absorbing layer of a first conductivity type formed on a semiconductor surface region of the semiconductor substrate the light absorbing layer absorbs the first and second wavelength band light beams. A cap layer of the first conductivity type is formed on the light absorbing layer. In the cap layer, a region of a second conductivity type is formed which transmits the second wavelength band light beam. A light collecting layer is formed on the semiconductor surface region and adjacently to the cap layer and the light absorbing layer. The light collecting layer has a convex shape with curvature to collect the second wavelength band light beam.

Abstract: A compound semiconductor wafer providing an InGaAs light receiving layer having superior crystal characteristic suitable for a near-infrared sensor includes an InAsxP1-x graded buffer layer consisting of a plurality of layers positioned on an InP substrate and an InAsyP1-y buffer layer positioned on the graded buffer layer, sandwiched between said InP substrate and the InGaAs layer, wherein maximum value of PL light emission intensity at an interface of each of the layers of the graded buffer layer and the buffer layer is, at every interface, smaller than 3/10 of the maximum PL light emission intensity of the buffer layer.

Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.