Pn Homojunction Potential Barrier (epo) Patents (Class 257/E31.057)
  • Patent number: 8896082
    Abstract: An integrated circuit-solar cell device comprising a well region of a first dopant type, a solar cell including: (i) a first region disposed in or on the well region, wherein the first region is of the first dopant type, and (ii) a second region disposed outside the well region, wherein the second region is of a second dopant type. The device further includes an integrated circuit including: (i) a first transistor of a first type disposed in or on the well region, and (ii) a second transistor of a second type disposed in or on the first major surface of the substrate and outside the well region. Power management circuitry selectively and electrically couples the solar cell to the battery when the integrated circuit is in an inactive mode.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 25, 2014
    Assignee: ActLight, S.A.
    Inventor: Serguei Okhonin
  • Patent number: 8753917
    Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
  • Patent number: 8633556
    Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 21, 2014
    Assignee: Sony Corporation
    Inventors: Tetsuya Ikuta, Yuki Miyanami
  • Patent number: 8558341
    Abstract: An object is to provide a photoelectric conversion element with high conversion efficiency. In a photoelectric conversion element with a fine periodic structure on a light-receiving surface side, focus is given to the traveling direction of light that is reflected off another surface. The photoelectric conversion element may be given a structure in which a textured structure that reflects light to the other surface is provided, and light that travels from the light-receiving surface side to the other surface side is reflected so that a component that travels along the photoelectric conversion layer increases. By the distance traveled by the reflected light inside the photoelectric conversion layer increasing, the light that enters the photoelectric conversion element is more easily absorbed by the photoelectric conversion layer and less easily released from the light-receiving surface side, and a photoelectric conversion element with high conversion efficiency can be provided.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Fumito Isaka, Jiro Nishida
  • Patent number: 8441089
    Abstract: This bispectral detector comprises a plurality of unitary elements for detecting a first and a second electromagnetic radiation range, consisting of a stack of upper and lower semiconductor layers of a first conductivity type which are separated by an intermediate layer that forms a potential barrier between the upper and lower layers; and for each unitary detection element, two upper and lower semiconductor zones of a second conductivity type opposite to the first conductivity type, are arranged respectively so that they are in contact with the upper faces of the upper and lower layers so as to form PN junctions, the semiconductor zone being positioned, at least partially, in the bottom of an opening that passes through the upper and intermediate layers. The upper face of at least one of the upper and lower layers is entirely covered in a semiconductor layer of the second conductivity type.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 14, 2013
    Assignee: Commissariat a l′Energie Atomique et Aux Energies Alternatives
    Inventors: Olivier Gravrand, Jacques Baylet
  • Patent number: 8420236
    Abstract: A magnetic semiconductor material contains at least one type of transition metals (Mn2+, Fe3+, Ru3+, Re2+, and Os3+) having five electrons in the d atomic orbital as a magnetic ion, in which the magnetic semiconductor material exhibits n-type electrical conduction by injection of an electron carrier and p-type electric conduction by injection of a hole carrier. A specific example is a layered oxy-pnictide compound represented by LnMnOPn (wherein Ln is at least one type selected from Y and rare earth elements of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and Pn is at least one selected from pnicogen elements of N, P, As, Bi, and Sb). A high-sensitivity magnetic sensor, current sensor, or memory device can be made by using a magnetic pn homojunction structure made of thin films composed of the magnetic semiconductor material.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: April 16, 2013
    Assignee: Japan Science and Technology Agency
    Inventors: Hideo Hosono, Masahiro Hirano, Hidenori Hiramatsu, Toshio Kamiya, Hiroshi Yanagi, Eiji Motomitsu
  • Patent number: 8410533
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaya Katayama
  • Publication number: 20130056807
    Abstract: A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other.
    Type: Application
    Filed: August 27, 2012
    Publication date: March 7, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Tetsunobu Kochi
  • Patent number: 8334534
    Abstract: A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 18, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Neil Davies, Simon Armbruster, Ando Feyh
  • Patent number: 8314446
    Abstract: A sensor including an array of light sensitive pixels, each pixel including: at least one hetero-junction phototransistor having a floating base without contact, wherein each phototransistor is a mesa device having active layers exposed at side-walls of the mesa device; and at least one atomic layer deposited high-k dielectric material adjacent to and passivating at least the side-wall exposed active layers.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: November 20, 2012
    Assignee: Wavefront Holdings, LLC
    Inventor: Jie Yao
  • Patent number: 8274127
    Abstract: A photodiode array includes a substrate of a common read-out control circuit; and a plurality of photodiodes arrayed on the substrate and each including an absorption layer, and a pair of a first conductive-side electrode and a second conductive-side electrode. In this photodiode array, each of the photodiodes is isolated from adjacent photodiodes, the first conductive-side electrodes are provided on first conductivity-type regions and electrically connected in common across all the photodiodes, and the second conductive-side electrodes are provided on second conductivity-type regions and individually electrically connected to read-out electrodes of the read-out control circuit.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Yasuhiro Iguchi
  • Patent number: 8258596
    Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 4, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Takanori Nakano
  • Publication number: 20120119316
    Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 17, 2012
    Applicant: Sony Corporation
    Inventors: Tetsuya IKUTA, Yuki MIYANAMI
  • Patent number: 8178912
    Abstract: An image sensor includes a first substrate, readout circuitry, an electrical junction region, a metal interconnection and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the electrical junction region is formed in the first substrate and electrically connected to the readout circuitry. The metal interconnection is electrically connected to the electrical junction region. The image sensing device is formed on and/or over the metal interconnection.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: May 15, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Joon Hwang
  • Publication number: 20120100658
    Abstract: Provided is a method of forming a semiconductor device. The method includes forming an insulating film on a semiconductor substrate, a conductive film on the insulating film, and a first structure and a second structure on the conductive film. The semiconductor substrate has first and second regions. The first and second structures are formed on the first and second regions, respectively. An impurity diffused region is formed in the semiconductor substrate using the first structure as a mask. The impurity diffused region overlaps the first structure. A portion of the first structure, and the conductive film are etched to respectively form a gate structure and a capacitor structure on the first and second regions.
    Type: Application
    Filed: September 8, 2011
    Publication date: April 26, 2012
    Inventors: JONG-WON CHOI, Jun-Seok Yang, Keon-Yong Cheon, Sung-Hyun Yoon
  • Publication number: 20110315861
    Abstract: It is an object to provide a photoelectric conversion device whose power consumption and a mounting area are reduced and yield is improved and further to provide a photoelectric conversion device whose number of manufacturing processes and manufacturing cost are reduced. A photoelectric conversion device includes a photoelectric conversion element for outputting photocurrent corresponding to illuminance, and a resistor changing resistance corresponding to illuminance. In the photoelectric conversion device, one terminal of the photoelectric conversion element and one terminal of the resistor are electrically connected in series; the other terminal of the photoelectric conversion element is connected to a high power supply potential; the other terminal of the resistor is connected to a low power supply potential; and a light intensity adjusting unit is provided on a light reception surface side of the photoelectric conversion element or the resistor to adjust illuminance.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yukinori SHIMA, Atsushi HIROSE
  • Patent number: 8080857
    Abstract: The present invention provides a semiconductor photodetecting device that suppresses sensitivity of a short wavelength component of irradiated light as well as a long wavelength component thereof and has a spectral sensitivity characteristic approximately coincident with a human visibility characteristic, and an illuminance sensor including the semiconductor photodetecting device. The semiconductor photodetecting device has a P-type well region and an N-type well region provided side by side along the surface of a P-type semiconductor substrate, a high-concentration N-type region formed in the neighborhood of the surface of the P-type well region, and a high-concentration P-type region formed in the neighborhood of the surface of the N-type well region.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: December 20, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriko Tomita
  • Patent number: 8048705
    Abstract: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jieguang Huo, Jianping Yang
  • Publication number: 20110226936
    Abstract: Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 22, 2011
    Inventors: Bedabrata PAIN, Thomas J. Cunningham
  • Patent number: 8022494
    Abstract: A lateral photodiode, with improved response speed, includes a semiconductor substrate having active regions, and a p-type region and an n-type region arranged parallel to the surface of the substrate. The active regions are an n-layer and a p-layer respectively, and stacked in the thickness direction of the substrate to form a p-n junction. In addition, a barrier layer, for preventing movement of carriers from the substrate toward the active region, is provided on the side of the active regions toward the substrate.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 20, 2011
    Assignees: FUJIFILM Corporation, Massachusetts Institute of Technology
    Inventors: Yukiya Miyachi, Wojciech P. Giziewicz, Jurgen Michel, Lionel C. Kimerling
  • Publication number: 20110156193
    Abstract: There is provided a semiconductor component including: a semiconductor substrate of a first conduction type; a semiconductor layer of a second conduction type that is formed on the semiconductor substrate and is PN-joined with the semiconductor substrate; an insulator layer laminated on the semiconductor layer; a metal layer laminated on the insulator layer at a pre-specified region; a semiconductor of the second conduction type at a side of the semiconductor layer at which the insulating layer is laminated, the semiconductor being formed directly under the metal layer such that incident light that is incident from the metal layer side is not illuminated onto the semiconductor layer, and the semiconductor containing more impurities than the semiconductor layer; and a conduction portion that conducts between the metal layer and the semiconductor.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 30, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Atsushi NAKAMURA, Masami IKEGAMI
  • Patent number: 7968963
    Abstract: A photodiode array with reduced optical crosstalk and an image pickup device using it are provided. The photodiode array 10 according to the present invention has an anti-crosstalk portion B dividing each adjacent pair of photodiodes S, the anti-crosstalk portion B and the photodiodes S individually have a p-type area 16 extending inward from the surface side of a semiconductor laminate, and the inner end of the p-type area of the anti-crosstalk portion, namely the front, is closer to the back surface of the semiconductor laminate than the front of the p-type area of each of the photodiodes.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: June 28, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiroshi Inada
  • Publication number: 20110121423
    Abstract: A mask for use in making a planar PN junction in a semiconductor device includes a central mask opening and a plurality of spaced apart concentric mask openings surrounding the central mask opening. The concentric mask openings each have a width less than a maximum dimension of the central mask opening. The central mask opening can be circular and the concentric mask openings can have a ring-shape. The mask can be used to form openings in a wafer layer for introducing an impurity to dope that wafer layer.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: Sensors Unlimited, Inc.
    Inventors: Keith Forsyth, Noah Clay
  • Patent number: 7943455
    Abstract: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ui-sik Kim
  • Patent number: 7936038
    Abstract: Disclosed herein is a photodiode cell, including: a first-type substrate; a second-type epitaxial layer disposed on the first-type substrate; heavily-doped second-type layers, each having a small depth, formed on the second-type epitaxial layer; and heavily-doped first-type layers, each having a narrow and shallow section, disposed on the second-type epitaxial layer and formed between the heavily-doped second-type layers, wherein the first-type and second-type have opposite doped states.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung Electro-Mechanics Co.
    Inventors: Ha Woong Jeong, Kyoung Soo Kwon, Chae Dong Go, Deuk Hee Park
  • Publication number: 20110057282
    Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.
    Type: Application
    Filed: September 9, 2009
    Publication date: March 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. ELLIS-MONAGHAN, Jeffery P. GAMBINO, Daniel N. MAYNARD, Richard J. RASSEL
  • Patent number: 7888766
    Abstract: A photodiode array 1 is provided with an n-type silicon substrate 3. A plurality of photodiodes 4 are formed in array on the opposites surface side to an incident surface of light L to be detected, in the n-type silicon substrate 3. A depression 6 with a predetermined depth more depressed than a region not corresponding to regions where the photodiodes 4 are formed is formed in regions corresponding to the regions where the photodiodes 4 are formed, on the incident surface side of the light L to be detected, in the n-type silicon substrate 3.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 15, 2011
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Patent number: 7888765
    Abstract: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaki Taniguchi, Hisatada Yasukawa, Takaki Iwai
  • Publication number: 20110024807
    Abstract: A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region.
    Type: Application
    Filed: July 9, 2010
    Publication date: February 3, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaya Katayama
  • Patent number: 7875890
    Abstract: Structures and methods to improve the crosstalk between adjacent pixels of back-illuminated photodiode arrays on a substrate having first and second surfaces, including providing a first matrix of regions of a first conductivity type of a higher conductivity than the substrate extending into the substrate from the first surface and surrounding each photodiode of the array, and providing a second matrix of regions of a first conductivity type of a higher conductivity than the substrate extending into the substrate from the second surface, the second matrix being a mirror image of and aligned with the first matrix, the matrices extending into the substrate less than one half the thickness of the substrate so as to not touch each other. The methods and corresponding structures may be applied to p/n diodes, pin diodes, avalanche photodiodes, photoconductive cells (no p-n junction at all), or similar photosensitive device arrays.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: January 25, 2011
    Assignee: Array Optronix, Inc.
    Inventor: Alexander O. Goushcha
  • Publication number: 20110001204
    Abstract: Consistent the present disclosure, a receive circuit is provided that includes a balanced detector portion and a transimpedance amplifier (TIA). The anode of one photodiode is connected to the cathode of the other by a bonding pad, which supplies the sum of the currents generated in each photodiode to an input of the TIA. Thus, the TIA may, for example, have a single input, as opposed to multiple inputs, thereby reducing the number of connections so that the photodiodes and the TIA may be integrated onto a smaller die. In addition, since there are few connections, fewer TIAs are required and differential stages are unnecessary. Power consumption is thus reduced, and, since the photodiode current is fed through one input to the TIA, fewer feedback resistors are required, thereby reducing thermal noise. In addition, since the anode of one photodiode is connected to the cathode of the other, the dark current generated in each flows in opposite directions, and is therefore effectively cancelled out.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 6, 2011
    Inventors: Radhakrishnan L. Nagarajan, Huan-Shang Tsal
  • Publication number: 20100308212
    Abstract: Each of even-numbered photodiodes 1 and 2 for constituting a diode of the present invention (i) has regions (regions 1a through 1c and regions 2a through 2c) whose sizes in a certain direction are identical to sizes of regions of a reference diode 5, and (ii) has a channel width equal to ½ of a channel width W of the reference diode 5. The regions 1a through 1c and the regions 2a through 2c are arranged so as to (i) extend parallel to the certain direction which is provided parallel to a channel length L of the reference diode 5, and so as to be (ii) line-symmetric or point-symmetric to each other as a whole. The photodiodes 1 and 2 are electrically connected to each other in series so as to carry out an equivalent operation to that of the reference diode 5. Employing of the photodiodes 1 and 2 provides a configuration of diodes each having an identical characteristic and occupying a reduced area on a substrate.
    Type: Application
    Filed: January 14, 2009
    Publication date: December 9, 2010
    Inventors: Kohei Tanaka, Christopher Brown
  • Publication number: 20100258894
    Abstract: A photodiode array with reduced optical crosstalk and an image pickup device using it are provided. The photodiode array 10 according to the present invention has an anti-crosstalk portion B dividing each adjacent pair of photodiodes S, the anti-crosstalk portion B and the photodiodes S individually have a p-type area 16 extending inward from the surface side of a semiconductor laminate, and the inner end of the p-type area of the anti-crosstalk portion, namely the front, is closer to the back surface of the semiconductor laminate than the front of the p-type area of each of the photodiodes.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hiroshi INADA
  • Publication number: 20100244177
    Abstract: Disclosed herein is a photodiode cell, including: a first-type substrate; a second-type epitaxial layer disposed on the first-type substrate; heavily-doped second-type layers, each having a small depth, formed on the second-type epitaxial layer; and heavily-doped first-type layers, each having a narrow and shallow section, disposed on the second-type epitaxial layer and formed between the heavily-doped second-type layers, wherein the first-type and second-type have opposite doped states.
    Type: Application
    Filed: May 12, 2009
    Publication date: September 30, 2010
    Inventors: Ha Woong Jeong, Kyoung Soo Kwon, Chae Dong Go, Deuk Hee Park
  • Publication number: 20100244174
    Abstract: A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 30, 2010
    Applicant: SIONYX, INC.
    Inventors: Nathaniel J. McCaffrey, James E. Carey
  • Publication number: 20100224946
    Abstract: An embodiment of the invention provides a solid-state image pickup element, including: a semiconductor layer having a photodiode, photoelectric conversion being carried out in the photodiode; a silicon oxide film formed on the semiconductor layer in a region having at least the photodiode by using plasma; and a film formed on the silicon oxide film and having negative fixed charges.
    Type: Application
    Filed: January 21, 2010
    Publication date: September 9, 2010
    Applicant: SONY CORPORATION
    Inventors: Itaru Oshiyama, Susumu Hiyama
  • Publication number: 20100213348
    Abstract: Provided are a separation type unit pixel for preventing sensitivity reduction to prevent a depletion area from decreasing and a method of driving the unit pixel. The separation type unit pixel for preventing sensitivity reduction includes: a substrate; a photodiode constructed with a junction of a P-type diffusion area and an N-type diffusion area which are formed under a surface of the substrate in a vertical direction; a gate electrode conductor which is disposed on an upper portion of the surface of the substrate to be adjacent to the N-type or P-type diffusion area; a floating diffusion area formed to be adjacent to another surface of the gate electrode conductor; and a sensitivity reduction preventing conductor disposed on an upper portion of the photodiode area to cover the photodiode area.
    Type: Application
    Filed: August 4, 2008
    Publication date: August 26, 2010
    Applicant: SILICONFILE TECHNOLOGIES INC.
    Inventor: Do-Young Lee
  • Patent number: 7781253
    Abstract: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart in the second epitaxial layer; and a second isolation region electrically isolating the second photodiodes from each other.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: August 24, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong-Su Park
  • Publication number: 20100207231
    Abstract: Photoelectric conversion regions (130, 140) are formed from both sides of a semiconductor substrate 100, so that the photoelectric conversion regions (130, 140) can be easily formed at a deep position from the surfaces of the semiconductor substrate 100 without using a high-energy ion implanter and a thick resist. With this configuration, long-wavelength input light from a visible light region to a far-red light region can be efficiently absorbed from the outside. Thus it is possible to improve the light receiving sensitivity of a solid-state image device and increase the number of pixels of the solid-state image device without reducing sensitivity in a unit pixel.
    Type: Application
    Filed: February 16, 2010
    Publication date: August 19, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masatoshi IWAMOTO, Tohru YAMADA
  • Publication number: 20100151619
    Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.
    Type: Application
    Filed: February 25, 2010
    Publication date: June 17, 2010
    Applicant: ANALOG DEVICES, INC.
    Inventors: John A. Yasaitis, Lawrence Jay Lowell
  • Patent number: 7737517
    Abstract: A display device includes a pixel including: a gate line; a gate insulating film; a substrate; a data line; a pixel electrode; a semiconductor layer formed on the gate line and the gate insulating film; a protective film formed on the data line, the pixel electrode, and the semiconductor layer; and a thin film transistor. A portion of the gate line also serves as a gate electrode of the thin film transistor. A portion of the data line also serves as a drain electrode of the thin film transistor. A portion of the pixel electrode also serves as a source electrode of the thin film transistor. The semiconductor layer is formed of an oxide semiconductor layer. The oxide semiconductor layer is directly connected to the drain electrode and the source electrode, and the data line and the pixel electrode are formed of different conductive films.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: June 15, 2010
    Assignee: Hitachi Displays, Ltd.
    Inventors: Tetsufumi Kawamura, Takeshi Sato, Mutsuko Hatano
  • Publication number: 20100140618
    Abstract: A sensor includes at least one micro-patterned diode pixel that has a diode implemented in, on, or under a diaphragm, and the diaphragm in turn being implemented above a cavity. The diode is contacted via supply leads that are implemented at least in part in, on, or under the diaphragm, and the diode is implemented in a polycrystalline semiconductor layer. The diode is implemented by way of two low-doped diode regions or at least one low-doped diode region. At least parts of the supply leads are implemented by way of highly doped supply lead regions of the shared polycrystalline semiconductor layer.
    Type: Application
    Filed: November 10, 2009
    Publication date: June 10, 2010
    Inventors: Jochen Reinmuth, Neil Davies, Simon Armbruster, Ando Feyh
  • Publication number: 20100123081
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on a surface at a side of an n-type silicon substrate (3) onto which light to be detected is made incident and penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with a transparent resin film (6), which covers the formed regions of the photodiodes (4) and transmits the light to be detected, provided at the incidence surface side.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 20, 2010
    Inventor: Katsumi Shibayama
  • Publication number: 20100116335
    Abstract: Solar cells fabricated without gasification of metallurgical-grade silicon. The substrates are prepared by: melting metallurgical grade silicon in a furnace; solidifying the melted metallurgical grade silicon into an ingot; slicing the ingot to obtain a plurality of wafers; polishing and cleaning each wafer; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride; and, removing the aluminum layer. The front surface may be textured prior to forming the solar cell. The solar cell structure comprises a metallurgical grade doped silicon substrate and a thin-film structure formed over the substrate to form a p-i-n junction with the substrate. The substrate may be doped p-type, and the thin film structure may be an intrinsic amorphous layer formed over the substrate and an n-type amorphous layer formed over the intrinsic layer.
    Type: Application
    Filed: December 2, 2009
    Publication date: May 13, 2010
    Applicant: SUNPREME, LTD.
    Inventor: Ashok Sinha
  • Patent number: 7713766
    Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 11, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Danielle Thomas, Maurice Rivoire
  • Publication number: 20100108893
    Abstract: Ultra thin photodiode array structures and fabrication methods are disclosed. The back illuminated or front illuminated photodiode arrays have the active portion fabricated in a semiconductor layer which may be bonded to a supporting substrate layer. The active portion of semiconductor layer may comprise epitaxially grown layer. The isolation regions between pixels of an array may span the epitaxial layer and a semiconductor layer. Electrical contacts to the diodes are made through the bonded substrate or a portion of active layer. Methods of fabrication include steps to form a photodiode array of this type as well as steps to bond this array to supporting substrates. In some embodiments, supporting substrates are temporarily bonded for support of the methods of processing.
    Type: Application
    Filed: October 26, 2009
    Publication date: May 6, 2010
    Applicant: ARRAY OPTRONIX, INC.
    Inventors: Frederick A. Flitsch, Alexander O. Goushcha
  • Publication number: 20100109117
    Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.
    Type: Application
    Filed: January 13, 2010
    Publication date: May 6, 2010
    Applicants: Lumiense Photonics Inc., HANVISION CO., LTD.
    Inventor: Robert Steven Hannebauer
  • Publication number: 20100084729
    Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.
    Type: Application
    Filed: August 25, 2009
    Publication date: April 8, 2010
    Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
  • Publication number: 20100078751
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor can include a readout circuitry on a first substrate; an interlayer dielectric layer including at least one metal and contact plug electrically connected to the readout circuitry; and an image sensing device formed on a second substrate, bonded to the interlayer dielectric layer, and provided with a first conductive type conduction layer and a second conductive type conduction layer. An uppermost contact plug in the interlayer dielectric layer has a wall structure extending from an uppermost metal in the interlayer dielectric layer. The top surface of the uppermost contact plug makes contact with the image sensing device and is connected to an image sensing device and an uppermost metal of an adjacent pixel.
    Type: Application
    Filed: September 21, 2009
    Publication date: April 1, 2010
    Inventor: Jong Man Kim
  • Publication number: 20100059847
    Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.
    Type: Application
    Filed: November 15, 2007
    Publication date: March 11, 2010
    Inventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Takanori Nakano