Device Comprising Active Layer Formed Only By Group Iv Compound (epo) Patents (Class 257/E31.06)
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Patent number: 8753917Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.Type: GrantFiled: December 14, 2010Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
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Patent number: 8734687Abstract: The present invention relates to screen-printable quaternary chalcogenide compositions. The present invention also provides a process for creating an essentially pure crystalline layer of the quaternary chalcogenide on a substrate. Such coated substrates contain p-type semiconductors and are useful as the absorber layer in a solar cell.Type: GrantFiled: November 23, 2010Date of Patent: May 27, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Alex Sergey Ionkin, Brian M. Fish, Ross Getty
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Publication number: 20130320478Abstract: System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiu-Ko JangJian, Kei-Wei Chen, Chi-Cherng Jeng, Min Hao Hong
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Patent number: 8222075Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.Type: GrantFiled: March 17, 2009Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Eiji Ito
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Patent number: 8048705Abstract: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.Type: GrantFiled: October 27, 2008Date of Patent: November 1, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Jieguang Huo, Jianping Yang
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Patent number: 7999250Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.Type: GrantFiled: February 27, 2009Date of Patent: August 16, 2011Assignee: HVVi Semiconductors, Inc.Inventors: Bishnu Prasanna Gogoi, Robert Bruce Davies
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Publication number: 20110163406Abstract: A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Inventor: Noriyuki MIURA
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Publication number: 20110147602Abstract: A radiographic imaging apparatus includes a sensor panel having an effective pixel region and a peripheral region surrounding the effective pixel region; a scintillator layer disposed on the effective pixel region and the peripheral region of the sensor panel; and a scintillator protecting layer disposed on the scintillator layer. The scintillator layer includes a plurality of columnar crystals disposed on the effective pixel region, a plurality of columnar crystals disposed on the peripheral region, and a resin disposed between the plurality of the columnar crystals on the peripheral region and surrounding the plurality of the columnar crystals on the effective pixel region. The plurality of the columnar crystals on the effective pixel region is enclosed by the sensor panel, the scintillator layer, and the resin.Type: ApplicationFiled: December 15, 2010Publication date: June 23, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Yohei Ishida, Satoshi Okada, Kazumi Nagano, Masato Inoue, Shinichi Takeda, Keiichi Nomura, Satoru Sawada
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Patent number: 7420233Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.Type: GrantFiled: October 22, 2003Date of Patent: September 2, 2008Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Richard A. Mauritzson, Inna Patrick
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Publication number: 20080111205Abstract: A photodiode that can separately detect the intensities of the three wavelength ranges of ultraviolet light of 400 nm or below includes an insulating layer; and a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, wherein each of the plurality of silicon semiconductor layers has a low-concentration diffusion layer formed by diffusing one of a P-type impurity or an N-type impurity therein with a low concentration; a P-type high-concentration diffusion layer formed by diffusing a P-type impurity therein with a high concentration; and an N-type high-concentration diffusion layer formed by diffusing an N-type impurity therein with a high concentration, and wherein the P-type high-concentration diffusion layer and the N-type high-concentration diffusion layer formed in a respective one of the plurality of silicon semiconductor layers are arranged to face each other with the low-concentration diffusion layer interposed there between.Type: ApplicationFiled: November 9, 2007Publication date: May 15, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Noriyuki Miura