Metal-semiconductor-metal (msm) Schottky Barrier (epo) Patents (Class 257/E31.066)
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Patent number: 11522066Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.Type: GrantFiled: December 8, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Patent number: 8154025Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.Type: GrantFiled: September 18, 2009Date of Patent: April 10, 2012Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 8143688Abstract: A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations.Type: GrantFiled: May 18, 2010Date of Patent: March 27, 2012Assignee: SiOnys, Inc.Inventors: Nathaniel J. McCaffrey, James E. Carey
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Patent number: 8125008Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.Type: GrantFiled: November 17, 2006Date of Patent: February 28, 2012Assignee: System General CorporationInventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin
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Publication number: 20120012967Abstract: A black silicon based metal-semiconductor-metal photodetector includes a silicon substrate and a black silicon layer formed on the silicon substrate. An interdigitated electrode pattern structure is formed on the black silicon layer, which can be a planar or U-shaped structure. A thin potential barrier layer is deposited at the interdigitated electrode pattern structure. An Al or transparent conductive ITO thin film is deposited on the thin potential barrier layer. A passivation layer is provided on the black silicon layer. In the black silicon based metal-semiconductor-metal photodetector, the black silicon layer, as a light-sensitive area, can respond to ultraviolet, visible and near infrared light.Type: ApplicationFiled: July 13, 2010Publication date: January 19, 2012Inventors: Yadong Jiang, Guodong Zhao, Zhiming Wu, Wei Li, Jing Jiang, Anyuan Zhang, Zhengyu Guo
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Patent number: 8048705Abstract: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.Type: GrantFiled: October 27, 2008Date of Patent: November 1, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Jieguang Huo, Jianping Yang
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Patent number: 8044486Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.Type: GrantFiled: December 11, 2009Date of Patent: October 25, 2011Assignee: Alpha & Omega Semiconductor, Inc.Inventor: François Hébert
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Publication number: 20110237015Abstract: The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5 microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction with the semiconductor core and the other forms an ohmic contact therewith. In other embodiment, the nanophotovoltaic device includes a semiconductor core comprising a p-n junction that is sandwiched between two metallic layers forming ohmic contacts with the core.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Applicant: SPIRE CORPORATIONInventors: Steven J. Wojtczuk, James G. Moe, Roger G. Little
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Publication number: 20110175183Abstract: Metal-semiconductor-metal (MSM) photodetectors may see increased responsivity when a plasmonic lens is integrated with the photodetector. The increased responsivity of the photodetector may be a result of effectively ‘guiding’ photons into the active area of the device in the form of a surface plasmon polariton. In one embodiment, the plasmonic lens may not substantially decrease the speed of the MSM photodetector. In another embodiment, the Shottkey contacts of the MSM photodetector may be corrugated to provide integrated plasmonic lens. For example, one or more of the cathodes and anodes can be modified to create a plurality of corrugations. These corrugations may be configured as a plasmonic lens on the surface of a photodetector. The corrugations may be configured as parallel linear corrugations, equally spaced curved corrugations, curved parallel corrugations, approximately equally spaced concentric circular corrugations, chirped corrugations or the like.Type: ApplicationFiled: August 13, 2010Publication date: July 21, 2011Applicant: DREXEL UNIVERSITYInventors: Bahram Nabet, James Anthony Shackleford, Richard R. Grote, Jonathan E. Spanier
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Patent number: 7928480Abstract: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90°.Type: GrantFiled: November 30, 2006Date of Patent: April 19, 2011Assignee: Sharp Kabushiki KaishaInventors: Masaharu Yamashita, John Kevin Twynam
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Publication number: 20100244174Abstract: A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations.Type: ApplicationFiled: May 18, 2010Publication date: September 30, 2010Applicant: SIONYX, INC.Inventors: Nathaniel J. McCaffrey, James E. Carey
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Patent number: 7781786Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.Type: GrantFiled: April 10, 2007Date of Patent: August 24, 2010Assignee: Nissan Motor Co., Ltd.Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
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Patent number: 7633135Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as an Schottky anode.Type: GrantFiled: July 22, 2007Date of Patent: December 15, 2009Assignee: Alpha & Omega Semiconductor, Ltd.Inventor: François Hébert
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Patent number: 7538362Abstract: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided.Type: GrantFiled: August 29, 2005Date of Patent: May 26, 2009Assignee: Infineon Technologies AGInventors: Gabriel Konrad Dehlinger, Michael Treu