For Device Having Potential Or Surface Barrier (epo) Patents (Class 257/E31.114)
  • Patent number: 8502389
    Abstract: An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Wen-De Wang, Shih Pei Chou
  • Publication number: 20130049151
    Abstract: Interconnect structures suitable for use in connecting anode-illuminated detector modules to downstream circuitry are disclosed. In certain embodiments, the interconnect structures are based on or include low atomic number or polymeric features and/or are formed at a density or thickness so as to minimize or reduce radiation attenuation by the interconnect structures.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: General Electric Company
    Inventors: Vladimir A. Lobastov, Kevin Matthew Durocher, John Eric Tkaczyk, James Wilson Rose, Paul Alan McConnelee
  • Publication number: 20130026355
    Abstract: A neutron porosity measurement device adapted to receive a neutron source configured to emit neutrons having a first energy includes a segmented semiconductor detector located at a predetermined distance from the neutron source. The segmented semiconductor detector includes a plurality of semiconductor neutron detection cells configured to detect neutrons having a second energy smaller than the first energy. The cells are arranged in subsets located between a first distance and a second distance from the neutron source, each subset including semiconductor neutron detection cells surrounding an axis and being disposed in opposite sectors defined relative to the axis at substantially same distance from the neutron source. One or more of the neutron detection cells are configured to acquire data related to detected neutrons independently from one or more other of the neutron detected cells. A method of manufacturing the neutron porosity measurement device is also provided.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Applicant: SONDEX WIRELINE LIMITED
    Inventors: Helene Claire CLIMENT, Jason MACINNIS
  • Patent number: 8338904
    Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
  • Publication number: 20120318330
    Abstract: A voltage matched multijunction solar cell having first and second solar cell stacks which are electrically connected parallel to each other. The first solar cell stack is optimized for absorption of incoming solar light in a first wavelength range and the second solar cell stack is optimized for absorption of incoming solar light in a second wavelength range, wherein the first and the second wavelength range do not or at most only partially overlap each other.
    Type: Application
    Filed: March 17, 2011
    Publication date: December 20, 2012
    Applicant: SOITEC
    Inventors: Andreas Gombert, Sascha Van Riesen
  • Publication number: 20120260973
    Abstract: Embodiments of the invention generally relate to a busing sub-assembly and methods of forming photovoltaic modules having busing sub-assemblies. The busing sub-assembly generally includes a carrier backsheet and a plurality of conductive ribbons coupled to the carrier backsheet. An electrically insulating cover is disposed over the conductive ribbons and the carrier backsheet. The ends of each conductive ribbon remain exposed for making an electrical connection to the conductive foil or a junction box. Methods of forming photovoltaic modules generally include positioning a flexible backsheet having an opening therethrough and a conductive foil thereon on a support. A busing sub-assembly is disposed on the flexible backsheet over the opening and in electrical contact with the conductive foil. The busing sub-assembly includes the components necessary to bus electrical current from a plurality of solar cells to a junction box, and can be applied to a photovoltaic module in a singe process step.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: John Telle, Brian J. Murphy, David H. Meakin
  • Publication number: 20120222719
    Abstract: A solar battery module includes a first cell line formed by arraying a plurality of solar battery cells in a first direction, a first inter-cell lead that connects the solar battery cells in the first cell line in an array direction, a second cell line formed by arraying the solar battery cells in parallel to the first cell line, a second inter-cell lead that connects the solar battery cells forming the second cell line in an array direction, and an inter-line lead that extends in a direction perpendicular to the first direction and electrically connects the first inter-cell lead and the second inter-cell lead, in which at least a portion of the inter-line lead overlaps the solar battery cell.
    Type: Application
    Filed: November 9, 2009
    Publication date: September 6, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keiichiro Utsunomiya, Tatsuya Ishigaki
  • Publication number: 20120211047
    Abstract: A method of forming a multijunction solar cell string by mounting first and second multijunction solar cells on a first side of a perforated carrier; attaching a first electrical interconnect to the contact pad of said first multijunction solar cell, the electrical interconnect extending through said perforated carrier; attaching a second electrical interconnect to the metal contact layer of said second multijunction solar cell, the electrical interconnect extending through said perforated carrier; and connecting said first electrical interconnect to said second electrical interconnect.
    Type: Application
    Filed: April 5, 2012
    Publication date: August 23, 2012
    Applicant: Emcore Solar Power, Inc.
    Inventor: Arthur Cornfeld
  • Publication number: 20110203630
    Abstract: A photovoltaic device that can prevent performance degradation caused by electrodeposition generated as a result of moisture penetration. In the photovoltaic device, two or more intermediate insulation portions that electrically insulate solar cell unit cells positioned adjacently in the X-direction are formed on the substrate center side of side insulation portions so as to extend in the Y-direction in a parallel arrangement across the X-direction, a conductive portion that electrically connects solar cell unit cells positioned adjacently in the X-direction is provided in a position partway along each of the intermediate insulation portions, and the solar cell unit cells where the conductive portion is positioned are electrically insulated from a solar cell unit cell positioned adjacently in the X-direction by another of the intermediate insulation portions positioned distant from the conductive portion in the X-direction.
    Type: Application
    Filed: August 14, 2007
    Publication date: August 25, 2011
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Akemi Takano, Tatsuji Horioka, Satoshi Kokaji, Kazutaka Uda
  • Patent number: 7936039
    Abstract: A pixel for a CMOS photo sensor with increased full well capacity is disclosed. The pixel having a photosensitive element, a photo gate, potential well and a readout circuit. The photosensitive element having a front side and a back side, for releasing charge when light strikes the back side of the photosensitive element. The potential well receives the released charge from the photosensitive element. The photo gate located on the front side of the photosensitive element, for transferring the released charge from the potential well to a sense node. The readout circuit coupled to the sense node, for measuring a voltage corresponding to the released charge transferred to the sense node.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 3, 2011
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Stefan Clemens Lauxtermann
  • Publication number: 20110062543
    Abstract: The present invention provides a photoelectric conversion device capable of detecting light from weak light to strong light and relates to a photoelectric conversion device having a photodiode having a photoelectric conversion layer; an amplifier circuit including a transistor; and a switch, where the photodiode and the amplifier circuit are electrically connected to each other by the switch when intensity of entering light is lower than predetermined intensity so that a photoelectric current is amplified by the amplifier circuit to be outputted, and the photodiode and part or all of the amplifier circuits are electrically disconnected by the switch so that a photoelectric current is reduced in an amplification factor to be outputted. According to such a photoelectric conversion device, light from weak light to strong light can be detected.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuo NISHI, Tatsuya ARAO, Atsushi HIROSE, Yuusuke SUGAWARA, Naoto KUSUMOTO, Daiki YAMADA, Hidekazu TAKAHASHI
  • Patent number: 7863077
    Abstract: An image sensor and method of manufacturing the same are disclosed. A semiconductor substrate can be prepared comprising a photodiode region, a transistor region, and a floating diffusion region. A gate dielectric can be disposed under a surface of the semiconductor substrate in the transistor region. A first dielectric pattern can be provided having a portion above and a portion below the surface of the semiconductor substrate in the photodiode and the floating diffusion regions. A second dielectric can be disposed under the gate dielectric. The second dielectric can extend the depth of the gate dielectric into the semiconductor substrate to space the movement path of photoelectrons from the photodiode region to the floating diffusion region.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 4, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Dong Bin Park
  • Publication number: 20100220226
    Abstract: An image sensor includes a semiconductor substrate, a guard ring structure in the substrate, and at least one pixel surrounded by the guard ring structure. The guard ring structure is implanted in the substrate by high-energy implantation.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 2, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-De WANG, Dun-Nian YAUNG, Jen-Cheng LIU, Chun-Chieh CHUANG, Jeng-Shyan LIN
  • Publication number: 20100148283
    Abstract: An integrated structure of MEMS device and CIS device and a fabricating method thereof includes providing a substrate having a CIS region and a MEMS region defined therein with a plurality of CIS devices positioned in the CIS region; performing a multilevel interconnect process to form a multilevel interconnect structure in the CIS region and the MEMS region and a micro-machined mesh metal in the MEMS region on a front side of the substrate; performing a first etching process to form a chamber in MEMS region in the front side of the substrate; forming a first mask pattern and a second mask pattern respectively in the CIS region and the MEMS region on a back side of the substrate; and performing a second etching process to form a plurality of vent holes connecting to the chamber on the back side of the substrate through the second mask pattern.
    Type: Application
    Filed: December 14, 2008
    Publication date: June 17, 2010
    Inventor: Hui-Shen Shih
  • Publication number: 20100078750
    Abstract: An image sensor includes readout circuit arranged over a semiconductor substrate, an interlayer dielectric film covering the readout circuit and including metal lines, a buffer layer arranged over the interlayer dielectric film, a crystallized silicon layer arranged over the buffer layer, an ion-implantation layer to partition photodiode regions corresponding to unit pixels in the crystallized silicon layer, and a metal plug arranged in a via-hole of the buffer layer, to electrically connect the photodiode region to the metal lines. In accordance with the method, a channel, enabling smooth transfer of photocharges, is provided between the photodiode and the readout circuit, to minimize dark current sources and prevent a deterioration in saturation and sensitivity and thereby improve image properties.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Inventor: Oh-Jin Jung
  • Publication number: 20100059848
    Abstract: Embodiments provide an image sensor. The image sensor includes readout circuitry, an interlayer dielectric, an interconnection, and an image sensing device. The interconnection includes a lower barrier metal and a nitride barrier formed under the lower barrier metal. A contact plug electrically connecting the lower barrier metal to a lower interconnect is formed passing through the nitride barrier.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 11, 2010
    Inventor: Ji Hoon Hong
  • Publication number: 20090309232
    Abstract: A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal.
    Type: Application
    Filed: April 28, 2009
    Publication date: December 17, 2009
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • Publication number: 20090215215
    Abstract: A method is provided for producing a hybrid multi-junction photovoltaic device. The method begins by providing a plurality of planar photovoltaic semi-transparent modules. Each of the modules is a fully functional, thin-film, photovoltaic device and includes first and second conductive layers and at least first and second semiconductor layers disposed between the conductive layers. The first and second semiconductor layers define a junction at an interface therebetween. The method continues by disposing the modules one on top of another and hybridly adhering them to each other. At least one of the modules is configured to convert a first spectral portion of optical energy into an electrical voltage and transmit a second spectral portion of optical energy to another of the junctions that is configured to convert at least part of the second spectral portion of optical energy into an electrical voltage.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: Sunlight Photonics Inc.
    Inventors: Sergey Frolov, Michael Cyrus
  • Publication number: 20090121264
    Abstract: A CMOS image sensor is formed utilizing a through-poly implantation process. First, a substrate including a photo-sensing region and a transistor region is provided. Subsequently, at least a gate structure is formed on a surface of the substrate within the transistor region. Thereafter, an ion implantation process is performed on the substrate to form a first conductive type well in the substrate through the gate structure. Since the ion implantation process implants ions into the substrate to a channel region of the transistor through the gate structure, the implant depth of the uncovered parts of the substrate is deeper than the implant depth of the parts of the substrate covered by the gate structure, and defects caused by the energy of the ion implantation process are prevented within the channel region.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Inventor: Ching-Hung Kao
  • Publication number: 20080283880
    Abstract: An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Applicant: FOVEON, INC.
    Inventors: Richard B. Merrill, Shri Ramaswami, Glenn J. Keller
  • Publication number: 20080188028
    Abstract: A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield region of a high concentration disposed at the surface of the upper region and spaced at an interval from the electrode contact region and connected to a ground potential, and a first-conduction-type second shield region of a low concentration disposed between the electrode contact region and the first shield region at the surface of the upper region so as to surround the electrode contact region, and further, is connected to the ground potential.
    Type: Application
    Filed: April 2, 2008
    Publication date: August 7, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Yushi SEKIGUCHI
  • Publication number: 20080173967
    Abstract: Disclosed is an image sensor, which includes a dielectric layer on a substrate having a photodiode, a metal interconnection layer on the dielectric layer and an upper insulating layer on the metal interconnection layer. The metal interconnection layer includes a lower barrier layer, a bulk metal layer on the lower barrier layer and an upper barrier layer on the bulk metal layer having a predetermined thickness which is 0.8 to 1.5 times as thick as the lower barrier layer.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 24, 2008
    Inventor: Woo Seok Hyun
  • Publication number: 20080153193
    Abstract: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.
    Type: Application
    Filed: March 6, 2008
    Publication date: June 26, 2008
    Inventor: Jeong Ho Lyu
  • Patent number: 7368750
    Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; a semiconductor layer of a first conduction type that is formed on the semi-insulating substrate; a buffer layer of the first conduction type that is formed on the semi-insulating substrate and has a lower impurity concentration than the semiconductor layer of the first conduction type; a light absorption layer that is formed on the buffer layer and generates carriers in accordance with incident light; a semiconductor layer of a second conduction type that is formed on the light absorption layer; and a semiconductor intermediate layer that is interposed between the buffer layer and the light absorption layer, and has a forbidden bandwidth within a range lying between the forbidden bandwidth of the buffer layer and the forbidden bandwidth of the light absorption layer.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Gang Wang, Yoshihiro Yoneda