Abstract: A photodetector includes: a semiconductor substrate having a first main surface and a second main surface; a first semiconductor layer that is of a first conductivity type, and is included in the semiconductor substrate and closer to the first main surface than to the second main surface; a second semiconductor layer that is of a second conductivity type different from the first conductivity type, and is included in the semiconductor substrate and interposed between the first semiconductor layer and the second main surface; a multiplication region that causes avalanche multiplication to a charge generated in the semiconductor substrate through photoelectric conversion; a circuit region disposed alongside the first semiconductor layer in a direction parallel to the first main surface; at least one isolation transistor disposed in the circuit region; and an isolation region interposed between the first semiconductor layer and the circuit region.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Abstract: An ionizing radiation detector includes a first common semiconductor substrate and a first plurality of single-photon avalanche diode (SPAD) microcell structures disposed at a top face of the first common semiconductor substrate. Each SPAD microcell structure includes a first semiconductor junction that is reverse-biased beyond a first breakdown threshold. The ionizing radiation detector may also include common anode and cathode connections to each of the SPAD microcell structures that operate as an output. The ionizing radiation detector may also include control circuitry connected to the SPAD microcell structures. The control circuitry may be configured to control biasing of the SPAD microcell structures and measure electrical characteristics of a signal provided on the output. Charge drift within the first common semiconductor substrate need not be inhibited from exciting more than one of the SPAD microcell structures of the first plurality of SPAD microcell structures by isolation barriers.

Abstract: There is provided a solid-state image pickup element including a pixel array part in which a plurality of pixels are arranged on a silicon substrate in arrays, and a drive part driving the pixel. The pixel includes a photoelectric conversion part formed near a second face of the silicon substrate opposite to a first face on which a wiring layer is laminated, for generating a charge corresponding to incident light, an overflow part formed in contact with the second face and fixed to a predetermined voltage, and a potential barrier part formed to be connected with the photoelectric conversion part and the overflow part, for serving as a barrier against a charge overflowed from the photoelectric conversion part on the overflow part.

Abstract: Systems and methods for dry eteching a photodetector array based on InAsSb are provided. A method for fabricating an array of photodetectors includes receiving a pattern of an array of photodetectors formed from InAsSb, the pattern including at least one trench defined between adjacent photodetectors, and dry etching the at least one trench with a plasma including BrCl3 and Ar.

Abstract: An image sensor includes a substrate having a front side and a back side, an insulating structure containing circuits on the front side of the substrate, contact holes extending through the substrate to the circuits, respectively, and a plurality of pads disposed on the backside of the substrate, electrically connected to the circuits along conductive paths extending through the contact holes, and located directly over the circuits, respectively. The image sensor is fabricated by a process in which a conductive layer is formed on the back side of the substrate and patterned to form the pads directly over the circuits.

Abstract: An interlayer insulating film is disposed above an image pickup region and a peripheral region of the semiconductor substrate. An opening is formed in the interlayer insulating film at a position overlying a photoelectric conversion portion. A waveguide member is formed above the image pickup region and the peripheral region of the semiconductor substrate. A part of the waveguide member, which part is disposed above the peripheral region, is removed such that the interlayer insulating film is exposed.

Abstract: A photoelectric conversion apparatus includes: an active matrix-type TFT array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape.

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.

Abstract: A method for manufacturing a solid-state image sensor having a pixel region, a peripheral circuit region, and an intermediate region interposed between the pixel region and the peripheral circuit region, includes forming a high melting point metal compound in active regions of the peripheral circuit region and the intermediate region, forming an etch stop film on the high melting point metal compound formed in the active regions of the peripheral circuit region and the intermediate region, forming an interlayer insulating film on the etch stop film, and forming, by using the etch stop film, a contact plug to contact the high melting point metal compound in the active region of the peripheral circuit region.

Abstract: A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.

Abstract: A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.

Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, wherein the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and a width of the gap in a direction along the second electrically conductive line is not larger than a width of the first electrically conductive line.

Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.

Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.

Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

Abstract: A wiring board with a built-in imaging element includes a substrate having an accommodation portion and a first surface and a second surface on the opposite side of the first surface, an imaging device having a light receiver and positioned in the accommodation portion of the substrate such that the light receiver faces the first surface of the substrate, and a buildup structure formed on the first surface of the substrate and having insulation layers and conductive layers. The buildup structure has an opening portion formed such that the light receiver of the imaging device is exposed from the opening portion of the buildup structure, and the insulation layers in the buildup structure include a first insulation layer formed on the first surface of the substrate.

Abstract: An electrically conductive ribbon, which is soldered on an electrically conductive busbar of a photovoltaic panel, includes a cooper core and a tin based solder. The tin based solder fully wraps an outer surface of the cooper core, and has a convex solder surface, which has a first curvature to be fitted with a second curvature of a concave solder surface of the electrically conductive busbar.

Abstract: A solar cell includes negative metal contact fingers and positive metal contact fingers. The negative metal contact fingers are interdigitated with the positive metal contact fingers. The metal contact fingers, both positive and negative, have a radial design where they radially extend to surround at least 25% of a perimeter of a corresponding contact pad. The metal contact fingers have bend points, which collectively form a radial pattern with a center point within the contact pad. Exactly two metal contact pads merge into a single leading metal contact pad that is wider than either of the exactly two metal contact pads.

Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.

Abstract: An integrated circuit structure or a back side illumination image sensor is provided, wherein the integrated circuit structure includes a bond pad and a metal structure located in a dielectric layer, wherein the bond pad and the metal structure have different materials, and the back side illumination image sensor includes an image sensor unit and an interconnect structure respectively located on both sides of a bond pad. Moreover, an integrated circuit process forming said integrated circuit structure or back side illumination image sensor is also provided.

Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

Abstract: A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.

Abstract: A semiconductor light-receiving device includes a semiconductor light-receiving element that has a first electrode and a second electrode, a first wiring coupled to the first electrode, and a second wiring coupled to the second electrode, a width of the second wiring being smaller than a width of the first wiring.

Abstract: A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least first, second and third series-connected cells on a support, each cell being a laminated structure comprising a junction layer including semiconducting material of a first and second type, a front electrode formed of a transparent conductive oxide resistant to an etchant disposed in electrical contact with the semiconducting material of the first type, and a back electrode in electrical contact with the semiconducting material of the second type. A portion of both the back electrode and the junction layer are separated from a selected parent solar cell. Using the separated portion of the back electrode the semiconducting material of the second type of the separated portion of the junction layer is connected to the semiconducting material of the first type of any one chosen solar cell in the array.

Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.

Abstract: A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Abstract: The present invention provides a display apparatus for capturing images. The display apparatus includes a first substrate, a pixel array disposed on the first substrate, a thin film transistor array disposed in the pixel array and a photodetector array disposed in the pixel array. The pixel array includes a plurality of sub-pixels. The thin film transistor array controls image data transferred to the pixel array. When a light illuminates a sub-pixel of the pixel array, a photodetector corresponding to the sub-pixel of the photodetector array generates a leakage current in response to a gray-level of the light.

Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.

Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.

Abstract: A solar cell assembly provides a solar cell with a reduced size potting ring that retains the conductive contact strips that extend through the solar cell substrate and are coupled to the solar cell circuitry on the front surface of the solar cell substrate. A reduced volume of potting material is required and the solar cells are advantageously packed, shipped and stored in this configuration. Diode connections and power cable connections are made external the potting box once the solar cell assemblies are received at their installation location.

Abstract: Designs of image sensors with subpixels are disclosed. According to one aspect of an image sensor in one embodiment, subpixels within a pixel are designed without significantly increasing the cell or pixel area of the pixel. The readouts from the subpixels are accumulated to increase the sensitivity of the pixel without increasing the area of the image sensor. According to another aspect of the image sensors in the present invention, some subpixels within a pixel are respectively coated with filters, each designed for a frequency range. Thus the frequency response of a CMOS image sensor can be enhanced significantly according to application.

Abstract: According to an embodiment, a light-receiving circuit includes a MOSFET, a first light-receiving element and a second light-receiving element. The first light-receiving element controls a state of the MOSFET between ON state and OFF state by applying a voltage induced by a light signal between a gate of the MOSFET and a source of the MOSFET; and a second light-receiving element controls a threshold voltage of the MOSFET.

Abstract: Embodiments provide a chip device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick. A bonding wire is electrically connected to the bonding pad.

Abstract: Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.

Abstract: A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least three series-connected solar cells, each cell being a laminated structure including semiconducting material of first and second types, a front electrode in contact with the material of the first type, and a back electrode in contact with the material of the second type. The bypass diode is formed by total separation from a selected parent cell. The material of the first type of the diode is connected to the material of the second type of any one chosen solar cell in the array. The material of the second type of the diode is connected with the material of the first type of the one chosen solar cell in the array so that the diode is connected in parallel and in opposition to the one chosen solar cell.

Abstract: The present invention discloses a flip chip packaging structure which is applied to a process of a compact camera module (CCM), and the structure thereof comprises an image sensor component, at least one connection member, a circuit board and an insulating plate. The image sensor component is electrically connected with the circuit board via an electrical-conduction of the connection body. Hence, by disposing the insulating plate between the image sensor component and the circuit board, the present invention not only can provide a thermal insulating protection to the image sensor component but also use enough space to execute a surface mount technology (SMT), so as to simplify the flip chip process and to increase the yield of manufacture.

Abstract: An image sensor module includes a substrate, a circuit layer, a flip chip, an insulating layer, and a conducting layer. The substrate has at least one transparent area and defines a first surface and a second surface. The circuit layer is provided on the first surface of the substrate. The flip chip is connected to the circuit layer. The insulating layer substantially encases the flip chip and a part of the circuit layer, wherein the insulating layer has at least one groove at a lateral side of said insulating layer thereof each provided with a metal layer. The conducting layer is provided on a top surface of the insulating layer, wherein the conducting layer is electrically connected to the circuit layer via the metal layer.

Abstract: An aspect of the invention provides a method for measuring I-V characteristics of a solar cell, the solar cell comprising a plurality of fine line-shaped electrodes formed on a first surface in a predetermined direction; and a coupling line formed on the first surface that electrically couples at least two fine line-shaped electrodes among the plurality of fine line-shaped electrodes, the coupling line having a line width larger than a line width of the fine line-shaped electrodes. The method includes: contacting a probe pin for voltage measurement with the coupling line; contacting two or more probe pins for current measurement electrically connected to each other with two or more fine line-shaped electrodes including the fine line-shaped electrodes coupled to each other by the coupling line among the plurality of fine line-shaped electrodes; and measuring I-V characteristics while irradiating the first surface with light.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: An integrated back sheet for a back-contact solar cell module and a back-contact solar cell module made with such an integrated back-sheet are provided. Processes for making such integrated back-sheets and back-contact solar cell modules incorporating such integrated back-sheets are also provided. Elongated electrically conductive wires that extend at least two times the length of solar cells in the back-contact cell module are mounted on a layer of the integrated back-sheet. The elongated conductive wires of the integrated back-sheet electrically connect to solar cell back contacts when the back-sheet is used in a back-contact photovoltaic module.

Abstract: Embodiments of the invention generally relate to methods for performing rear-point-contact processes on substrates, particularly solar cell substrates. The methods generally include disposing a substrate on a substrate support which functions as a mask during deposition of a passivation layer on a back surface of the substrate. A process gas is introduced to an area between the back surface of the substrate and the substrate support in order to deposit the passivation layer on the back surface of the substrate. The deposited passivation layer has openings therethrough in order to facilitate electrical contact of the substrate with a metallization layer subsequently formed over the passivation layer. The passivation layer is formed without requiring a separate patterning and etching process of the passivation layer.

Abstract: This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.

Abstract: Detector modules and methods of manufacturing are provided. One detector module includes a detector having a silicon wafer structure formed from a first layer having a first resistivity and a second layer having a second resistivity, wherein the first resistivity is greater than the second resistivity. The detector further includes a photosensor device provided with the first layer on a first side of the silicon wafer and one or more readout electronics provided with the second layer on a second side of the silicon wafer, with the first side being a different side than the second side.

Abstract: An actuatable punch assembly forms a hole within an article. The actuatable punch assembly comprises a base plate coupled to the actuator. At least one segment block is adjustably coupled to the base plate. At least one cutting device for forming the hole within the article is coupled to the segment block. The segment block is adjustable relative to the base plate. The cutting device is adjustable relative to the segment block. As such, the cutting device is adjustable relative to the base plate for varying a position of the cutting device relative to the article to vary a size of the hole formed in the article.

Abstract: A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction mismatch between the layers. The adhesive material is required to have an associated viscosity such that, when provided under predetermined conditions, the adhesive stops wicking before reaching, and possibly degrading the performance of, the circuit elements.

Abstract: Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Throughput of the solar cell ablation process is improved by incorporating linear base diffusion regions with narrow width, for example as compared to an overlying metal contact. Throughput of the solar cell ablation process may also be improved by having contact holes to base diffusion regions that are perpendicular to contact holes to emitter diffusion regions. To allow for continuous laser scanning, a laser blocking layer may be located over an interlayer dielectric to prevent contact hole formation on certain regions, such as regions where a metal contact of one polarity may electrically shunt to a diffusion region of opposite polarity. In a hybrid design, a solar cell may have both linear and dotted base diffusion regions. An electro-optical modulator may be employed to allow for continuous laser scanning in dotted base diffusion designs.