Device Working In Avalanche Mode (epo) Patents (Class 257/E31.116)
  • Patent number: 12066580
    Abstract: A photodetection device includes a substrate and a plurality of pixel units. The plurality of pixel units includes a pixel unit including a first photodetector in an active area, and a pixel unit including a second photodetector in an inactive area. The first photodetector includes a first lower electrode layer, a first lower extrinsic semiconductor layer, a first intrinsic semiconductor layer, a first upper extrinsic semiconductor layer, and a first upper electrode layer. The second photodetector includes a second lower electrode layer, a second lower extrinsic semiconductor layer, a second intrinsic semiconductor layer, a second upper extrinsic semiconductor layer, and a second upper electrode layer. The second lower electrode layer is covered with the second lower extrinsic semiconductor layer and the second intrinsic semiconductor layer.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 20, 2024
    Assignee: Kyocera Corporation
    Inventors: Noboru Noguchi, Yasuhiro Yanagihara, Nobuyuki Shima
  • Patent number: 11984525
    Abstract: An apparatus wherein, in plane view, a first semiconductor region of a first conductivity type overlaps at least a portion of a third semiconductor region, a second semiconductor region overlaps at least a portion of a fourth semiconductor region of a second conductivity type, a height of a potential of the third semiconductor region with respect to an electric charge of the first conductivity type is lower than that of the fourth semiconductor region, and a difference between a height of a potential of the first semiconductor region and that of the third semiconductor region is larger than a difference between a height of a potential of the second semiconductor region and that of the fourth semiconductor region.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: May 14, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuhiro Morimoto, Mahito Shinohara
  • Patent number: 11721779
    Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 8, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Rahmi Hezar, Henry Litzmann Edwards
  • Patent number: 11703575
    Abstract: A photodetector includes a plurality of channels each having a plurality of SPAD units, each SPAD unit having an avalanche photodiode. The photodetector is capable of selecting outputting or non-outputting of the channels. The SPAD unit includes: an active quenching circuit which performs active quenching of the avalanche photodiode; and a control circuit which brings the active quenching circuit which corresponds to the channel where non-outputting is selected into an operable state.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: July 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Kubota, Nobu Matsumoto
  • Patent number: 11552200
    Abstract: An avalanche photo-diode (APD) circuit includes a first APD and a bias circuit. The first APD is configured to detect light. The bias circuit is configured to control a gain of the first APD. The bias circuit includes a second APD, a reference voltage source, a bias voltage generation circuit, and a metal layer configured to shield the second APD from the light. The reference voltage source is configured to bias the second APD. The bias voltage generation circuit is configured to generate a bias voltage for biasing the first APD based on dark current output by the second APD.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gerd Schuppener, Miaad Aliroteh, Srinath Ramaswamy, Baher Haroun
  • Patent number: 8779543
    Abstract: A semiconductor device that may include an avalanche photodiode (APD), the APD may include: a first doped region of a first polarity; a buried guard ring of a second polarity, the second polarity is opposite to the first polarity, the buried guard ring is spaced apart from the first doped region and is positioned below the first doped region; a well of the second polarity, wherein the well interfaces the first doped region to form a p-n junction; and a second doped region of the second polarity, the second doped region is spaced apart from the first doped region.
    Type: Grant
    Filed: September 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Technion Research and Development Foundation Ltd.
    Inventors: Yael Nemirovsky, Vitali Savuskan, Sharon Bar-Lev Shefi, Igor Brouk, Gil Visokolov, Amos Fenigstein, Tomer Leitner
  • Patent number: 8742543
    Abstract: The invention is directed to an avalanche photodiode containing a substrate and semiconductor layers with various electro-physical properties having common interfaces both between themselves and with the substrate. The avalanche photodiode may be characterized by the presence in the device of at least one matrix consisting of separate solid-state areas with enhanced conductivity surrounded by semiconductor material with the same type of conductivity. The solid-state areas are located between two additional semiconductor layers, which have higher conductivity in comparison to the semiconductor layers with which they have common interfaces. The solid-state areas are generally made of the same material as the semiconductor layers surrounding them but with conductivity type that is opposite with respect to them. The solid-state areas may be made of a semiconductor with a narrow forbidden zone with respect to the semiconductor layers with which they have common interfaces.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: June 3, 2014
    Inventors: Ziraddin Yagub-Ogly Sadygov, Abdelmounairne Faouzi Zerrouk
  • Patent number: 8698268
    Abstract: An avalanche photodiode including a first electrode; and a substrate including a first semiconductor layer of a first conduction type electrically connected to the first electrode, in which at least an avalanche multiplication layer, a light absorption layer, and a second semiconductor layer of a second conduction type with a larger band gap than the light absorption layer are deposited on the substrate. The second semiconductor layer is separated into inner and outer regions by a groove formed therein, the inner region electrically connected to a second. With the configuration, the avalanche photodiode has a low dark current and high long-term reliability. In addition, the outer region includes an outer trench, and at least the light absorption layer is removed by the outer trench to form a side face of the light absorption layer. With the configuration, the dark current can be further reduced.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eiji Yagyu, Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 8610231
    Abstract: A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p?-type semiconductor layer 13 formed on the n-type semiconductor layer 12 of the substrate 2; resistors 4 each of which is provided to each of the photodetector channels 10 and is connected to a signal conductor 3 at one end thereof; and an n-type separating part 20 formed between the plurality of photodetector channels 10. The p?-type semiconductor layer 13 forms a pn junction at the interface between the substrate 2, and comprises a plurality of multiplication regions AM for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 17, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kazuhisa Yamamura, Kenichi Sato
  • Patent number: 8574945
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8471293
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Publication number: 20110284926
    Abstract: An avalanche photodiode structure, to a method of fabricating an avalanche photodiode structure, and to devices incorporating an avalanche photodiode structure. The avalanche photodiode structure comprises a Ge doped region having a first polarity; a GaAs doped region having a second polarity opposite to the first polarity; and an undoped region between the Ge doped region and the GaAs doped region forming a heterojunction; wherein the undoped region comprises Ge and AlxGa1-xAs.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 24, 2011
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventor: Ching Kean Chia
  • Patent number: 8008741
    Abstract: A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p?-type semiconductor layer 13 formed on the n-type semiconductor layer 12 of the substrate 2; resistors 4 each of which is provided to each of the photodetector channels 10 and is connected to a signal conductor 3 at one end thereof; and an n-type separating part 20 formed between the plurality of photodetector channels 10. The p?-type semiconductor layer 13 forms a pn junction at the interface between the substrate 2, and comprises a plurality of multiplication regions AM for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: August 30, 2011
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kazuhisa Yamamura, Kenichi Sato
  • Patent number: 7910953
    Abstract: An optical semiconductor device includes a distributed Bragg reflection layer of a first conductivity type, a distortion elaxation layer of the first conductivity type, a light absorbing layer, and a semiconductor layer of a second conductivity type, sequentially arranged on a semiconductor substrate. The distortion relaxation layer the same material as the semiconductor substrate. The total optical length of layers between the distributed Bragg reflection layer and the light absorbing layer is an integer multiple of one-half the wavelength of incident light that is detected.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: March 22, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaharu Nakaji, Eitaro Ishimura, Eiji Yagyu
  • Patent number: 7898051
    Abstract: An imaging device is provided and includes: a photoelectric conversion layer that has a silicon crystal structure and generates signal charges upon incidence of light; a multiplication and accumulation layer that multiplies the signal charges by a phenomenon of avalanche electron multiplication; and a wiring substrate that reads the signal charges from the multiplication and accumulation layer and transmits the read signal charges.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 1, 2011
    Assignee: FUJIFILM Corporation
    Inventor: Shinji Uya
  • Patent number: 7863647
    Abstract: An avalanche photodiode semiconductor device (20) for converting an impinging photon (22) includes a base n+ doped material layer (52) formed having a window section (72) for passing the photon (22). An n? doped material layer (30) is formed on the n+ doped material layer (52) having a portion of a lower surface (74) suitably exposed. An n+ doped material layer (32) is formed on the n? doped material (30). A p+ layer (24) formed on top of the n+ doped layer (32). At least one guard ring (26) is formed in the n? doped layer (30).
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: January 4, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 7851823
    Abstract: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 ?m reaches the wavelength selection/absorption layer through the InP window layer. Then, the light is absorbed by the wavelength selection/absorption layer and drawn from the device as an electric current signal. Light with a wavelength of 1.55 ?m reaches the transmitted light absorption/recombination layer through the barrier layer. Then, the light is absorbed by the transmitted light absorption/recombination layer, generating electrons and holes. These electrons and holes recombine with each other and, hence, disappear.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: December 14, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Eitaro Ishimura
  • Patent number: 7719029
    Abstract: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: May 18, 2010
    Assignee: Princeton Lightwave, Inc.
    Inventor: Mark Allen Itzler
  • Publication number: 20090184317
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato SANFILIPPO, Emilio Antonio SCIACCA, Piero Giorgio FALLICA, Salvatore Antonio LOMBARDO
  • Publication number: 20090184384
    Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Delfo Nunziato Sanfilippo, Piero Giorgio Fallica
  • Patent number: 7560751
    Abstract: In a semiconductor photo-detecting element (an avalanche photodiode), a high-sensitivity element is obtained by incorporating a multiplication layer having high-performance multiplication characteristics. By using a structure which reduces an electric field applied to an etching stopper layer, it is possible to use a multiplication layer having higher-performance multiplication characteristics (a multiplication layer which performs multiplication with a high electric field). The first method to realize this is to use a conductivity type multiplication layer. The second method is to use a structure in which a field buffer layer of the second conductivity type is incorporated. As a result of the use of these methods, a structure which applies an electric field lower than the multiplier electrical field to the etching stopper layer is obtained.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: July 14, 2009
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Takeshi Nakata, Kikuo Makita, Atsushi Shono
  • Patent number: 7432537
    Abstract: An avalanche photodiode (APD) includes an anode layer, a cathode layer, an absorption layer between the anode layer and the cathode layer, a first multiplying stage between the absorption layer and the cathode layer, a second multiplying stage between the first multiplying stage and the cathode layer, and a carrier relaxation region between the first and second multiplying stages. Each multiplying stage includes, in the direction of drift of electrons, a first layer that is doped with acceptors, a second layer that is substantially undoped, a third layer that is doped with acceptors, a fourth layer that is substantially undoped, and a fifth layer that is doped with donors.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: October 7, 2008
    Assignee: Voxtel, Inc.
    Inventor: Andrew S. Huntington
  • Patent number: 7368750
    Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; a semiconductor layer of a first conduction type that is formed on the semi-insulating substrate; a buffer layer of the first conduction type that is formed on the semi-insulating substrate and has a lower impurity concentration than the semiconductor layer of the first conduction type; a light absorption layer that is formed on the buffer layer and generates carriers in accordance with incident light; a semiconductor layer of a second conduction type that is formed on the light absorption layer; and a semiconductor intermediate layer that is interposed between the buffer layer and the light absorption layer, and has a forbidden bandwidth within a range lying between the forbidden bandwidth of the buffer layer and the forbidden bandwidth of the light absorption layer.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Gang Wang, Yoshihiro Yoneda
  • Publication number: 20070090397
    Abstract: In a semiconductor photo-detecting element (an avalanche photodiode), a high-sensitivity element is obtained by incorporating a multiplication layer having high-performance multiplication characteristics. By using a structure which reduces an electric field applied to an etching stopper layer, it is possible to use a multiplication layer having higher-performance multiplication characteristics (a multiplication layer which performs multiplication with a high electric field). The first method to realize this is to use a conductivity type multiplication layer. The second method is to use a structure in which a field buffer layer of the second conductivity type is incorporated. As a result of the use of these methods, a structure which applies an electric field lower than the multiplier electrical field to the etching stopper layer is obtained.
    Type: Application
    Filed: February 4, 2005
    Publication date: April 26, 2007
    Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATION
    Inventors: Takeshi Nakata, Kikuo Makita, Atsushi Shono