Texturized Surface (epo) Patents (Class 257/E31.13)
  • Patent number: 10468289
    Abstract: Provided is a substrate holding member that includes a base body and a plurality of protrusions formed on a surface of the base body and that is capable of suppressing generation of particles due to peeling-off or cracking of protective layers of the protrusions. A substrate holding member includes a base body and a plurality of protrusions formed on a surface of the base body. Each of the protrusions includes a base portion and a protective layer, the base portion having a flat upper end surface and being made from a silicon carbide sintered compact, the protective layer being made of silicon carbide. The protective layer includes a region on at least a part of the base portion from an edge of the upper end surface to a lower end of the base portion, the region being exposed along an entire periphery. Preferably, the protective layer is formed so as to cover at least only a part of an upper portion of the base portion, the upper portion including the upper end surface.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: November 5, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tomohiro Ishino, Takashi Teshima
  • Patent number: 9799783
    Abstract: Dopant ink compositions and methods of fabricating solar cells there from are described. A dopant ink composition may include a cross-linkable matrix precursor, a bound dopant species, and a solvent. A method of fabricating a solar cell may include delivering a dopant ink composition to a region above a substrate. The dopant ink composition includes a cross-linkable matrix precursor, a bound dopant species, and a solvent. The method also includes baking the dopant ink composition to remove a substantial portion of the solvent of the dopant ink composition, curing the baked dopant ink composition to cross-link a substantial portion of the cross-linkable matrix precursor of the dopant ink composition, and driving dopants from the cured dopant ink composition toward the substrate.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 24, 2017
    Assignee: SunPower Corporation
    Inventors: Paul Loscutoff, Kahn Wu, Steven Edward Molesa
  • Patent number: 9537025
    Abstract: Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 3, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Gregg S. Higashi, Frank Reinhardt, Sylvia Spruytte
  • Patent number: 9419153
    Abstract: A solar cell segment includes a substrate defining a rear side including a number of base doped regions and emitter doped regions. A dielectric layer and at least one metallizing layer are disposed on the rear side of the substrate. The at least one metallizing layer is structured in an interdigital comb-shaped contact deck arrangement and defines base contact decks for a number of base doped regions and emitter contact decks for a number of base doped regions. The at least one metallization layer is disposed between the rear side of the substrate and the dielectric layer. At least one first row of first contact openings is formed in the dielectric layer lying in a region of the base contact decks and at least one second row of second contact openings is formed in the dielectric layer lying in a region of the emitter contact decks.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 16, 2016
    Assignee: SolarWorld Innovations GmbH
    Inventor: Hans-Joachim Krokoszinski
  • Patent number: 9018033
    Abstract: A method of manufacturing solar cells is disclosed. The method comprises depositing an etch-resistant dopant material on a silicon substrate, the etch-resistant dopant material comprising a dopant source, forming a cross-linked matrix in the etch-resistant dopant material using a non-thermal cure of the etch-resistant dopant material, and heating the silicon substrate and the etch-resistant dopant material to a temperature sufficient to cause the dopant source to diffuse into the silicon substrate.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 28, 2015
    Assignee: SunPower Corporation
    Inventors: Kahn C. Wu, Steven M. Kraft, Paul Loscutoff, Steven Edward Molesa
  • Patent number: 9012933
    Abstract: A light-emitting diode includes a substrate, the substrate including an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer includes a first portion and a second portion, and the second portion includes an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion includes a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: April 21, 2015
    Assignee: Epistar Corporation
    Inventors: Liang-Sheng Chi, Pei-Chia Chen, Chih-Hao Chen
  • Patent number: 9000414
    Abstract: An object of the present invention is to provide a light emitting diode having a heterogeneous material structure and a method of manufacturing thereof, in which efficiency of extracting light to outside is improved by forming depressions and prominences configured of heterogeneous materials different from each other before or in the middle of forming a semiconductor material on a substrate in order to improve the light extraction efficiency.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 7, 2015
    Assignee: Korea Photonics Technology Institute
    Inventors: Sang-Mook Kim, Jong-Hyeob Baek
  • Patent number: 9000492
    Abstract: In a back-illuminated solid-state image pickup device including a semiconductor substrate 4 having a light incident surface at a back surface side and a charge transfer electrode 2 disposed at a light detection surface at an opposite side of the semiconductor substrate 4 with respect to the light incident surface, the light detection surface has an uneven surface. By the light detection surface having the uneven surface, etaloning is suppressed because lights reflected by the uneven surface have scattered phase differences with respect to a phase of incident light and resulting interfering lights offset each other. A high quality image can thus be acquired by the back-illuminated solid-state image pickup device.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 7, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hisanori Suzuki, Yasuhito Yoneta, Yasuhito Miyazaki, Masaharu Muramatsu, Koei Yamamoto
  • Patent number: 8969986
    Abstract: An infrared photo-detector with multiple discrete regions of a first absorber material. These regions may have geometric shapes with sloped sidewalls. The detector also may include a second absorber region comprising a second absorber material that absorbs light of a shorter wavelength than the light absorbed by the multiple discrete absorber regions of the first absorber material. The geometric shapes may extend only through the first absorber material. Alternatively, the geometric shapes may extend partially into the second absorber region. The detector has a metal reflector coupled to the multiple discrete absorber regions. The detector also has a substrate containing the discrete absorber regions and the second absorber region. The substrate can further include geometric shaped features etched into the substrate, with those features formed on the side of the substrate opposite the side containing the discrete absorber regions and the second absorber region.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Hasan Sharifi
  • Patent number: 8962373
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 24, 2015
    Assignee: SunPower Corporation
    Inventors: Peter J. Cousins, David D. Smith, Seung Bum Rim
  • Patent number: 8957490
    Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Thoralf Kautzsch
  • Patent number: 8945972
    Abstract: The invention relates to a layered system for producing a solar cell on a metal substrate and to a method of producing the layered system.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: February 3, 2015
    Assignee: Tata Steel Nederland Technology BV
    Inventors: Joost Willem Hendrik Van Krevel, Albertus Johannes Maria Wigchert, Ganesan Palaniswamy
  • Patent number: 8946728
    Abstract: A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles, and having a void therein. A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles or quantum dots, and having a void therein.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu Sang Kim
  • Patent number: 8932896
    Abstract: The solar cell manufacturing apparatus includes: a load lock chamber configured to allow loading and unloading of a substrate by switching between atmospheric ambient and vacuum ambient; a processing chamber where the substrate for a solar cell is to be doped with impurity ions for pn junction formation in the vacuum ambient; and a conveyance chamber including a conveyance unit configured to convey the substrate between the load lock chamber and the processing chamber. The doping of impurity ions is performed by irradiation with the impurity ions from an ion gun, and the ion gun is provided with a grid plate, as its ion irradiation surface, facing the substrate conveyed to the processing chamber.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: January 13, 2015
    Assignee: Ulvac, Inc.
    Inventor: Genji Sakata
  • Patent number: 8933526
    Abstract: An article including a nanostructured functional coating disposed on a substrate is described. The functional coating is characterized by both anti-reflection properties and down-converting properties. Related optoelectronic devices are also described.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: January 13, 2015
    Assignee: First Solar, Inc.
    Inventors: Loucas Tsakalakos, Eric Gardner Butterfield, Alok Mani Srivastava, Bastiaan Arie Korevaar
  • Patent number: 8928106
    Abstract: An electroconductive element includes a substrate having a first wavy surface and a second wavy surface, and an electroconductive layer formed on the first wavy surface, wherein the electroconductive layer forms an electroconductive pattern, and the first wavy surface and the second wavy surface satisfy the following relationship: 0?(Am1/?m1)<(Am2/?m2)?1.8. Am1 is a mean amplitude of vibrations of the first wavy surface, Am2 is a mean amplitude of vibrations of the second wavy surface, ?m1 is a mean wavelength of the first wavy surface, and ?m2 is a mean wavelength of the second wavy surface.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: January 6, 2015
    Assignee: Sony Corporation
    Inventors: Shunichi Kajiya, Kazuya Hayashibe, Sohmei Endoh
  • Patent number: 8916945
    Abstract: Prepared is an n? type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n? type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n? type semiconductor substrate 1 is formed on the second principal surface 1b side of the n type semiconductor substrate 1. After formation of the accumulation layer 11, the n? type semiconductor substrate 1 is subjected to a thermal treatment.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: December 23, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Akira Sakamoto, Takashi Iida, Koei Yamamoto, Kazuhisa Yamamura, Terumasa Nagano
  • Patent number: 8912653
    Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kah Wee Gan, Yonggang Jin, Anandan Ramasamy, Yun Liu
  • Patent number: 8865509
    Abstract: A cleaning method of a silicon substrate includes a first step of etching a surface of a silicon substrate by a metal-ion-containing mixed aqueous solution of an oxidizing agent and hydrofluoric acid and of forming a porous layer on the surface of the silicon substrate, a second step of etching a pore of the porous layer by mixed acid mainly containing hydrofluoric acid and nitric acid and of forming texture on the surface of the silicon substrate, a third step of etching the surface of the silicon substrate on which the texture is formed with an alkaline chemical solution, and a fourth step of treating the silicon substrate etched by the alkaline chemical solution by ozone-containing water, of generating an air bubble within the pore formed in the silicon substrate, and of removing metal and organic impurities from within the pore.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: October 21, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Nishimoto, Nozomu Yasunaga, Takayoshi Matsuda
  • Patent number: 8859322
    Abstract: The present invention relates to cost effective production methods of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 14, 2014
    Assignee: Rec Solar Pte. Ltd.
    Inventors: Richard Hamilton Sewell, Andreas Bentzen
  • Patent number: 8859321
    Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8822259
    Abstract: Embodiments of the invention generally relate to solar cell devices and methods for manufacturing such solar cell devices. In one embodiment, a method for forming a solar cell device includes depositing a conversion layer over a first surface of a substrate, depositing a first transparent conductive oxide layer over a second surface of the substrate that is opposite the first surface, depositing a first p-doped silicon layer over the first transparent conductive oxide layer, depositing a first intrinsic silicon layer over the first p-doped silicon layer, and depositing a first n-doped silicon layer over the first intrinsic silicon layer. The method further includes depositing a second transparent conductive oxide layer over the first n-doped silicon layer, and depositing an electrically conductive contact layer over the second transparent conductive oxide layer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Robert Visser, Vijay Parihar, Randhir P. S. Thakur
  • Patent number: 8815104
    Abstract: A method (300) for etching a silicon surface (116) to reduce reflectivity. The method (300) includes electroless deposition of copper nanoparticles about 20 nanometers in size on the silicon surface (116), with a particle-to-particle spacing of 3 to 8 nanometers. The method (300) includes positioning (310) the substrate (112) with a silicon surface (116) into a vessel (122). The vessel (122) is filled (340) with a volume of an etching solution (124) so as to cover the silicon surface (116). The etching solution (124) includes an oxidant-etchant solution (146), e.g., an aqueous solution of hydrofluoric acid and hydrogen peroxide. The silicon surface (116) is etched (350) by agitating the etching solution (124) with, for example, ultrasonic agitation, and the etching may include heating (360) the etching solution (124) and directing light (365) onto the silicon surface (116). During the etching, copper nanoparticles enhance or drive the etching process.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 26, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Fatima Toor, Howard Branz
  • Patent number: 8816361
    Abstract: Disclosed is a structure combining a solar cell and a light-emitting element. The structure includes a light-emitting device having a substrate and a light-emitting structure disposed on the first surface of the substrate. The substrate includes a plurality of cones formed on a second surface opposite to the first surface. The structure also includes a first conductive layer, disposed on the second surface, a power convention layer disposed on the first conductive layer, a second conductive layer disposed on the power conversion layer, and a patterned transparent layer disposed on the second conductive layer. The patterned transparent layer includes a surface consisting of a plurality of cones and disposed on a side opposite to the second conductive layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Phecda Technology Co. Ltd.
    Inventor: Yong-Fa Huang
  • Patent number: 8809893
    Abstract: The present invention relates to a vertical/horizontal light-emitting diode for a semiconductor.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pun Jae Choi, Sang Bum Lee, Jin Bock Lee, Yu Seung Kim, Sang Yeob Song
  • Patent number: 8808933
    Abstract: A structure comprising an array of semiconductor structures, an infill material between the semiconductor materials, and one or more light-trapping elements is described. Photoconverters and photoelectrochemical devices based on such structure also described.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 19, 2014
    Assignee: California Institute of Technology
    Inventors: Michael D. Kelzenberg, Harry A. Atwater, Ryan M. Briggs, Shannon W. Boettcher, Nathan S. Lewis, Jan A. Petykiewicz
  • Patent number: 8796060
    Abstract: Novel methods of producing photovoltaic cells are provided herein, as well as photovoltaic cells produced thereby, and uses thereof. In some embodiments, a method as described herein comprises doping a substrate so as to form a p+layer on one side and an n+layer on an another side, removing at least a portion of the n+layer, and then forming a second n+layer, such that a concentration of the n-dopant in the second n+layer is variable throughout a surface of the substrate.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: August 5, 2014
    Assignee: Solar Wind Technologies, Inc.
    Inventors: Marat Zaks, Galina Kolomoets, Andrey Sitnikov, Oleg Solodukha
  • Patent number: 8791469
    Abstract: In a semiconductor light emitting element (1) having a sapphire substrate (100), and lower (210) and upper (220) semiconductor layers laminated on the sapphire substrate, the substrate includes a substrate top surface (113), a substrate bottom surface (114), first substrate side surfaces (111) and second substrate side surfaces (112); plural first (121a) and second (122a) cutouts are provided at a border between the first substrate side surface, the second substrate side surface and the substrate top surface; the lower semiconductor layer includes a lower semiconductor bottom surface, a lower semiconductor top surface (213), first lower semiconductor side surfaces (211) and second lower semiconductor side surfaces (212); plural first projecting portions (211a) and plural first depressing portions (211b) are provided on the first lower semiconductor side surface; and plural second protruding portions (212a) and second flat portions (212b) are provided on the second lower semiconductor side surface.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 29, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hironao Shinohara, Kensuke Hirano
  • Patent number: 8790954
    Abstract: An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Yuan-Chih Hsieh, Dun-Nian Yaung, Chung-Yi Yu
  • Patent number: 8790955
    Abstract: Semiconductor photovoltaic cells have surfaces that are textured for processing and photovoltaic reasons. The absorbing regions may have parallel grooves that reduce loss of solar energy that would otherwise be lost by reflection. One form of texturing has parallel grooves and ridges. The cell also includes regions of metallization for collecting the generated electrical carriers and conducting them away, which may be channels. The topography is considered during production, using a process that takes advantage of the topography to govern what locations upon will receive a specific processing, and which locations will not receive such a processing. Liquids are treated directly into zones of the cell. They migrate throughout a zone and act upon the locations contacted. They do not migrate to other zones, due to impediments to fluid flow that are features of the surface texture, such as edges, walls and ridges.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: July 29, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Emanuel M. Sachs, James F. Bredt
  • Patent number: 8779280
    Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a first doped region of a first conductive type formed on a semiconductor substrate of the first conductive type, a second doped region of a second conductive type opposite the first conductive type formed on the semiconductor substrate at a location adjacent to the first doped region, a passivation layer exposing a portion of each of the first and second doped regions, a first electrode formed on the exposed portion of the first doped region, and a second electrode formed on the exposed portion of the second doped region. The first electrode includes a metal seed layer directly contacting the first doped region, and the second electrode includes a metal seed layer directly contacting the second doped region.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 15, 2014
    Assignee: LG Electronics Inc.
    Inventors: Sungeun Lee, Youngho Choe
  • Patent number: 8759849
    Abstract: A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventors: Kenta Masuda, Keiichi Akamatsu, Yuichi Kato
  • Patent number: 8742560
    Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
  • Patent number: 8742530
    Abstract: A conduction element includes a substrate which has a first wave surface and a second wave surface, and a laminate film which is formed on the first wave surface and where two or more layers are laminated, where the laminate film forms a conduction pattern, and the first wave surface and the second wave surface satisfy a relationship below. 0?(Am1/?m1)<(Am2/?m2)?1.8 (Here, Am1: average width of vibration in the first wave surface, Am2: average width of vibration in the second wave surface, ?m1: average wavelength of the first wave surface, ?m2: average wavelength of the second wave surface).
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Shunichi Kajiya, Kazuya Hayashibe
  • Patent number: 8736005
    Abstract: In a photoelectric conversion device capable of adding signals of photoelectric conversion elements included in each of photoelectric conversion units, each of the photoelectric conversion elements includes a first semiconductor region of a first conductivity type for collecting a signal charge, a second semiconductor region of a second conductivity type is arranged between the photoelectric conversion elements arranged adjacent to each other and included in the photoelectric conversion unit, and a third semiconductor region of the second conductivity type is arranged between the photoelectric conversion elements arranged adjacent to each other among the plurality of photoelectric conversion elements and included in different photoelectric conversion units arranged adjacent to each other. An impurity concentration of the second semiconductor region is lower than an impurity concentration of the third semiconductor region.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kobayashi, Takafumi Kishi, Yuichiro Yamashita
  • Patent number: 8728857
    Abstract: A photovoltaic solar cell for generating electricity from sunlight is disclosed. The photovoltaic solar cell comprises a plurality of spaced-apart point contact junctions formed in a semiconductor body to receive the sunlight and generate the electricity therefrom, the plurality of spaced-apart point contact junctions having a first plurality of regions having a first doping type and a second plurality of regions having a second doping type. In addition, the photovoltaic solar cell comprises a first electrical contact electrically connected to each of the first plurality of regions and a second electrical contact electrically connected to each of the second plurality of regions, as well as a passivation layer covering major surfaces and sidewalls of the photovoltaic solar cell.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 20, 2014
    Assignee: Sandia Corporation
    Inventors: Gregory N. Nielson, Jose Luis Cruz-Campa, Murat Okandan, Paul J. Resnick
  • Publication number: 20140124795
    Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 8, 2014
    Applicants: Bay Zu Precision Co., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shun-Ming Chen, Chien-Chih Huang, Joel P. Desouza, Augustin J. Hong, Jeehwan Kim, Chien-Yeh Ku, Devendra K. Sadana, Chuan-Wen Wang
  • Patent number: 8698272
    Abstract: Optoelectronic devices, materials, and associated methods having increased operating performance are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material, a first doped region in the semiconductor material, a second doped region in the semiconductor material forming a junction with the first doped region, and a laser processed region associated with the junction. The laser processed region is positioned to interact with electromagnetic radiation. Additionally, at least a portion of a region of laser damage from the laser processed region has been removed such that the optoelectronic device has an open circuit voltage of from about 500 mV to about 800 mV.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 15, 2014
    Assignee: SiOnyx, Inc.
    Inventors: Christopher Vineis, James Carey, Xia Li
  • Patent number: 8685856
    Abstract: A fabrication method of an anti-reflection structure includes the steps of: forming a resin film having micro-particles dispersed therein on a surface of a substrate; forming a protrusion dummy pattern on the resin film by etching the resin film using the micro-particles in the resin film as a mask while gradually etching the micro-particles; and forming a protrusion pattern on the surface of the substrate by etching back the surface of the substrate together with the resin film having the protrusion dummy pattern formed thereon, and transferring a surface shape of the protrusion dummy pattern formed on a surface of the resin film to the surface of the substrate.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: April 1, 2014
    Assignee: Sony Corporation
    Inventors: Kensaku Maeda, Kaoru Koike, Tohru Sasaki, Tetsuya Tatsumi
  • Patent number: 8679889
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 25, 2014
    Assignee: SunPower Corporation
    Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
  • Patent number: 8664737
    Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Selexel, Inc.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
  • Publication number: 20140050492
    Abstract: A high-speed photodiode may include a photodiode structure having a substrate, a light-absorbing layer and a light-directing layer that is deposited on a top surface of the photodiode structure and patterned to form a textured surface used to change the angle of incident light to increase a light path of the incident light when entering the photodiode structure. In one embodiment, the light-directing layer may include a plurality of polygon such as triangular projections to refract the incident light to increase the light path thereof when entering the photodiode structure. In another embodiment, a plurality of nanoscaled sub-triangular projections can patterned on both sides of each triangular projection to more effectively increase the light paths. In a further embodiment, porous materials can be used to form the light-directing layer.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Inventors: Shirong Liao, Jinlin Ye, Bo Liao, Jie Dong
  • Publication number: 20140038338
    Abstract: A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.
    Type: Application
    Filed: June 13, 2012
    Publication date: February 6, 2014
    Inventor: Peter John COUSINS
  • Publication number: 20140038339
    Abstract: A process of manufacturing a crystalline silicon solar cell includes forming a rough surface on a surface of the crystalline silicon wafer and an Al2O3 film is coated on a non-rough surface thereof. A single-sided n diffusion layer and phosphosilicate glass film are formed. An anti-reflection layer SiNx film is formed on a top surface of the phosphosilicate glass film. An Al metallic film is formed as a back ohmic electrode on the Al2O3 film. The local area of the anti-reflection layer SiNx film and the phosphosilicate glass film is melted and removed to form a local area of n+-Si layer. Then, an Al—Si back ohmic contact electrode is formed between the Al metallic film and the crystalline silicon wafer. A front ohmic contact electrode is formed on the molten and removed area of the antireflection layer SiNx film and the phosphosilicate film by light-induced plating.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: Atomic Energy Council-Institute of Nuclear Energy Research
    Inventor: Tsun-Neng Yang
  • Patent number: 8637405
    Abstract: A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mahadevaiyer Krishnan, Jun Liu, Satyavolu S. Papa Rao, George G. Totir
  • Patent number: 8628996
    Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20130330871
    Abstract: A method for modifying the texture of a semiconductor material is provided. The method includes performing a first texture step comprising reactive ion etching to a first surface of semiconductor material. After the first texture step, the first surface of the semiconductor material has a random texture comprising a plurality of peaks and a plurality of valleys, and wherein at least fifty percent of the first surface has a peak-to-valley height of less than one micron and an average peak-to-peak distance of less than one micron. Additional texture steps comprising wet etch or RIE etching may be optionally applied.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Bonna Newman, Venkatesan Murali, Zhiyong Li, Liang Chen
  • Patent number: 8604337
    Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Laura L. Kosbar, Deborah A. Neumayer, Xiaoyan Shao
  • Patent number: 8597970
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 3, 2013
    Assignee: SunPower Corporation
    Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
  • Patent number: 8586397
    Abstract: A method of manufacturing solar cells is disclosed. The method comprises depositing an etch-resistant dopant material on a silicon substrate, the etch-resistant dopant material comprising a dopant source, forming a cross-linked matrix in the etch-resistant dopant material using a non-thermal cure of the etch-resistant dopant material, and heating the silicon substrate and the etch-resistant dopant material to a temperature sufficient to cause the dopant source to diffuse into the silicon substrate.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 19, 2013
    Assignee: SunPower Corporation
    Inventors: Kahn C. Wu, Steven M. Kraft, Paul Loscutoff, Steven Edward Molesa