Texturized Surface (epo) Patents (Class 257/E31.13)
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Patent number: 8698272Abstract: Optoelectronic devices, materials, and associated methods having increased operating performance are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material, a first doped region in the semiconductor material, a second doped region in the semiconductor material forming a junction with the first doped region, and a laser processed region associated with the junction. The laser processed region is positioned to interact with electromagnetic radiation. Additionally, at least a portion of a region of laser damage from the laser processed region has been removed such that the optoelectronic device has an open circuit voltage of from about 500 mV to about 800 mV.Type: GrantFiled: December 21, 2011Date of Patent: April 15, 2014Assignee: SiOnyx, Inc.Inventors: Christopher Vineis, James Carey, Xia Li
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Patent number: 8685856Abstract: A fabrication method of an anti-reflection structure includes the steps of: forming a resin film having micro-particles dispersed therein on a surface of a substrate; forming a protrusion dummy pattern on the resin film by etching the resin film using the micro-particles in the resin film as a mask while gradually etching the micro-particles; and forming a protrusion pattern on the surface of the substrate by etching back the surface of the substrate together with the resin film having the protrusion dummy pattern formed thereon, and transferring a surface shape of the protrusion dummy pattern formed on a surface of the resin film to the surface of the substrate.Type: GrantFiled: March 22, 2010Date of Patent: April 1, 2014Assignee: Sony CorporationInventors: Kensaku Maeda, Kaoru Koike, Tohru Sasaki, Tetsuya Tatsumi
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Patent number: 8679889Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: GrantFiled: December 21, 2011Date of Patent: March 25, 2014Assignee: SunPower CorporationInventors: Peter J. Cousins, David D. Smith, Seung B. Rim
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Patent number: 8664737Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.Type: GrantFiled: January 9, 2012Date of Patent: March 4, 2014Assignee: Selexel, Inc.Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
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Publication number: 20140050492Abstract: A high-speed photodiode may include a photodiode structure having a substrate, a light-absorbing layer and a light-directing layer that is deposited on a top surface of the photodiode structure and patterned to form a textured surface used to change the angle of incident light to increase a light path of the incident light when entering the photodiode structure. In one embodiment, the light-directing layer may include a plurality of polygon such as triangular projections to refract the incident light to increase the light path thereof when entering the photodiode structure. In another embodiment, a plurality of nanoscaled sub-triangular projections can patterned on both sides of each triangular projection to more effectively increase the light paths. In a further embodiment, porous materials can be used to form the light-directing layer.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Inventors: Shirong Liao, Jinlin Ye, Bo Liao, Jie Dong
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Publication number: 20140038339Abstract: A process of manufacturing a crystalline silicon solar cell includes forming a rough surface on a surface of the crystalline silicon wafer and an Al2O3 film is coated on a non-rough surface thereof. A single-sided n diffusion layer and phosphosilicate glass film are formed. An anti-reflection layer SiNx film is formed on a top surface of the phosphosilicate glass film. An Al metallic film is formed as a back ohmic electrode on the Al2O3 film. The local area of the anti-reflection layer SiNx film and the phosphosilicate glass film is melted and removed to form a local area of n+-Si layer. Then, an Al—Si back ohmic contact electrode is formed between the Al metallic film and the crystalline silicon wafer. A front ohmic contact electrode is formed on the molten and removed area of the antireflection layer SiNx film and the phosphosilicate film by light-induced plating.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: Atomic Energy Council-Institute of Nuclear Energy ResearchInventor: Tsun-Neng Yang
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Publication number: 20140038338Abstract: A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.Type: ApplicationFiled: June 13, 2012Publication date: February 6, 2014Inventor: Peter John COUSINS
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Patent number: 8637405Abstract: A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.Type: GrantFiled: June 21, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Mahadevaiyer Krishnan, Jun Liu, Satyavolu S. Papa Rao, George G. Totir
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Patent number: 8628996Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.Type: GrantFiled: June 15, 2011Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Christos Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
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Publication number: 20130330871Abstract: A method for modifying the texture of a semiconductor material is provided. The method includes performing a first texture step comprising reactive ion etching to a first surface of semiconductor material. After the first texture step, the first surface of the semiconductor material has a random texture comprising a plurality of peaks and a plurality of valleys, and wherein at least fifty percent of the first surface has a peak-to-valley height of less than one micron and an average peak-to-peak distance of less than one micron. Additional texture steps comprising wet etch or RIE etching may be optionally applied.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: TWIN CREEKS TECHNOLOGIES, INC.Inventors: Bonna Newman, Venkatesan Murali, Zhiyong Li, Liang Chen
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Patent number: 8604337Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.Type: GrantFiled: September 5, 2012Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: John M. Cotte, Laura L. Kosbar, Deborah A. Neumayer, Xiaoyan Shao
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Patent number: 8597970Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: GrantFiled: December 21, 2011Date of Patent: December 3, 2013Assignee: SunPower CorporationInventors: Peter J. Cousins, David D. Smith, Seung B. Rim
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Patent number: 8586397Abstract: A method of manufacturing solar cells is disclosed. The method comprises depositing an etch-resistant dopant material on a silicon substrate, the etch-resistant dopant material comprising a dopant source, forming a cross-linked matrix in the etch-resistant dopant material using a non-thermal cure of the etch-resistant dopant material, and heating the silicon substrate and the etch-resistant dopant material to a temperature sufficient to cause the dopant source to diffuse into the silicon substrate.Type: GrantFiled: September 30, 2011Date of Patent: November 19, 2013Assignee: SunPower CorporationInventors: Kahn C. Wu, Steven M. Kraft, Paul Loscutoff, Steven Edward Molesa
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Patent number: 8581358Abstract: A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens.Type: GrantFiled: August 16, 2012Date of Patent: November 12, 2013Assignee: Canon Kabushiki KaishaInventor: Sakae Hashimoto
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Patent number: 8574949Abstract: Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.Type: GrantFiled: September 20, 2010Date of Patent: November 5, 2013Assignee: Intermolecular, Inc.Inventors: Jian Li, Minh Anh Nguyen, Nikhil Kalyankar, Nitin Kumar, Craig Hunter
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Patent number: 8569098Abstract: A method for manufacturing a photoelectric conversion device including a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, and a second-conductivity-type semiconductor region that are stacked over an electrode is provided for a new anti-reflection structure. An interface between the electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. The first-conductivity-type crystalline semiconductor region and the intrinsic crystalline semiconductor region are formed by a low pressure chemical vapor deposition method at a temperature higher than 550° C. and lower than 650° C.Type: GrantFiled: June 10, 2011Date of Patent: October 29, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8569099Abstract: Semiconductor photovoltaic cells have surfaces that are textured for processing and photovoltaic reasons. The absorbing regions may have grooves that reduce loss of solar energy that would otherwise be lost by reflection. One form of texturing has grooves and ridges. The cell also includes metallizations for collecting generated electrical carriers and conducting them away, which may be channels. The topography is considered during production, using a process that takes advantage of the topography to govern what locations will receive a specific processing, and which locations will not. Liquids are treated directly into zones. They migrate throughout a zone and act upon the locations contacted. They do not migrate to other zones, due to impediments to flow, such as edges, walls and ridges. Liquid may also be deposited and migrate within a zone, to block or mask a subsequent activity, such as etching.Type: GrantFiled: August 27, 2012Date of Patent: October 29, 2013Assignee: Massachusetts Institute of TechnologyInventors: Emanuel M. Sachs, James F. Bredt
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Patent number: 8563352Abstract: Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well.Type: GrantFiled: March 30, 2010Date of Patent: October 22, 2013Assignee: GTAT CorporationInventors: Mohamed M. Hiliali, S. Brad Herner
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Publication number: 20130247967Abstract: Methods of fabricating solar cells and apparatuses for fabricating solar cells are described. In an example, a method of fabricating a solar cell includes treating a light-receiving surface of a substrate with a gaseous ozone (O3) process. Subsequently, the light-receiving surface of the substrate is texturized.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Inventor: Scott Harrington
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Publication number: 20130252371Abstract: A method for manufacturing a thin film solar cell includes depositing a front electrode on a substrate in a chamber, etching the front electrode formed on the substrate to form an uneven portion on the surface of the front electrode, forming a photoelectric conversion unit on the front electrode, and forming a back electrode on the photoelectric conversion unit. The depositing of the front electrode includes depositing the front electrode while reducing a process pressure of the chamber from a first pressure to a second pressure lower than the first pressure. The etching of the front electrode form the uneven portion of the front electrode so that a top portion of the uneven portion includes a portion formed at the second pressure.Type: ApplicationFiled: November 7, 2012Publication date: September 26, 2013Applicant: LG ELECTRONICS INC.Inventors: Soohyun KIM, Hyun LEE, Jinwon CHUNG, Sehwon AHN
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Publication number: 20130247965Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Inventors: Richard M. Swanson, Marius M. Bunea, Michael C. Johnson, David D. Smith, Yu-Chen Shen, Peter J. Cousins, Tim Dennis
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Publication number: 20130240023Abstract: The present invention relates to cost effective methods for metallisation and or metallisation and interconnection of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections.Type: ApplicationFiled: September 28, 2012Publication date: September 19, 2013Applicant: RENEWABLE ENERGY CORPORATION ASAInventors: Richard Hamilton SEWELL, Alan Francis LYON, Andreas BENTZEN
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Patent number: 8524549Abstract: A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.Type: GrantFiled: July 27, 2011Date of Patent: September 3, 2013Assignee: Samsung Display Co., Ltd.Inventors: Hyung-Jun Kim, Chang-Oh Jeong, Il-Yong Yoon
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Patent number: 8519260Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.Type: GrantFiled: July 8, 2010Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: John M. Cotte, Laura L. Kosbar, Deborah A. Neumayer, Xiaoyan Shao
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Publication number: 20130217171Abstract: The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.Type: ApplicationFiled: September 9, 2012Publication date: August 22, 2013Inventors: Teng-Yu WANG, Chien-Hsun CHEN, Chen-Hsun DU, Chung-Yuan KUNG
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Publication number: 20130181241Abstract: A method of manufacturing a substrate, characterized by a first surface and a second surface, for use in a semiconductor device is provided. The method includes providing a mold having a first template and/or a second template corresponding to a first texture and a second texture respectively. Then, the method includes injection molding a material for the substrate in the mold, to form the substrate, such that the material is injection molded to create the first texture on the first surface and/or the second texture on the second surface. The first texture and/or the second texture facilitate light extraction or light trapping in the semiconductor device.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Inventors: Jan Matthijs Ter Meulen, Patrick Peeters, Erik Jan Prins
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Publication number: 20130167920Abstract: A fabricating method of a conductive substrate including the following steps is provided. A substrate is provided. A barrier layer having a first roughened surface is formed on the substrate by an atmospheric pressure plasma process, wherein the surface roughness (Ra) of the first roughened surface formed by the atmospheric pressure plasma process is between 10 nanometers (nm) and 100 nm. A first electrode layer is formed on the first roughened surface of the barrier layer by a vacuum sputter process, wherein a second roughened surface with the surface roughness (Ra) between 10 nm and 100 nm is formed on a surface of the first electrode layer. Furthermore, a photoelectric conversion layer is formed on the second roughened surface of the first electrode layer. A second electrode layer is formed on the photoelectric conversion layer. A solar cell and a conductive substrate are also provided.Type: ApplicationFiled: August 6, 2012Publication date: July 4, 2013Applicants: BAY ZU PRECISION CO., LTD., INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chia-Chiang Chang, Chin-Jyi Wu, Chun-Hsien Su, Dao-Yang Huang
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Publication number: 20130164878Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
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Publication number: 20130164879Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Inventors: Peter J. Cousins, David D. Smith, Seung B. Rim
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Publication number: 20130153018Abstract: A method for manufacturing a solar cell includes texturing a front surface of a semiconductor substrate having a first conductive type dopant by using a dry etching method, forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate, forming a back passivation film on a back surface of the semiconductor substrate; and forming a first electrode electrically connected to the emitter layer and a second electrode being in partial contact with the back surface of the semiconductor substrate.Type: ApplicationFiled: May 11, 2012Publication date: June 20, 2013Applicant: LG ELECTRONICS INC.Inventors: Kyoungsoo LEE, Myungjun SHIN, Jiweon JEONG
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Publication number: 20130125969Abstract: This disclosure provides photovoltaic apparatus and methods of forming the same. In one implementation, a method of forming a photovoltaic device includes forming a plurality of substrate features on a surface of a glass substrate, the substrate features having a depth dimension in the range of about 10 ?m to about 1000 ?m and a width dimension in the range of about 10 ?m to about 1000 ?m. The method further includes forming a thin film solar cell over the surface of the glass substrate including over the plurality of substrate features.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: QUALCOMM MEMS Technologies, Inc.Inventors: Wilhelmus A. de Groot, Sijin Han, Fan Yang
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Patent number: 8445314Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.Type: GrantFiled: May 24, 2010Date of Patent: May 21, 2013Assignee: Solexel, Inc.Inventors: Suketu Parikh, David Dutton, Pawan Kapur, Somnath Nag, Mehrdad Moslehi, Joe Kramer, Nevran Ozguven, Asli Buccu Ucok
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Publication number: 20130118548Abstract: This disclosure provides photovoltaic modules and methods of making the same. In one implementation, a photovoltaic module includes a plurality of photovoltaic devices configured to absorb light and generate electrical power and a plurality of conductors disposed over the photovoltaic devices. The photovoltaic module further includes a glass layer disposed over the photovoltaic devices, and the glass layer includes a textured surface opposite the plurality of photovoltaic devices. The textured surface includes features configured to diffract light incident the photovoltaic module. The photovoltaic module further includes a diffusive layer disposed over at least a portion of the plurality of conductors.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: QUALCOMM MEMS Technologies, Inc.Inventors: Sandeep K. Giri, Sijin Han
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Publication number: 20130112256Abstract: A photovoltaic device operable to convert light to electricity, comprising a substrate, one or more structures essentially perpendicular to the substrate, and a wavelength-selective layer disposed on the substrate, wherein the structures comprise a crystalline semiconductor material.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Inventors: Young-June YU, Munib WOBER
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Publication number: 20130109127Abstract: A method for making a solar cell includes following steps. A silicon substrate is provided, and the silicon substrate has a first surface and a second surface opposite to the first surface. A patterned mask layer is located on the second surface, and the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side. A slot is defined between each two adjacent protruding structures to expose a portion of the second surface of the silicon substrate. The exposed portion of the second surface is etched to form a protruding pair. The mask layer is removed. A doped silicon layer is located on the three-dimensional nano-structures. An upper electrode is applied on at least part of a surface of the doped silicon layer. A back electrode is placed on the first surface of the silicon substrate.Type: ApplicationFiled: December 29, 2011Publication date: May 2, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITYInventors: ZHEN-DONG ZHU, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20130102107Abstract: It is an object to provide a method for processing a silicon substrate that can reduce surface reflectance as much as possible. The method includes a first step of forming a thin film including a metal having higher electronegativity than silicon and having a plurality of openings on a silicon substrate, a second step of soaking the silicon substrate subjected to the first step in a hydrofluoric acid solution containing oxidizer, and a third step of soaking the silicon substrate subjected to the second step in an ammonia aqueous solution containing oxidizer. By performing the steps in the above order, a minute uneven structure is formed on a surface of the silicon substrate to reduce the reflectance.Type: ApplicationFiled: October 11, 2012Publication date: April 25, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: SEMICONDUCTOR ENERGY LABORATORY CO.
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Patent number: 8420436Abstract: A solar cell manufacturing method according to the present invention is a solar cell manufacturing method that forms a transparent conductive film of ZnO as an electric power extracting electrode on a light incident side, the method comprises at least in a following order: a process A forming the transparent conductive film on a substrate by applying a sputtering voltage to sputter a target made of a film formation material for the transparent conductive film; a process B forming a texture on a surface of the transparent conductive film; a process C cleaning the surface of the transparent conductive film on which the texture has been formed using an UV/ozone; and a process D forming an electric power generation layer on the transparent conductive film.Type: GrantFiled: October 27, 2009Date of Patent: April 16, 2013Assignee: ULVAC, Inc.Inventors: Hirohisa Takahashi, Satoru Ishibashi, Sadayuki Ukishima, Masahide Matsubara, Satoshi Okabe
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Patent number: 8420435Abstract: A front contact thin-film solar cell is formed on a thin-film crystalline silicon substrate. Emitter regions, selective emitter regions, and a back surface field are formed through ion implantation processes. In yet another embodiment, a back contact thin-film solar cell is formed on a thin-film crystalline silicon substrate. Emitter regions, selective emitter regions, base regions, and a front surface field are formed through ion implantation processes.Type: GrantFiled: May 5, 2010Date of Patent: April 16, 2013Assignee: Solexel, Inc.Inventors: Virendra V. Rana, Pawan Kapur, Mehrdad M. Moslehi
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Publication number: 20130081680Abstract: Solar cells with doped groove regions separated by ridges and methods of fabricating solar cells are described. In an example, a solar cell includes a substrate having a surface with a plurality of grooves and ridges. A first doped region of a first conductivity type is disposed in a first of the grooves. A second doped region of a second conductivity type, opposite the first conductivity type, is disposed in a second of the grooves. The first and second grooves are separated by one of the ridges.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Inventors: Steven Edward Molesa, Thomas Pass, Steve Kraft
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Publication number: 20130081687Abstract: A method of manufacturing solar cells is disclosed. The method comprises depositing an etch-resistant dopant material on a silicon substrate, the etch-resistant dopant material comprising a dopant source, forming a cross-linked matrix in the etch-resistant dopant material using a non-thermal cure of the etch-resistant dopant material, and heating the silicon substrate and the etch-resistant dopant material to a temperature sufficient to cause the dopant source to diffuse into the silicon substrate.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Inventors: Kahn C. Wu, Steven M. Kraft, Paul Loscutoff, Steven Edward Molesa
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Publication number: 20130082343Abstract: One of disclosed embodiments provides a photoelectric conversion device, comprising a member including a first surface configured to receive light, and a second surface opposite to the first surface, and a plurality of photoelectric conversion portions aligned inside the member in a depth direction from the first surface, wherein at least one of the plurality of photoelectric conversion portions other than the photoelectric conversion portion positioned closest to the first surface includes, on a boundary surface thereof with the member, unevenness having a difference in level larger than a difference in level of unevenness of the photoelectric conversion portion positioned closest to the first surface, and wherein the boundary surface having the unevenness is configured to localize or resonate light incident on the member from a side of the first surface around the boundary surface having the unevenness.Type: ApplicationFiled: September 12, 2012Publication date: April 4, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Tetsuya Fudaba, Masatsugu Itahashi, Masahiro Kobayashi, Hideo Kobayashi
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Patent number: 8409912Abstract: In one embodiment, active diffusion junctions of a solar cell are formed by diffusing dopants from dopant sources selectively deposited on the back side of a wafer. The dopant sources may be selectively deposited using a printing method, for example. Multiple dopant sources may be employed to form active diffusion regions of varying doping levels. For example, three or four active diffusion regions may be fabricated to optimize the silicon/dielectric, silicon/metal, or both interfaces of a solar cell. The front side of the wafer may be textured prior to forming the dopant sources using a texturing process that minimizes removal of wafer material. Openings to allow metal gridlines to be connected to the active diffusion junctions may be formed using a self-aligned contact opening etch process to minimize the effects of misalignments.Type: GrantFiled: September 15, 2010Date of Patent: April 2, 2013Assignee: SunPower CorporationInventors: Denis de Ceuster, Peter John Cousins, Richard M. Swanson, Jane E. Manning
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Patent number: 8409904Abstract: Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.Type: GrantFiled: June 21, 2011Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
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Publication number: 20130068292Abstract: Described herein is a method for obtaining a three-dimensional nanostructure array on an aluminum substrate. The method includes anodizing the aluminum substrate; forming an oxide layer on the aluminum substrate; texturizing the aluminum substrate; etching the oxide layer from the aluminum substrate to expose the texturized aluminum substrate; and forming a three-dimensional aluminum nanostructure array on the aluminum substrate. The three-dimensional nanostructure array, coated with a light absorber, is utilized in a thin film solar cell or photovoltaic cell.Type: ApplicationFiled: September 10, 2012Publication date: March 21, 2013Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Zhiyong Fan, Rui Yu
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Publication number: 20130065350Abstract: A design and manufacturing method for an interdigitated backside contact photovoltaic (PV) solar cell less than 100 ?m thick are disclosed. A porous silicon layer is formed on a wafer substrate. Portions of the PV cell are then formed using diffusion, epitaxy and autodoping from the substrate. All backside processing of the solar cell (junctions, passivation layer, metal contacts to the N+ and P+ regions) is performed while the thin epitaxial layer is attached to the porous layer and substrate. After backside processing, the wafer is clamped and exfoliated. The front of the PV cell is completed from the region of the wafer near the exfoliation fracture layer, with subsequent removal of the porous layer, texturing, passivation and deposition of an antireflective coating. During manufacturing, the cell is always supported by either the bulk wafer or a wafer chuck, with no processing of bare thin PV cells.Type: ApplicationFiled: October 30, 2012Publication date: March 14, 2013Applicant: Crystal Solar, IncorporatedInventor: Crystal Solar, Incorporated
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Patent number: 8389309Abstract: There is provided a method for manufacturing a light-emitting element comprising a semiconductor layered structure of Group III-V compound semiconductor layers; the manufacturing method including a step of forming a projection/depression structure on a light extraction surface of the semiconductor layered structure using as an etchant an aqueous solution containing hydrobromic acid.Type: GrantFiled: February 23, 2012Date of Patent: March 5, 2013Assignee: Stanley Electric Co., Ltd.Inventor: Seiichiro Kobayashi
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Publication number: 20130052771Abstract: The solar cell manufacturing apparatus includes: a load lock chamber configured to allow loading and unloading of a substrate by switching between atmospheric ambient and vacuum ambient; a processing chamber where the substrate for a solar cell is to be doped with impurity ions for pn junction formation in the vacuum ambient; and a conveyance chamber including a conveyance unit configured to convey the substrate between the load lock chamber and the processing chamber. The doping of impurity ions is performed by irradiation with the impurity ions from an ion gun, and the ion gun is provided with a grid plate, as its ion irradiation surface, facing the substrate conveyed to the processing chamber.Type: ApplicationFiled: June 8, 2011Publication date: February 28, 2013Applicant: ULVAC, INC.Inventor: Genji Sakata
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Publication number: 20130045561Abstract: Semiconductor photovoltaic cells have surfaces that are textured for processing and photovoltaic reasons. The absorbing regions may have grooves that reduce loss of solar energy that would otherwise be lost by reflection. One form of texturing has grooves and ridges. The cell also includes metallizations for collecting generated electrical carriers and conducting them away, which may be channels. The topography is considered during production, using a process that takes advantage of the topography to govern what locations will receive a specific processing, and which locations will not. Liquids are treated directly into zones. They migrate throughout a zone and act upon the locations contacted. They do not migrate to other zones, due to impediments to flow, such as edges, walls and ridges. Liquid may also be deposited and migrate within a zone, to block or mask a subsequent activity, such as etching.Type: ApplicationFiled: August 27, 2012Publication date: February 21, 2013Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Emanuel M. Sachs, James F. Bredt
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Publication number: 20130025678Abstract: A solar cell and a method for manufacturing the same are disclosed. The solar cell may include a substrate, an emitter layer positioned at a first surface of the substrate, a first anti-reflection layer that is positioned on a surface of the emitter layer and may include a plurality of first contact lines exposing a portion of the emitter layer, a first electrode that is electrically connected to the emitter layer exposed through the plurality of first contact lines and may include a plating layer directly contacting the emitter layer, and a second electrode positioned on a second surface of the substrate.Type: ApplicationFiled: October 28, 2010Publication date: January 31, 2013Applicant: LG ELECTRONICS INC.Inventors: Goohwan Shim, Changseo Park, Philwon Yoon, Yoonsil Jin, Jinsung Kim, Youngho Choe, Jaewon Chang
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Publication number: 20130025669Abstract: The invention provides a photovoltaic cell substrate that is a semiconductor substrate comprising an n-type diffusion layer, an n+-type diffusion layer having a higher n-type impurity concentration than the n-type diffusion layer, and a concave portion at a surface of the n+-type diffusion layer.Type: ApplicationFiled: July 24, 2012Publication date: January 31, 2013Inventors: Tetsuya SATO, Masato Yoshida, Takeshi Nojiri, Youichi Machii, Mitsunori Iwamuro, Akihiro Orita