Abstract: An organic light emitting diode display includes a substrate main body, a semiconductor layer and a first capacitor electrode on the substrate main body, bottom surfaces of the semiconductor layer and first capacitor electrode being substantially coplanar, and each of the semiconductor layer and first capacitor electrode including an impurity-doped polysilicon layer, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, the second capacitor electrode including a convex electrode portion and a concave electrode portion, the concave electrode portion being thinner than each of the convex electrode portion and the gate electrode.

Abstract: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.

Abstract: Provided is a display device including first and second gate interconnections; a first pixel circuit disposed at one side of the first gate interconnection, the first pixel circuit including a first transistor, a gate electrode of the first transistor electrically connected to the first gate interconnection, a source electrode of the first transistor formed in a source layer, the source electrode including a first source electrode facing portion overlapping with the gate electrode; and a second pixel circuit disposed at the other side of the second gate interconnection, the second pixel circuit including a second transistor, a gate electrode of the second transistor electrically connected to the second gate interconnection, a source electrode of the second transistor formed in the source layer, the source electrode including a second source electrode facing portion overlapping with the gate electrode and stretched along the first source electrode facing portion.

Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.

Abstract: A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

Abstract: Disclosed is a nitride-based semiconductor light emitting device with excellent light extraction efficiency. A light emitting device 11 includes a support base 13 and a semiconductor laminate 15. The semiconductor laminate 15 includes an n-type GaN-based semiconductor region 17, an active layer 19, and a p-type GaN-based semiconductor region 21. The n-type GaN-based semiconductor region 17, the active layer 19, and the p-type GaN-based semiconductor region 21 are mounted on a principal surface 13a, and are arranged in the direction of a predetermined axis Ax orthogonal to the principal surface 13a. A rear surface 13b of the support base 13 is inclined with respect to a plane orthogonal to a reference axis extending in the c-axis direction of a hexagonal gallium nitride semiconductor of the support base 13. A vector VC represents the c-axis direction. A surface morphology M of the rear surface 13b has a plurality of protrusions 23 protruding in the direction of a <000-1>-axis.

Abstract: An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

Abstract: A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high.

Abstract: A III-V group compound semiconductor light-emitting diode, containing a substrate 1 having plural crystal planes, and a grown layer formed on the substrate by epitaxial growth, the grown layer at least including a barrier layer 2 and 3 and an active layer 8, wherein at least the active layer of the grown layer has plural crystal planes each having a different bandgap energy in the in-plane direction, and an Ohmic electrode 4 for current injection is formed on a crystal plane (3) having a higher bandgap energy among the plural crystal planes.

Abstract: A light emitting structure comprising a hot electron source and a layer of ptoelectronic material disposed thereon and optionally p-type material disposed on the optoelectronic material. For example, a light emitting structure that comprises, in order, a polycrystalline silicon layer, a silicon dioxide layer, a zinc oxide layer and an indium tin oxide (ITO) layer. When a sufficient voltage is applied across the layers, light is generated.

Abstract: The present invention is a liquid crystal panel substrate that comprises: pixel units each having a pixel electrode, to be used as a reflective electrode and arranged in a matrix pattern on a substrate, and a switching element controlling a voltage applied to the pixel electrode; wherein between the pixel electrode and a conductive layer forming a terminal electrode of the switching element, a contact hole is provided for connecting the pixel electrode and the terminal electrode. A light-shielding layer, having an opening surrounding the portion in which the contact hole is formed, and having no opening in regions between a plurality of adjacent pixel electrodes, is formed between the pixel electrode and the conductive layer. Harmful effects due to light leaking through a space between the pixel electrodes can thereby be prevented.

Abstract: One or more embodiments relate to a semiconductor device, comprising: a substrate; and a radio frequency coupler including a first coupling element and a second coupling element spacedly disposed from the first coupling element, the first coupling element including at least one through-substrate via disposed in the substrate, the second coupling element including at least one through-substrate via disposed in the substrate.

Abstract: A diode (130) whose anode is connected to a conductive plate (140) formed so as to cover a TFT (120) of a pixel formation portion (110) and whose cathode is connected to a video signal line is provided. With the configuration, when potential of a video signal applied to the video signal line is lower than that of the conductive plate (140), a current is passed to the diode (130), and the potential of the conductive plate (140) becomes equal to that of the video signal line. On the other hand, when the potential of the video signal is higher than that of the conductive plate (140), no current flows, so that the potential of the diode (130) is held as it is. As a result, the potential of the conductive plate (140) is clamped to the lowest potential among potentials of video signals. Consequently, a leak current which flows from the pixel electrode Ep of the pixel formation portion (110) to the video signal line when the TFT (120) is in the off state is suppressed.

Abstract: A ZnO-containing semiconductor layer contains Se or S added to ZnO and has an emission peak wavelength of ultraviolet light and an emission peak wavelength of visual light. By combining the ZnO-containing semiconductor layer with phosphor or semiconductor which is excited by the emitted ultraviolet light and emits visual light, visual light at various wavelengths can be emitted.

Abstract: The present invention provides a motherboard having panel substrates efficiently arranged thereon and a reduced wasted substrate region, a method for producing the motherboard, and a device substrate comprising the panel substrates formed on the motherboard. The motherboard of the present invention comprises a plurality of panel substrates, wherein the motherboard has a silicon thin film formed on a principal surface thereof, each of the panel substrates has a transistor forming region and a marginal region, the transistor forming region is formed by polycrystallizing the silicon thin film, the marginal region is provided on an outer edge of each of the panel substrates, and at least one of the panel substrates has the marginal region including a region with a silicon thin film which has a crystal profile different from a crystal profile of a silicon thin film in the transistor forming region.

Abstract: A method for fabricating organic electroluminescent devices is disclosed. The method comprises providing a substrate divided into first and second regions, forming an amorphous silicon layer on the substrate, forming a protection film on the amorphous silicon layer within the second region, performing an excimer laser annealing process on the amorphous silicon layer for converting it to a polysilicon layer, removing the protection film, patterning the polysilicon layer, thus a first patterned polysilicon layer in the first region and a second patterned polysilicon layer in the second region are formed. A resultant organic electroluminescent device is obtained. Specifically, the grain size of the first patterned polysilicon layer is large than that of the second patterned polysilicon layer.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 ?, e.g., between 100 and 750 ?. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: In a display device of the present invention which forms thin film transistors on a substrate, the thin film transistor comprises: a silicon nitride film which is formed on the substrate in a state that the silicon nitride film covers a gate electrode; a silicon oxide film which is selectively formed on the silicon nitride film; a semiconductor layer which is formed at least on an upper surface of the silicon oxide film and includes a pseudo single crystal layer or a polycrystalline layer; and a drain electrode and a source electrode which are formed on an upper surface of the semiconductor layer by way of a contact layer, wherein either one of the pseudo single crystal layer and the poly-crystalline layer is formed by crystallizing the amorphous silicon layer, and a peripheral-side wall surface of the pseudo single crystal layer or the polycrystalline layer is contiguously constituted with a peripheral-side wall surface of the silicon oxide film below the pseudo single crystal layer or the polycrystalline la

Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: A thin film transistor (TFT), a method of fabricating the same, an organic light emitting diode (OLED) display device having the same, and a method of fabricating the same. The TFT includes a substrate; a buffer layer disposed on the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and corresponding to the semiconductor layer; and source and drain electrodes insulated from the gate electrode, and electrically connected to the semiconductor layer. Here, the semiconductor layer includes a plurality of seed regions separated from each other by a distance of 50 ?m or more.

Abstract: A Group III nitride semiconductor device of the present invention is obtained by laminating at least a buffer layer (12) made of a Group III nitride compound on a substrate (11), wherein the buffer layer (12) is made of AlN, and a lattice constant of a-axis of the buffer layer (12) is smaller than a lattice constant of a-axis of AlN in a bulk state.

Abstract: The object of this invention is to provide a high-output type nitride light emitting device. The nitride light emitting device comprises an n-type nitride semiconductor layer or layers, a p-type nitride semiconductor layer or layers and an active layer therebetween, wherein a gallium-containing nitride substrate is obtained from a gallium-containing nitride bulk single crystal, provided with an epitaxial growth face with dislocation density of 105/cm2 or less, and A-plane or M-plane which is parallel to C-axis of hexagonal structure for an epitaxial face, wherein the n-type semiconductor layer or layers are formed directly on the A-plane or M-plane. In case that the active layer comprises a nitride semiconductor containing In, an end face film of single crystal AlxGa1-xN (0?x?1) can be formed at a low temperature not causing damage to the active layer.

Abstract: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.

Abstract: In a laser chip 1 using a nitride semiconductor having a hexagonal crystal structure, the ?c plane is used as a first resonator facet A, which is the side of the laser chip 1 through which light is emitted. On the first resonator facet A, that is, on the ?c plane, a facet protection film 14 is formed. This ensures firm joint between the first resonator facet A and the facet protection film 14 and alleviates deterioration of the first resonator facet A.

Abstract: A semiconductor light emitting device (10) is provided with a base substrate (12) and three LED chips (14A, 14B, and 14C) disposed on the base substrate (12). Each LED chip (14A, 14B, and 14C) includes a semiconductor multilayer structure (20) and has a rhombus shape with interior angles of approximately 60° and approximately 120° in plan view. Each semiconductor multilayer structure (20) has an HCP single crystal structure and includes a light emission layer (24). The LED chips (14A, 14B, and 14C) are arranged on the base substrate (12) so as to face one another at a vertex forming the larger interior angle in plan view. With this arrangement, the LED chips (14A, 14B, and 14C) as a whole form a substantially regular hexagonal shape.

Abstract: A high frequency diode comprising: a P type region, an N type region, and an I layer as a high resistivity layer interposed between the P type region and the N type region, wherein the I layer is made of a silicon wafer that has a carbon concentration of 5×1015 to 5×1017 atoms/cm3, interstitial oxygen concentration of 6.5×1017 to 13.5×1017 atoms/cm3, and a resistivity of 100 ?cm or more.

Abstract: There are provided a semiconductor light emitting element which allows an improvement in light extraction efficiency without increasing the number of fabrication steps, and a wafer. In a semiconductor light emitting element 1 formed by laminating a compound semiconductor layer 3 on a single crystal substrate, and dividing the single crystal substrate into pieces, the side faces 21 to 24 of each of substrate pieces 2 as the divided single crystal substrate are formed such that the side face 21 used as the reference of the substrate piece 2 forms an angle of 15° with respect to the (1-100) plane, and that the side faces 21 to 24 are formed of planes different from cleaved planes of a crystalline structure in the single crystal substrate.

Abstract: A light emitting device and a light emitting device package including the same are provided. The light emitting device may include a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a first electrode on the light emitting structure, the first electrode including a pattern, and a pad electrode on the first electrode.

Abstract: A compound semiconductor light emitting element is provided with a substrate which is provided on a side of one electrode; a plurality of columnar crystal structures of nanometer scale extending in a vertical direction on the substrate; and another electrode which interconnects top portions of the plurality of columnar crystal structures. On the substrate are provided a first region, and a second region having a step between the first region and the second region and having a substrate thickness greater than that in the first region; a porous first mask layer is formed on the surface of the first region on the substrate; and the plurality of columnar crystal structures are formed by sequentially layering an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer, in the first and second regions on the substrate.

Abstract: An active device array mother substrate including a substrate, pixel arrays, and a polymer-stabilized alignment curing circuit is provided. The substrate has panel regions, a circuit region, a first cutting line, and a second cutting line. The first cutting line is disposed on the circuit region between an edge of the substrate and the second cutting line. The active devices of the pixel arrays have a semiconductor layer. The polymer-stabilized alignment curing circuit disposed on the circuit region includes curing pads disposed between the edge of the substrate and the first cutting line and curing lines having an upper conductive layer connected to the corresponding curing pads and the corresponding pixel array. The upper conductive layer is in the same layer as the source/drain conductor. Therefore, the curing lines are capable of preventing problems such as peeling, so as to keep the polymer-stabilized alignment curing circuit operating normally.

Abstract: An optoelectronic component contains an epitaxial layer sequence (6) based on a nitride compound semiconductor having an active layer (4) and, wherein the epitaxial growth substrate (1) comprises Al1-xGaxN, where 0<x<0.95. In the case of a method for producing an optoelectronic component an epitaxial growth substrate (1) of Al1-x(InyGa1-y)xN or In1-xGaxN, where 0<x<0.99 and 0?y?1 is provided and an epitaxial layer sequence (6) which is based on a nitride compound semiconductor and contains an active layer (4) is grown thereon.

Abstract: An organic light emitting diode (OLED) display device having a pixel area and a pad area. The pad area includes a silicon layer pattern arranged on the substrate, an insulating layer arranged on the silicon layer pattern, an interconnection layer arranged on the insulating layer, and a protective layer surrounding an edge of the interconnection layer and having an opening exposing the interconnection layer. Since a surface area of the interconnection layer is increased due to a roughness of the underlying polycrystalline silicon layer pattern in the pad area, resulting in increased contact area and reduced contact resistance between parts configured to operate a flat panel display device and the interconnection layer is increased.

Abstract: A high frequency diode comprising: a P type region, an N type region, and an I layer as a high resistivity layer interposed between the P type region and the N type region, wherein the I layer is made of a silicon wafer that has a carbon concentration of 5×1015 to 5×1017 atoms/cm3, interstitial oxygen concentration of 6.5×1017 to 13.5×1017 atoms/cm3, and a resistivity of 100 ?cm or more.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

Abstract: A display device which has thin film transistors, wherein a semiconductor layer includes a first layer, second layers and third layers, the first layer has a channel region, the second layers are an impurity layer, the third layers are a low-concentration impurity layer, the second layers have connection portions connected with an electrodes, the third layers are formed to annularly surround the second layers, a channel-region-side edge portion out of edge portions of the third layer is in contact with the first layer, the edge portions of the third layer but the channel-region-side edge portion are in contact with an interlayer insulation film, the second layers have a first region where the second layer overlaps with a gate electrode and a second region where the second layer does not overlap with the gate electrode, and the connection portion is in the second region.

Abstract: Provided is a method for manufacturing a surface-emitting laser capable of forming a photonic crystal structure inside a semiconductor highly accurately and easily without direct bonding. It is a method by laminating on a substrate a plurality of semiconductor layers including an active layer and a semiconductor layer having a photonic crystal structure formed therein, the method including the steps of forming a second semiconductor layer on a first semiconductor layer to form the photonic crystal structure, forming a plurality of microholes in the second semiconductor layer, forming a low refractive index portion in a part of the first semiconductor layer via the plurality of microholes thereby to provide the first semiconductor layer with the photonic crystal structure having a one-dimensional or two-dimensional refractive index distribution in a direction parallel to the substrate, and forming a third semiconductor layer by crystal regrowth from a surface of the second semiconductor layer.

Abstract: A light-emitting semiconductor component comprising a substrate which has a first interface between a first and a second silicon layer, whose lattice structures which are considered as ideal are rotated relative to each other through a twist angle about a first axis perpendicular to the substrate surface and are tilted through a tilt angle about a second axis parallel to the substrate surface, in such a way that a dislocation network is present in the region of the interface, wherein the twist angle and the tilt angle are so selected that an electroluminescence spectrum of the semiconductor component has an absolute maximum of the emitted light intensity at either 1.3 micrometers light wavelength or 1.55 micrometers light wavelength.

Abstract: A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al1-yGayAs1-xPx with 0?x?1 and 0?y?1. A number of the semiconductor layers respectively comprising a phosphorus component x which is greater than in a neighboring semiconductor layer lying thereunder in the direction of growth of the semiconductor layer sequence. Two semiconductor layers directly preceding the uppermost semiconductor layer of the semiconductor layer sequence have a smaller lattice constant than the uppermost layer.

Abstract: The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer of thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase ; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film.

Abstract: A semiconductor light emitting device includes a substrate 11 including a group III-V nitride semiconductor; a first-conductivity-type layer 12 formed on the substrate 11, the first-conductivity-type layer including a plurality of group III-V nitride semiconductor layers of first conductivity type; an active layer 13 formed on the first semiconductor layer 12; and a second-conductivity-type layer 14 formed on the active layer 13, the second-conductivity-type layer including a group III-V nitride semiconductor layer of second conductivity type. The first-conductivity-type layer 12 includes an intermediate layer 23 made of Ga1-xInxN (0<x<1).

Abstract: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced.

Abstract: Disclosed is a method of manufacturing a semiconductor device including: forming a photothermal conversion layer in a second area where a semiconductor layer is formed other than a first area where line is formed; and heating the semiconductor layer with the photothermal conversion layer by irradiating light on the first area and the second area.

Abstract: An integrated circuit device, which can be a light emission device such as a light emitting diode (LED), comprises a substrate, a plurality of device layers formed on a first surface of the substrate, including a first device layer and a second device layer, a first electrode formed on the first device layer, and a second electrode formed on a second surface of the substrate which is parallel and opposite to the first surface of the substrate. A plurality of substantially identical such devices can formed on a semiconductor wafer, where one or both of the first and second electrodes are shared by the plurality of devices prior to dicing the wafer. All of the devices can be tested simultaneously on the wafer, prior to dicing. Formation of the electrodes on opposite sides of the substrate allow the device to be directly connected to a mounting substrate, without any wire bonding.

Abstract: The semiconductor light-emitting element includes a group III nitride semiconductor multilayer structure having an active layer containing In as well as a p-type layer and an n-type layer stacked to hold the active layer therebetween. The group III nitride semiconductor multilayer structure is made of a group III nitride semiconductor having a major surface defined by a nonpolar plane whose offset angle in a c-axis direction is negative. A remarkable effect is attained when the emission wavelength of the active layer is not less than 450 nm. In the group III nitride semiconductor constituting the group III nitride semiconductor multilayer structure, the offset angle ? in the c-axis direction preferably satisfies ?1°<?<0°.

Abstract: A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first

Abstract: An integrated circuit, which is configured such that a MOS transistor and a bipolar transistor are integrated at the same time, is formed on an insulating substrate which includes a display device. An electronic device or a display includes a plurality of semiconductor devices which are formed by using a semiconductor thin film and are formed in the semiconductor thin film that is provided on an insulating substrate and is crystallized in a predetermined direction. The plurality of semiconductor devices include a MOS transistor and at least either one of a lateral bipolar thin-film transistor and a MOS-bipolar hybrid thin film transistor.

Abstract: In an auxiliary capacitance electrode of each pixel region, a side end on one side in a direction in which a drain electrode crosses an end of a gate electrode so as to enter from the outside of the gate electrode to the inside thereof is disposed inside of an auxiliary capacitance line, and a side end on the other side in a direction in which the drain electrode crosses the end of the gate electrode so as to go out from the inside of the gate electrode to the outside thereof is disposed outside of the auxiliary capacitance line.

Abstract: A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 ?m. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.