With Heterojunction (epo) Patents (Class 257/E33.021)
  • Patent number: 8957450
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a film covering a side face of the first metal pillar and a side face of the second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The film has a solder wettability poorer than a solder wettability of the first metal pillar and a solder wettability of the second metal pillar. The resin layer covers at least part of the film.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Sugizaki
  • Publication number: 20120273815
    Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.
    Type: Application
    Filed: October 14, 2011
    Publication date: November 1, 2012
    Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventors: YU-LI TSAI, Chih-Hung Wu, Jei-Li Ho, Chao-Huei Huang, Min-De Yang
  • Patent number: 8148731
    Abstract: Semiconductor films and structures, such as films and structures utilizing zinc oxide or other metal oxides, and processes for forming such films and structures, are provided for use in metal oxide semiconductor light emitting devices and other metal oxide semiconductor devices, such as ZnO based semiconductor devices.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: April 3, 2012
    Assignee: Moxtronics, Inc.
    Inventors: Yungryel Ryu, Tae-seok Lee, Henry W. White
  • Publication number: 20120074380
    Abstract: A white light emitting diode (LED) and method for forming the white LED are provided, wherein a semiconductor material is formed directly with a epitaxial method on a GaN epitaxial structure. The semiconductor material is a doped II-VI semiconductor compound with a broad FWHM (Full Width at Half Maximum) compared to conventional phosphor, can provide a white LED with better color rendering.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 29, 2012
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Jyh-Shyang Wang, Wei-Jie Chen, Wei-Hsuan Lo, Ren-Hao Chen
  • Publication number: 20110175054
    Abstract: A device using a layer containing emitting semiconductor nanocrystals wherein each emitting nanocrystal includes a core structure wherein the cores have an aspect ratio less than 2:1 and a diameter greater than 10 nanometers and a protective shell surrounding the core
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Inventors: XIAOFAN REN, KEITH B. KAHEN
  • Publication number: 20110127932
    Abstract: A blue light emitting semiconductor nanocrystal having an quantum yield of greater than 20% can be incorporated in a light emitting device.
    Type: Application
    Filed: August 9, 2007
    Publication date: June 2, 2011
    Applicant: Massachusetts Institute of Technology
    Inventors: Jonathan E. Halpert, Polin O. Anikeeva, Moungi G. Bawendi, Vladmir Bulovic
  • Patent number: 7859106
    Abstract: A core substrate using paste bumps, the core substrate including a first paste bump board having a plurality of first paste bumps joined to a surface thereof; a second paste bump board having a plurality of second paste bumps facing the first paste bumps joined thereto; and an insulation element placed between the first paste bump board and the second paste bump board. In the core substrate, the first paste bumps and the second paste bumps are electrically interconnected.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: December 28, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoong Oh, Chang-Sup Ryu, Dong-Jin Park, Jee-Soo Mok, Byung-Bae Seo
  • Patent number: 7772586
    Abstract: The present invention aims at providing a structure in which a high p-type carrier concentration of 1×1017 cm?3 or more is obtained in a material in which, although it shows normally p-type conductivity, a carrier concentration smaller than 1×1017 cm?3 is only obtained. Also, the present invention aims at providing highly reliable semiconductor element and device each of which has excellent characteristics such as light emitting characteristics and a long lifetime. Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2 ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10 ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm?3 or more is obtained when a single layer is inserted at suitable intervals.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: August 10, 2010
    Assignees: Sophia School Corporation, Sony Corporation, Hitachi, Ltd.
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Hitoshi Nakamura
  • Publication number: 20100180950
    Abstract: A method and corresponding system for providing a uniform nanowire array including uniform nanowires composed of at least three elements is presented. An embodiment of the method includes growing an array of two-element nanowires, and thereafter uniformly doping or alloying each two-element nanowire, with respect to each other two-element nanowire, with at least one doping or alloying element through a wet chemical synthesis with a precursor solution, to produce the uniform array of nanowires composed of at least three elements. The two-element nanowire can include Zn and O, and the at least one doping or alloying element can be Mg, Cd, Mn, Cu, Be, Fe, and Co. Applications of the three-element nanowire array include solar cells and light emitting diodes with improved efficiencies over existing technologies.
    Type: Application
    Filed: November 13, 2009
    Publication date: July 22, 2010
    Applicant: University of Connecticut
    Inventors: Pu-Xian Gao, Paresh Shimpi
  • Publication number: 20100163864
    Abstract: An object of the present invention is to increase the light emission efficiency of a ZnO-based optical semiconductor device. An optical semiconductor device B has a structure which includes n-type Zn1-zMgzO (barrier layer) 11/Zn1-zMgxO (active layer) 15/p-type Zn1-yMgyO (barrier layer) 17, and light is emitted from the active layer 15. Electrodes 23, 21 are respectively formed on barrier layers 11, 17. By applying a voltage between the two electrodes 23, 21, light is emitted from ZnO (active layer) 15. Here, there are a relationship of x<y and a relationship of x<z. For instance, such values as x=0.1, y=0.15 and z=0.16 can be chosen. Otherwise, such values as x=0.15, y=0.25 and z=0.24 can be choose as well. In this case, by increasing the value x of the active layer, it is possible to shift its light emission wavelength to the shorter wavelength side. In addition, as shown in the above-described results, by increasing the value x, it is possible to enhance its light emission efficiency.
    Type: Application
    Filed: May 13, 2008
    Publication date: July 1, 2010
    Inventors: Hajime Shibata, Hitoshi Tampo, Koji Matsubara, Akimasa Yamada, Keiichiro Sakurai, Shogo Ishizuka, Shigeru Niki
  • Patent number: 7525128
    Abstract: A light-emitting zinc oxide based compound semiconductor device of a double-heterostructure. The double-heterostructure includes a light-emitting layer formed of a low-resistivity Mg1?x?yCdxZnyO; 0?x<1, 0<y?1, and x+y=0.1 to 1 compound semiconductor doped with p-type and/or n-type impurity. A first clad layer is joined to one surface of the light-emitting layer and formed of an n-type zinc oxide compound semiconductor having a composition different from the light-emitting layer. A second clad layer is joined to another surface of the light-emitting layer and formed of a low-resistivity, p-type zinc oxide based semiconductor having a composition different from the light-emitting layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: April 28, 2009
    Assignee: Cermet, Inc.
    Inventors: Jeffrey E. Nause, Shanthi Ganesan
  • Patent number: 7335920
    Abstract: An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the n-type layer of material. The confinement structure is generally aligned with the contact on the top and primary emission surface of the LED and substantially prevents the emission of light from the area of the active region that is coincident with the area of the confinement structure and the top-surface contact. The LED may include a roughened emitting-side surface to further enhance light extraction.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: February 26, 2008
    Assignee: Cree, Inc.
    Inventors: Steven P. Denbaars, Shuji Nakamura, Max Batres
  • Publication number: 20070102723
    Abstract: A light-emitting zinc oxide based compound semiconductor device of a double-heterostructure. The double-heterostructure includes a light-emitting layer formed of a low-resistivity Mg1-x-yCdxZnyO; 0?x<1, 0<y?1, and x+y=0.1 to 1 compound semiconductor doped with p-type and/or n-type impurity. A first clad layer is joined to one surface of the light-emitting layer and formed of an n-type zinc oxide compound semiconductor having a composition different from the light-emitting layer. A second clad layer is joined to another surface of the light-emitting layer and formed of a low-resistivity, p-type zinc oxide based semiconductor having a composition different from the light-emitting layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 10, 2007
    Applicant: CERMET, INC.
    Inventors: Jeff Nause, Shanthi Ganesan
  • Patent number: 7145180
    Abstract: In the fabricating of a light emitting device, a light emitting layer portion 24 and a current spreading layer 7, respectively composed of a Group III-V compound semiconductor, are stacked on a single crystal substrate. The light emitting layer portion 24 is formed by a metal organic vapor-phase epitaxy process, and the current spreading layer 7, on such light emitting layer portion 24, is formed to have conductivity type of n-type by a hydride vapor-phase epitaxy process.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 5, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masayuki Shinohara, Masato Yamada