Comprising Only Group Ii-iv-vi Compound (epo) Patents (Class 257/E33.039)
  • Patent number: 8399878
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silica particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 19, 2013
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 8373210
    Abstract: A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mitsuru Shiozaki, Atsushi Iwata
  • Patent number: 8263423
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 11, 2012
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 8097885
    Abstract: Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has a composition represented by a Cu2—Zn—IV—S4 type, in which the IV is at least one of Ge and Si. The light emitting film includes the light emitting material and the compound semiconductor film laminated on a substrate in the stated order.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 17, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyuki Oike, Tatsuya Iwasaki
  • Patent number: 7892872
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: February 22, 2011
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Publication number: 20100210056
    Abstract: A method of fabricating an array substrate for a display device includes steps of forming a gate line and a gate electrode on a substrate, forming a gate insulating layer and an intrinsic amorphous silicon layer, forming an oxide semiconductor layer, increasing a conductive property of the oxide semiconductor layer, forming a metal layer, forming a first photoresist pattern and a second photoresist pattern having a thinner thickness than the first photoresist pattern, forming a data line, a source drain pattern, an oxide semiconductor pattern and an active layer, removing the second photoresist pattern and exposing the source drain pattern, wet-etching the source drain pattern using a first etchant, thereby forming source and drain electrodes, wet-etching the oxide semiconductor pattern using a second etchant, thereby forming ohmic contact layers, removing the first photoresist pattern, forming a passivation layer having a drain contact hole exposing the drain electrode on the source and drain electrodes, and
    Type: Application
    Filed: December 23, 2009
    Publication date: August 19, 2010
    Inventors: Hyun-Sik Seo, Jong-Uk Bae, Dae-Hwan Kim