Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.

Abstract: An organic semiconductor compound may include a structural unit represented by the aforementioned Chemical Formula 1 and an organic thin film and an electronic device may include the organic semiconductor compound.

Abstract: Organic polymeric multi-metallic alkoxide or aryloxide composites are used as dielectric materials in various devices with improved properties such as improved mobility. These composites comprise an organic polymer comprising metal coordination sites, and multi-metallic alkoxide or aryloxide molecules that are coordinated with the organic polymer, the multi-metallic alkoxide or aryloxide molecules being represented by: (M)n(OR)x wherein at least one M is a metal selected from Group 2 of the Periodic Table and at least one other M is a metal selected from any of Groups 3 to 12 and Rows 4 and 5 of the Periodic Table, n is an integer of at least 2, R represents the same or different alkyl or aryl groups, and x is an integer of at least 2.

Abstract: Disclosed are new semiconducting polymers. The polymers disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.

Abstract: The present invention discloses a nanoball solution coating method and applications thereof. The method comprises steps: using a scraper to coat a nanoball solution on a substrate to attach a plurality of nanoballs on the substrate; flushing or flowing through the substrate with a heated volatile solution to suspend the nanoballs unattached to the substrate in the volatile solution; and using the scraper to scrape off the volatile solution carrying the suspended nanoballs, whereby is simplified the process to coat nanoballs. The method can be used to fabricate nanoporous films, organic vertical transistors, and large-area elements and favors mass production.

Abstract: An organic functional device (1; 40; 50) comprising a substrate (2) having a first electrode layer (3) and at least a first substrate shunt structure (6), at least a first organic functional layer (7) provided on top of the first electrode layer (3), a second, transparent electrode layer (8) arranged on top of the first organic functional layer (7). The organic functional device further comprises a plurality of mutually spaced apart second electrode shunting structures (9a-d) which are each in electrical contact with the second electrode layer (8) and with the first substrate shunt structure (6).

Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: According to example embodiments, a semiconductor device includes a first electrode, a second electrode apart from the first electrode, and an active layer between the first and second electrodes. The active layer includes first and second layers, the first layer contacts the first and second electrodes, and the second layer is separated from at least one of the first and second electrodes.

Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: The present invention has an object of providing a light emitting device including an OLED formed on a plastic substrate, which can prevent the degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light emitting layer in the OLED (hereinafter, referred to as barrier films) and a film having a smaller stress than that of the barrier films (hereinafter, referred to as a stress relaxing film), the film being interposed between the barrier films, are provided. Owing to a laminate structure of a plurality of barrier films, even if a crack occurs in one of the barrier films, the other barrier film(s) can effectively prevent moisture or oxygen from penetrating into the organic light emitting layer. Moreover, the stress relaxing film, which has a smaller stress than that of the barrier films, is interposed between the barrier films, thereby making it possible to reduce a stress of the entire sealing film.

Abstract: The invention relates to organic semiconducting materials, methods for their preparation and organic electronic devices incorporating the said organic semiconducting materials. The organic semiconductors contain a compound of formula (I) Ar1=(Qu)m=Ar2??(I) where Qu is independently a substituted or unsubstituted, substantially planar 5 to 8 membered conjugated ring, and Ar1 and Ar2 each independently is a substituted or unsubstituted, substantially planar conjugated aromatic structure having from 5 to 50 carbon atoms. The compounds of formula may generally form an H-shaped molecular structure. The said organic semiconducting materials could be used as the active layers for organic electronic devices, e.g. thin film transistors, photovoltaic cells, photo detectors, light emitting diodes, memory cells, sensors etc.

Abstract: A high-efficiency, white organic electroluminescent device has such a structure that its emission layer is obtained by laminating sub-emission layers of red, green, and blue, respectively. The green sub-emission layer contacting a hole transport layer has a delayed fluorescent material, and the red sub-emission layer has a phosphorescent light emitting material.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: The present invention is drawn to a layered organic device, and a method of forming the same. The method includes steps of applying a first solvent-containing organic layer to a substrate and removing solvent from the first solvent-containing organic layer to form a first solidified organic layer. Additional steps include applying a second solvent-containing organic layer to the first solidified organic layer and removing solvent from the second solvent-containing organic layer to form a second solidified organic layer. The first solidified organic layer can be crosslinked, which suppresses negative impact to components in the first solidified organic layer when the solvent of the second solvent-containing organic layer is deposited on the first solidified organic layer.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte pattern is also disclosed, the gel electrolyte pattern comprising either a mixture of a gelling agent and an electrolyte precursor or the products of a chemical reaction between a gelling agent and an electrolyte precursor.

Abstract: An organic thin film transistor (OTFT) array panel for a display device includes a gate line and a pixel electrode formed on a substrate, the gate line and pixel electrode each having a first conductive layer including a transparent conductive oxide and a second conductive layer including a metal, a data line crossing the gate line and including a source electrode, a drain electrode facing the source electrode and connected with the pixel electrode, and an organic semiconductor in contact with the source electrode and the drain electrode.

Abstract: The present invention is an electronic device and a process for making the electronic device in which the semiconductor component comprises at least one carbon nanotube functionalized with a fluorinated olefin. Functionalization with the fluorinated olefin renders the carbon nanotube semiconducting.

Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

Abstract: A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; forming a patterned layer of insulting material defining a well surrounding the channel region; depositing a protective layer in the well; subjecting exposed portions of the patterned layer of insulating material to a de-wetting treatment to lower the wettability of the exposed portions; removing the protective layer; and depositing organic semiconductive material from solution into the well.

Abstract: Provided are a nonvolatile memory device and methods of fabricating and operating the same. The memory device may include a substrate, at least a first and a second electrode on the substrate to be spaced a distance from each other, a conductive nanotube between the first and second electrodes and selectively coming into contact with the first electrode or the second electrode due to an electrostatic force and a support supporting the conductive nanotube. The memory device may be an erasable nonvolatile memory device which may retain information even when no power is supplied and may ensure relatively high operating speed and relatively high integration density. Because the memory device writes and erases information in units of bits, the memory device may be applied to a large number of fields.

Abstract: This invention is directed toward a bioelectronic cell gated nanodevice. The bioelectronic cell gated nanodevice comprises a plurality of bioelectric cells deposited on a fiber of a nanodevice. The bioelectronic cells of the nanodevice act as a gate, allowing current to be transmitted when the bioelectronic cells are exposed to an actuating chemical. The present invention also provides methods for constructing such a device.

Abstract: A pixel architecture for compensating for distortions in a flexible substrate of a flexible display, including: a first layer including a thin film transistor (TFT) on a flexible substrate; a second layer disposed above said first layer including a pixel electrode coupled to said TFT for receiving a signal from said TFT; and a third layer including a colour filter for filtering light displayed by said pixel, wherein said third layer is aligned to said second layer such that said colour filter is substantially aligned to said pixel electrode, said alignment compensating for distortions in said first layer caused by distortions in said flexible substrate.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer.

Abstract: This invention provides a circuit structure with a double-gate organic thin film transistor device and application thereof. A protection layer covered on an organic thin film transistor structure having a bottom gate is used as another gate insulating layer. A metal layer is formed on this gate insulating layer to serve as another gate. A double-gate structure is hence accomplished. The double-gate structure can be used in a circuit. By the double-gate structure the threshold voltage of the organic thin film transistor can be adjusted, and advantageously changing the characteristic of the organic thin film transistor to improve the accuracy of signal transmission.

Abstract: Methods of producing electrochemical transistor devices are provided, wherein a solidified electrolyte is arranged in direct contact with at least a portion of an organic material having the ability to electrochemically altering its electrical conductivity through change of redox state thereof, such that a current between a source contact and a drain contact of the transistor is controllable by a voltage applied to a gate electrode. A electrochemical transistor device is also provided, wherein an ion isolative material is provided between a solidified electrolyte and an organic material having the ability to electrochemically altering its redox state, such that a transistor channel of said transistor is defined thereby.

Abstract: A transistor capable of modulating, at low voltages, a large current flowing between an emitter electrode and a collector electrode. A process of producing the transistor, a light-emitting device comprising the transistor, and a display comprising the transistor. The transistor comprises an emitter electrode and a collector electrode. Between the emitter electrode and the collector electrode are situated a semiconductor layer and a sheet base electrode. It is preferred that the semiconductor layer be situated between the emitter electrode and the base electrode and also between the collector electrode and the base electrode to constitute a second semiconductor layer and a first semiconductor layer, respectively. It is also preferred that the thickness of the base electrode be 80 nm or less. Furthermore, a dark current suppressor layer is situated at least between the emitter electrode and the base electrode, or between the collector electrode and the base electrode.

Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.

Abstract: Multilayer anode structures (104) for electronic devices (100) such as polymer light-emitting diodes are described. The multilayer anodes include a high conductivity organic layer (114) adjacent to the photoactive layer (102) and a low conductivity organic layer (112) between the high conductivity organic layer and the anode's electrical connection layer (110). This anode structure provides polymer light emitting diodes which exhibit high brightness, high efficiency and long operating lifetime. The multilayer anode structure of this invention provides sufficiently high resistivity to avoid cross-talk in passively addressed pixellated polymer emissive displays; the multilayer anode structure of this invention simultaneously provides long lifetime for pixellated polymer emissive displays.

Abstract: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test.

Abstract: A method is provided for growth of carbon nanotube (CNT) synthesis at a low temperature. The method includes preparing a catalyst by placing the catalyst between two metal layers of high chemical potential on a substrate, depositing such placed catalyst on a surface of a wafer, and reactivating the catalyst in a high vacuum at a room temperature in a catalyst preparation chamber to prevent a deactivation of the catalyst. The method also includes growing carbon nanotubes on the substrate in the high vacuum in a CNT growth chamber after preparing the catalyst.

Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

Abstract: Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an electrode formed on the molecular active layer. The organic dielectric thin film may be immobilized on the electrode or a Si layer by a self-assembled method. The organic dielectric thin film may include first and second molecular layers bound together through hydrogen bonds. An organic compound may be self-assembled over the substrate to form the organic dielectric thin film. The organic compound may include an M?-R-T structure, where M?, R and T represent a thiol or silane derivative, a saturated or unsaturated C1 to C20 hydrocarbon group which is substituted or unsubstituted with fluorine (F), and an amino(—NH2) or carboxyl (—COOH) group, respectively.

Abstract: A method for forming an organic electronic device, which method comprises the steps of: a) forming a negative image of a desired pattern on a substrate or device layer with a lift-off ink; b) coating a first device layer to be patterned on top of the negative image; c) coating one or more further device layers to be patterned on top of the first device layer to be patterned; and d) removing the lift-off ink and unwanted portions of the device layers above it, thereby leaving the desired pattern of device layers. The method allows the formation of a device structure wherein the device layers to be patterned are self-aligned. The method enables a multiplicity of layers to be patterned in a single set of printing and lift-off steps using one pattern which ensures the excellent vertical alignment of edges, which would be difficult to achieve by direct printing. Horizontal alignment can also be achieved. The size of the device features can be reduced below the actual printing resolution.

Abstract: A method provides a simple yet reliable technique to assemble one-dimensional nanostructures selectively in a desired pattern for device applications. The method comprises forming a plurality of spaced apart conductive elements (12, 20) in a sequential pattern (26) on a substrate (17) and immersing the plurality of spaced apart conductive elements (12, 20) in a solution (23) comprising a plurality of one-dimensional nanostructures (22). A voltage is applied to one of the plurality of spaced apart conductive elements (12, 20) formed in the sequential pattern (26), thereby causing portions of the plurality of one-dimensional nanostructures (22) to migrate between adjacent conductive elements (12, 20) in sequence beginning with the one of the plurality of spaced apart conductive elements (12, 20) to which the voltage is applied.