Assembling Formed Circuit To Base Patents (Class 29/831)
  • Patent number: 10413650
    Abstract: A molded interconnect device can carry a Hall sensor for transducing a position of a rotor of the implantable blood pump. The molded interconnect device includes one or more integrated electronic circuit traces configured to electrically connect the hall sensor with a printed circuit board of the implantable blood pump, and the molded interconnect device is configured to be mounted to the printed circuit board.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: September 17, 2019
    Assignee: TC1 LLC
    Inventors: Samuel Schimpf, Mark McChrystal, Joseph C. Stark, III, Andre Siebenhaar
  • Patent number: 10383236
    Abstract: A manufacturing method for circuit board on copper ceramic substrate comprises stamping a copper sheet into a copper circuit board in a shape matching a ceramic substrate, fitting the copper circuit board to the ceramic substrate and sintering the copper circuit board and the ceramic substrate together by direct bonding copper.
    Type: Grant
    Filed: July 31, 2016
    Date of Patent: August 13, 2019
    Assignee: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITED
    Inventor: Fei Ren
  • Patent number: 10207103
    Abstract: Implementations described and claimed herein provide thin film devices and methods of manufacturing and implanting the same. In one implementation, a shaped insulator is formed having an inner surface, an outer surface, and a profile shaped according to a selected dielectric use. A layer of conductive traces is fabricated on the inner surface of the shaped insulator using biocompatible metallization. An insulating layer is applied over the layer of conductive traces. An electrode array and a connection array are fabricated on the outer surface of the shaped insulator and/or the insulating layer, and the electrode array and the connection array are in electrical communication with the layer of conductive traces to form a flexible circuit. The implantable thin film device is formed from the flexible circuit according to the selected dialectic use.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 19, 2019
    Assignee: PACESETTER, INC.
    Inventors: John R. Gonzalez, Jeffrey Urbanski, Tommy Cushing
  • Patent number: 10101367
    Abstract: A microelectronic test device comprising an organic substrate, a probe holder, and an interposer disposed between the organic substrate and the probe holder, wherein the interposer has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the organic substrate. The interposer may effectively decouple the organic substrate from probes in the probe holder, which may substantially reduce or eliminate probe misalignment due to the coefficient of thermal expansion mismatch between the organic substrate and other components of the microelectronic test device and to provide require stiffness to the organic substrate.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jin Pan, Jin Yang, Erkan Acar
  • Patent number: 9817029
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 9595453
    Abstract: The present disclosure relates to a chip package method and a package assembly. A metal plate is micro-etched to form trenches having a predetermined depth. A metallic conductor is formed as a leadframe by filling the trenches with a material having relatively small adhesion with the metal plate. In such manner, the metal plate can be peeled off from a package body after the chip is electrically coupled to the metallic conductor and encapsulated by a molding process. A bottom of the metallic conductor is exposed from the package body. A chip package is thus completed. It simplifies a manufacture process for forming a chip package, reduces manufacture cost, and increases reliability of the chip package.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: March 14, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Xiaochun Tan, Jiaming Ye
  • Patent number: 9579436
    Abstract: Techniques for mounting a sensor are disclosed. In some implementations, a molded interconnect device carries a sensor for transducing a position of a rotor of the implantable blood pump. The molded interconnect device includes one or more integrated electronic circuit traces configured to electrically connect the Hall sensor with a printed circuit board of the implantable blood pump, and the molded interconnect device is configured to be mounted to the printed circuit board.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 28, 2017
    Assignee: THORATEC CORPORATION
    Inventors: Mark McChrystal, Joseph C. Stark, III
  • Patent number: 9543255
    Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
  • Patent number: 9530831
    Abstract: A flexible display device and a method of manufacturing the same are provided. The flexible display device comprises a first flexible substrate including a display area including an organic light emitting layer, and a peripheral circuit area, and a second flexible substrate coming in contact with the first flexible substrate and including a pattern for facilitating bending thereof, wherein the second flexible substrate has a certain shape according to the pattern, and the first flexible substrate has a shape corresponding to the certain shape. Various embodiments of the present invention provide a flexible display device capable of realizing a narrow bezel-type or bezel-free display device and simultaneously realizing improved types of design, facilitating bending of a bezel area so as to realize a narrow bezel-type or bezel-free display device, and minimizing damage to an area to be bent.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 27, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Chanwoo Lee, JongHyun Park, TaeWoo Kim, Jaekyung Choi, Sangcheon Youn, SungJoon Min, SeYeoul Kwon, KwonHyung Lee
  • Patent number: 9492599
    Abstract: A molded interconnect device can carry a Hall sensor for transducing a position of a rotor of the implantable blood pump. The molded interconnect device includes one or more integrated electronic circuit traces configured to electrically connect the hall sensor with a printed circuit board of the implantable blood pump, and the molded interconnect device is configured to be mounted to the printed circuit board.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 15, 2016
    Assignee: THORATEC CORPORATION
    Inventors: Samuel Schimpf, Mark McChrystal, Joseph C. Stark, III, Andre Siebenhaar
  • Patent number: 9414501
    Abstract: The present invention provides systems and methods for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic or electromechanical component/device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 9, 2016
    Assignee: Board of Regents, The University of Texas System
    Inventors: Ryan B. Wicker, Francisco Medina, Eric MacDonald, Danny W. Muse, David Espalin
  • Patent number: 9396972
    Abstract: An IC assembly includes multiple microelectronic dies embedded in a substrate material using capillary forces such that the contact surface of each microelectronic die is coplanar with a planar upper surface of the substrate material. The substrate material is deposited as a layer of uncured polymer in a paste (or other solid form) on a base chip, and then the microelectronic dies are mounted on the layer surface in a predefined pattern. The uncured polymer is then heated until becomes a flowable liquid, causing the microelectronic dies to be pulled into the liquid polymer by capillary forces until the contact surface of each microelectronic die is coplanar with the upper liquid polymer surface. The liquid polymer is then cured to form the substrate material as a cross-linked robust solid film that fixedly secures the microelectronic dies in the predefined pattern. The microelectronic dies are then interconnected using standard metallization techniques.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: July 19, 2016
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Gregory L. Whiting, Rene A. Lujan
  • Patent number: 9332657
    Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a metal layer having metal member portions and connector portions connecting the metal member portions, forming laminated multilayer structures having electronic components and the metal member portions, respectively, forming cut penetrating holes in the connector portions of the metal layer, respectively, such that the connector portions of the metal layer are cut, and forming interlayer insulation layers on the laminated multilayer structures such that the laminated multilayer structures are interposed between the interlayer insulation layers. The forming of the interlayer insulation layers includes filling the cut penetrating holes with a resin derived from one or more interlayer insulation layers on the laminated multilayer structures.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 3, 2016
    Assignee: IBIDEN Co., Ltd.
    Inventors: Toshiki Furutani, Yukinobu Mikado, Mitsuhiro Tomikawa, Tomoya Terakura
  • Patent number: 9296056
    Abstract: An apparatus includes a top plate sized to cover components for a PCB in a solder operation to attach the components to a top surface of the PCB. The apparatus may include heat shielding devices and/or heat attracting devices. Each heat shielding device reduces heat transfer to a component to be soldered to the PCB and is positioned in the top plate to decrease heat to the component corresponding to the heat shielding device. Each heat attracting device increases heat transfer to a component to be soldered to the PCB and each heat attracting device is positioned in the top plate to increase heat to the component under the heat attracting device. The top plate is coupled to the heat shielding and/or heat attracting devices and includes a recess for each component configured with a heat shielding device or a heat attracting device.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel James Buschel, Michael J Fisher, James Edward Tersigni
  • Patent number: 9258907
    Abstract: A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited. Microvias may provide electrical connections between circuit layers.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 9, 2016
    Assignee: Lockheed Martin Corporation
    Inventors: Stephen Gonya, Kenn Twigg, Jim Patterson
  • Patent number: 9244099
    Abstract: Probe head assemblies, components of probe head assemblies, test systems including the probe head assemblies and/or components thereof, and methods of operating the same. The probe head assemblies are configured to convey a plurality of test signals to and/or from a device under test and include a space transformer, a contacting assembly, and a riser that spatially separates the space transformer from the contacting assembly and conveys the plurality of test signals between the space transformer and the contacting assembly. The contacting assembly may include a frame that defines an aperture and has a coefficient of thermal expansion that is within a threshold difference of that of the device under test, a flexible dielectric body that is attached to the frame, maintained in tension by the frame, and extends across the aperture, and a plurality of conductive probes. The plurality of conductive probes may include a dual-faceted probe tip.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 26, 2016
    Assignee: Cascade Microtech, Inc.
    Inventors: Koby Duckworth, Eric Hill
  • Patent number: 9198304
    Abstract: A method for manufacturing a rigid-flexible printed circuit board includes following steps. First, a flexible PCB is provided. The flexible PCB includes a base and an electrical trace layer on the base. The flexible PCB includes a first region and a second region connected to the first region. The first and second regions define a borderline. Second, a protective film and a peelable layer are sequentially formed on the electrical trace layer in the first region and part of the second region. Third, a copper coil, an adhesive tape and the flexible circuit board are laminated together. Fourth, the copper coil in the second region is etched to form an outer electrical trace layer. Last, the copper coil in the first region is removed and the peelable layer and the adhesive tape are peeled off, thereby obtaining an R-F PCB.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: November 24, 2015
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Biao Li
  • Patent number: 9150412
    Abstract: A method for producing a functional unit with a gas converter (1) and a flame ionization detector (10) is produced with the gas converter (1) and the flame ionization detector (10) being connected together as parts of a multi-layer ceramic (6).
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 6, 2015
    Assignee: KROHNE Messtechnik GmbH
    Inventor: Winfred Kuipers
  • Publication number: 20150135525
    Abstract: A method for selectively transferring active components from a source substrate to a destination substrate includes providing a source substrate having a process side including active components and a back side opposite the process side, the active components having respective primary surfaces including electrical connections thereon adjacent the process side and respective secondary surfaces opposite the primary surfaces and facing the back side; pressing a first stamp having first pillars protruding therefrom against the active components on the process side of the source substrate to adhere the respective primary surfaces of the active components including the electrical connections thereon to respective transfer surfaces of the first pillars; pressing a second stamp having second pillars protruding therefrom against the active components on the first pillars of the first stamp to adhere the respective secondary surfaces of the active components to respective transfer surfaces of the second pillars, wherei
    Type: Application
    Filed: November 14, 2014
    Publication date: May 21, 2015
    Inventor: Christopher Bower
  • Patent number: 9032608
    Abstract: In a method for manufacturing at least one mechanical-electrical energy conversion system including multiple individual parts, and a mechanical-electrical energy conversion, multiple different individual parts are positioned in an assembly device and joined in joining areas assigned to the individual parts in the assembly device, the individual parts including at least one piezoelectric element, one support structure and one seismic mass.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 19, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Franz Laermer, Thorsten Pannek, Ralf Reichenbach, Marian Keck
  • Publication number: 20150131136
    Abstract: A micromechanical component is described having a first substrate that has a first front side a first rear side facing away from the first front side; first printed conductors that are fashioned on the first front side of the first substrate; a plurality of actuator devices that are fashioned on and/or in the first substrate and that are electrically bonded to the first printed conductors, the actuator devices each having at least one stator electrode and each having at least one actuator electrode that works together with the at least one stator electrode, which are fashioned such that a voltage can be applied between the actuator electrode and cooperating stator electrode in such a way that the actuator electrode can be displaced relative to the stator electrode
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Hans ARTMANN, Jochen REINMUTH
  • Patent number: 9027242
    Abstract: A method of manufacturing an electrical device comprises the steps of providing a substrate, providing an electrical component on the substrate, providing a first electrical contact on the substrate that is electrically connected to the electrical component, and providing an electrochemical cell on or integrating the substrate for providing electrical energy to said electrical component. The electrochemical cell comprises at least one electrochemical layer comprising a cured or dried ink and a first electrode contact electrically connected to said at least one electrochemical layer. The method further includes the step of securing the electrochemical cell to the substrate through an electrically conductive connection that provides both a structural connection and an electrical connection between the first electrical contact and the first electrode contact.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Blue Spark Technologies, Inc.
    Inventor: Gary R. Tucholski
  • Patent number: 9027240
    Abstract: For the production of a flexible circuit configuration, which contains a layer sequence and a film connected thereto, for the creation of through contacts through the film up to terminal surfaces of the layer sequence, it is proposed that the film be connected unstructured to the layer sequence provided in a defined position on the substrate and then, while the composite of layer sequence and film remains on the substrate, perforations be created through the film up to terminal surfaces of a conductive layer of the layer sequence and contact metal be deposited in structured form on the film and in the perforations as through contacts.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 12, 2015
    Assignee: Cicor Management AG
    Inventors: Ernst Feurer, Bruno Holl, Alexander Kaiser, Karin Ruess
  • Publication number: 20150126134
    Abstract: Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 7, 2015
    Inventors: Anthony James LOBIANCO, Howard E. CHEN, David Scott WHITEFIELD
  • Patent number: 9021691
    Abstract: A method for introducing electrical insulations in a printed circuit board includes selectively introducing groove-shaped recesses between different regions of an electrically conductive layer on a substrate along a machining path using a thermal energy input such that end portions of each of the recesses or different ones of the recesses are joined to one another. The end portions are introduced parallel to one another without overlap such that a strip-shaped region of the conductive layer is initially retained between the end portions so as to insulate the different regions.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 5, 2015
    Assignee: LPKF Laser & Electronics AG
    Inventor: Jan van Aalst
  • Patent number: 9021689
    Abstract: A method of forming a dual port pressure sensor includes forming a first opening and a second opening in a flag of a lead frame. An encapsulant is molded to hold the lead frame in which the encapsulant is over a top of the flag and a bottom of the flag is uncovered by the encapsulant. A first opening in the encapsulant is aligned with and larger than the first opening in the flag and a second opening in the encapsulant aligned with the second opening in the flag. A pressure sensor transducer is attached to the bottom of the flag to cover the first opening in the flag, wherein the pressure sensor transducer provides an electrically detectable correlation to a pressure differential based on a first pressure received on its top side and a second pressure received on its bottom side. An integrated circuit is attached to the bottom of the flag. The integrated circuit is electrically coupled to the pressure sensor. A lid is attached to the encapsulant to form an enclosure around the bottom of the flag.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen R. Hooper, William G. McDonald
  • Publication number: 20150116972
    Abstract: A DC-DC converter assembly includes a board having a first side and a second side opposite the first side, a power stage die of a DC-DC converter attached to the first side of the board, and an output inductor electrically connected to an output of the power stage die and disposed over the power stage die on the first side of the board. The output inductor includes a magnetic core and an electrical conductor having first and second terminals attached to the first side of the board. The output inductor accommodates the power stage die under the magnetic core so that the power stage die is interposed between the magnetic core and the board. A corresponding method of manufacturing the DC-DC converter assembly and method of manufacturing the output inductor are also disclosed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Emil Todorov, Brian Molloy
  • Patent number: 9015931
    Abstract: A retention-extraction device is provided for a removable card in a chassis. The device includes an actuation rod having a cam slot, the actuation rod configured to provide linear movement along the length of the actuation rod, and an extraction lever operatively connected to a proximal end of the actuation rod and pivotally secured to the chassis. The device also includes a bell crank with a cam follower that is configured to ride in the cam slot and a latch hook that pivots between an open and closed position based on the motion of the bell crank. The linear movement of the actuation rod causes the extraction lever to apply a force to a portion of the card and causes the latch hook to pivot to an open position to allow removal of the card.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 28, 2015
    Assignee: Juniper Networks, Inc.
    Inventor: Kenneth D. Boetzer
  • Publication number: 20150109750
    Abstract: An electronic system includes a printed circuit board (PCB), and a heat dissipating element. The PCB includes one or more first electronic components mounted on a first side of the PCB, and one or more second electronic components mounted on a second side of the PCB. The first electronic components have a power consumption that is greater than a threshold and have a height over the first side of the PCB that is higher than any other electronic components mounted on the first side of the PCB. At least one of the second electronic components has a height over the second side of the PCB that is higher than the height of the first electronic components. The heat dissipating element is adjacent to the first electronic components so as to provide a thermal coupling for dissipating heat generated by the first electronic components.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 23, 2015
    Applicant: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Daniel ELKASLASSY, Daniel KALMANOVIZ
  • Patent number: 9009954
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes forming the Z-directed component in a cavity formed by a constraining material that defines the outer shape of the Z-directed component. The constraining material is dissipated to release the Z-directed component from the constraining material and the Z-directed component is fired.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 21, 2015
    Assignee: Lexmark International, Inc.
    Inventors: Keith Bryan Hardin, Paul Kevin Hall, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 9009956
    Abstract: Systems and methods are described that provide multilevel inverters having a plurality of levels using a simplified topology. For single phase systems, embodiments provide a full-bridge topology using bidirectional switching interconnections.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: April 21, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Yaosuo Xue, Madhav Manjrekar
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8997339
    Abstract: A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 7, 2015
    Assignee: Apple Inc.
    Inventors: Shih Chang Chang, John Z. Zhong, Lili Huang, Seung Jae Hong, Lynn Youngs
  • Patent number: 8997346
    Abstract: In order to avoid cost for accommodating a shield wire in a housing while bending, and smoothly and readily accommodate within the housing while the shield electric wire is insulated, a conductive housing 1 including a rear wall 4 continuing to an annular wall 3, and a tube wall 5 continuing to down the rear wall 4, a method comprising the steps of: passing through a shield electric wire 2 from a lower opening 5a of the tube wall of the conductive housing to a front opening 3a of the annular wall while bending the shield electric wire; putting a shield terminal 9 movably around the shield electric wire from top of the shield electric wire; exposing a core wire 2b and a braid 2a of the shield electric wire by stripping a tip thereof; connecting an L-shaped terminal 11 to the core wire; mounting an L-shaped insulation inner housing 12 outside the L-shaped terminal; connecting the shield terminal to the braid; and accommodating a vertical part 14 of the inner housing within the conductive housing by pulling in t
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 7, 2015
    Assignee: Yazaki Corporation
    Inventors: Takashi Omae, Kazuki Zaitsu
  • Patent number: 8998450
    Abstract: A light module (1; 14), comprising a carrier (8, 10) for mounting at least one semiconductor source (5), in particular a light emitting diode, wherein: the carrier (8, 10) has a flexible printed circuit board (10), the flexible printed circuit board (10) is bonded face-to face to at least one base plate, (8) and the carrier (8, 10) can be bent along at least one predetermined bending line (3; 3a-3e), the base plate (8) can be bent along the at least one bending line, (3; 3a-3e), the base plate (8) has at least one cutout (9) along the bending line (3; 3a-3e) and the flexible printed circuit board (10) has at least one strip (11; 15) which crosses at least one of the cutouts (9).
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 7, 2015
    Assignee: OSRAM GmbH
    Inventor: Thomas Preuschl
  • Publication number: 20150092378
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Mihir K. ROY, Mathew J. MANUSHAROW
  • Patent number: 8991040
    Abstract: A reusable electronic circuit assembling system facilitates assembly and testing of electronic circuits. The system has at least one baseboard and one or more assembling blocks magnetically or mechanically attached to the baseboard. Each assembling block has at least two electrically connected conductive clips located separately in the opening holes of the assembly block. Discrete electronic components are connected by selectively inserting the electrodes of the to-be-connected electronic components into the clips of the assembling blocks. A complete circuit is constructed by attaching the above block-component assemblies on the baseboard and connecting them in accordance with the desired circuit diagram.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 31, 2015
    Assignee: 5eTek, LLC
    Inventor: Erli Chen
  • Patent number: 8984748
    Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8978244
    Abstract: A method for manufacturing a printed circuit board with cavity includes following steps. First, a first substrate is provided. The first substrate includes a first electrically conductive layer defining an exposed portion and a laminating portion. Second, a second substrate is provided. The second substrate includes an unwanted portion corresponding to the exposed portion and a preserving portion. Third, a first annular bump surrounding the exposed portion is formed. Fourth, a second annular bump surrounding the unwanted portion is formed. Fifth, a first adhesive layer defining an opening is provided. Sixth, the first and second substrates are laminated to the first adhesive layer, the exposed portion and the unwanted portion are exposed in the opening, and the second annular bump is in contact with the first annular bump. Seventh, the unwanted portion is removed and a cavity is defined, the exposed portion is exposed in the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 17, 2015
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Xue-Jun Cai, Zhi-Yong Li, Chao Liu
  • Patent number: 8978217
    Abstract: A package manufacturing method where a base substrate and a lid substrate, at least one having a through-hole, are anodically bonded to each other using a jig having a communication-hole and arranged in a vacuum chamber to laminate the lid substrate to the base substrate and thereby form a bonded body having a plurality of cavities, each of which includes an electronic part sealed therein. The through-hole and the communication-hole are aligned with each other inside the vacuum chamber, such that gas within the cavities can escape through the through-hole and the communication-hole during bonding. A plurality of packages are formed by cutting the bonded body for every one of the plurality of cavities.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Takeshi Sugiyama
  • Patent number: 8973261
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Getac Technology Corporation
    Inventor: Cheng-Hung Chiang
  • Patent number: 8973258
    Abstract: A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Ching-Sheng Chen
  • Publication number: 20150060124
    Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto TERUI, Takashi KARIYA, Yoshinori SHIZUNO, Masatoshi KUNIEDA
  • Publication number: 20150060127
    Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
  • Publication number: 20150062836
    Abstract: The present disclosure relates to a stacked package of a voltage regulator and a method for fabricating the same.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventor: Wei Chen
  • Publication number: 20150062832
    Abstract: A method and apparatus provides an Intelligent Electronic Device (IED) with new hardware modules. Hardware modules are provided that are configured for electrically connecting with connections of a first IED housing that has a first form factor. A second IED housing is provided having a second form factor that is different from the first form factor. The hardware modules are mounted in the second housing. Adaptor structure is employed to electrically connect the hardware modules with connections of the second housing. The second housing is mounted into an existing wiring and second form factor environment.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: ABB Technology AG
    Inventors: Shamsi Ismayilov, Yaser A. Khalifa, Frantisek Koudelka, Arkady Oksengorn, Siu Lau, Hardik Patel, In Y. Choi
  • Patent number: 8966731
    Abstract: A method for manufacturing a switching element which has enough resistance to repeat switching operations and which can be miniaturized and have low power consumption, and a display device including the switching element are provided. The switching element includes a first electrode to which a constant potential is applied, a second electrode adjacent to the first electrode, and a third electrode over the first electrode with a spacer layer formed of a piezoelectric material interposed therebetween and provided across the second electrode such that there is a gap between the second electrode and the third electrode. A potential which is different from or approximately the same as a potential of the first electrode is applied to the third electrode to expand and contract the spacer layer, so that a contact state or a noncontact state between the second electrode and the third electrode can be selected.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Honda
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: J├╝rgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8959734
    Abstract: An interactive card or the like employs a piezoelectric charge generator (piezo-strip) for temporarily driving an indicator. The piezo-strip may be displaced (bent) in order to generate charge to drive the indicator. Printed electronic processes are utilized to produce the indicator and/or the piezoelectric charge generator. An indicator is formed on a substrate by way of a printed electronics process. A displaceable region of piezoelectric material associated with the said substrate is formed by way of a printed electronics process. Electrical interconnections are formed on said substrate by way of a printed electronics process. The electrical interconnections connecting said indicator and said first region of piezoelectric material such that displacement of said first region of piezoelectric material generates a voltage therein that is provided to said indicator in order to actuate said indicator and thereby indicate the displacement of said first region of piezoelectric material.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 24, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Tse Nga Ng
  • Patent number: 8959760
    Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 24, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Kazuhisa Kitajima