With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
  • Publication number: 20130291380
    Abstract: The present invention is: a package main body section having a hollow section; and an electronic device provided in the hollow section in the package main body section, in the package main body section, there being formed a through hole, through which the hollow section communicates with outside of the package main body section, and in the through hole, there being provided a sealing section in which a vicinity of the through hole is partly heated and a constituent material of the package main body section is melted to thereby block the through hole.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Applicant: NEC CORPORATION
    Inventors: TAKAO YAMAZAKI, MASAHIKO SANO, SEIJI KURASHIMA, YOSHIMICHI SOGAWA
  • Publication number: 20130294034
    Abstract: A method of manufacturing an electronic component module includes sealing a surface of an aggregate substrate on which a plurality of electronic components are mounted with a sealing resin and cutting boundary portions between electronic component modules from an outer surface of the sealing resin to a position at least partially through the aggregate substrate to form first grooves. A shield layer is formed by coating the outer surface of the sealing resin with a conductive resin and filling the first grooves with the conductive resin, and recesses are formed at positions on the shield layer where the first grooves are formed. The boundary portions between electronic component modules are cut along the corresponding recesses so that second grooves each having a width smaller than the width of a corresponding one of the recesses are formed, and the aggregate substrate is singulated into the individual electronic component modules.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Koichi KANRYO, Akio KATSUBE, Shunsuke KITAMURA
  • Patent number: 8567053
    Abstract: Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit including attaching a plurality of metal layer carriers to form a first subassembly including at least one copper foil pad on a first surface, applying an encapsulation material onto the first surface of the first subassembly, curing the encapsulation material and the first subassembly; applying a lamination adhesive to a surface of the cured encapsulation material, forming at least one via in the lamination adhesive and the cured encapsulation material to expose the at least one copper foil pad, attaching a plurality of metal layer carriers to form a second subassembly, and attaching the first subassembly and the second subassembly.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: October 29, 2013
    Assignee: DDI Global Corp.
    Inventors: Rajesh Kumar, Monte P. Dreyer, Michael J. Taylor
  • Patent number: 8567040
    Abstract: An iron core includes an electromagnetic steel plate having a first region on the surface of which an insulating film is formed and a second region which is not covered with the insulating film and exposed, and a coating member which coats at least the second region. The second region is formed by removing the insulating film by machining.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: October 29, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroyoshi Kubo
  • Publication number: 20130271928
    Abstract: A circuit module pertaining to an embodiment of the present invention has a board, multiple electronic components, a shield member, sealing layer, and cover layer. The board has a mounting surface that includes a first area and second area in which the multiple electronic components are mounted. The shield member is constituted by conductive material and placed between the first area and second area on the mounting surface. The sealing layer has on its top surface a groove having its bottom face including an upper end face of the shield member, is formed on the mounting surface, and is constituted by an insulator that covers the multiple electronic components. The cover layer is constituted by conductive material and has a first cover part that fills the groove as well as a second cover part that covers the first cover part and sealing layer.
    Type: Application
    Filed: March 22, 2013
    Publication date: October 17, 2013
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Masaya SHIMAMURA, Eiji MUGIYA
  • Patent number: 8555493
    Abstract: Described herein is a method of manufacturing a molded printed circuit board. The printed circuit board may be placed inside of a mold and a material is injected therein. The material hardens in the mold around the printed circuit board thereby forming an overmolded printed circuit board. The overmolded material may have apertures in it to allow access to the leads on the printed circuit board so that components to be connected to it. The overmolded printed circuit boards may allow a plurality of electrical components to selectively and removably attach to it. Further, the printed circuit board may be molded with components or a dock attached to it.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 15, 2013
    Assignee: Psion, Inc.
    Inventors: Bo Xu, Yanmin Mao
  • Publication number: 20130263446
    Abstract: A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250° C.-300° C. at a ramp rate of 50° C./second-100° C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.
    Type: Application
    Filed: September 30, 2011
    Publication date: October 10, 2013
    Applicant: Intel Corporation
    Inventors: Sivakumar Nagarajan, Sandeep Razdan, Nisha Ananthakrishnan, Craig J. Weinman, Kabirkumar J. Mirpuri
  • Patent number: 8544167
    Abstract: There is disclosed a collective mounting method of electronic components in which a plurality of electronic components can uniformly be pressed to an insulating layer in a short time in a case where the electronic components and a resin layer are fixed. To manufacture a semiconductor-embedded substrate 200 in which a plurality of semiconductor devices 220 are embedded, after disposing the plurality of semiconductor devices 220 on an unhardened resin layer 212, this is stored in a container 31 of a pressurizing and heating unit 3, the plurality of semiconductor devices 220 are simultaneously, collectively and isotropically pressurized by use of an internal gas in the container 31 as a pressure medium to simultaneously press the plurality of semiconductor devices 220 to the unhardened resin layer 212, and the resin layer 212 is heated and hardened.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 1, 2013
    Assignee: TDK Corporation
    Inventor: Takaaki Morita
  • Publication number: 20130249069
    Abstract: A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Khalil Hosseini, Joachim Mahler, Edward Fuergut
  • Patent number: 8536684
    Abstract: A method of assembling an integrated circuit (IC) device includes the steps of providing a lead frame or substrate panel, attaching a semiconductor die to the lead frame or substrate panel and electrically coupling the die to the lead frame or substrate panel. The method further includes encapsulating the die with a first encapsulant, and the encapsulating the first encapsulant with a second encapsulant where the second encapsulant includes a material that provides electromagnetic shielding.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 17, 2013
    Assignee: Freescale Semiconductor. Inc
    Inventors: Wei Min Chen, Zhigang Bai, Zhijie Wang
  • Patent number: 8528190
    Abstract: A method of manufacturing a power module on a substrate. In one embodiment, the method includes providing power conversion circuitry including providing a magnetic device having a magnetic core and at least one switch on the substrate. The method also includes placing a shielding structure with a baffle over the magnetic core to create a chamber thereabout. The method also includes depositing an encapsulant about the power conversion circuitry. The shielding structure limits the encapsulant entering the chamber and the baffle directs the encapsulant away from the magnetic core thereby limiting an amount of the encapsulant that contacts the magnetic core within the chamber.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: September 10, 2013
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Mathew Wilkowski, John D. Weld
  • Patent number: 8528195
    Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Patent number: 8528196
    Abstract: A component mounting apparatus for mounting components on a plurality of mounting regions placed on an edge part of a substrate along a first direction that is a direction along the edge part of the substrate, comprises component placing units for holding components placed in component delivery positions that are spaced from the edge part of the substrate in a second direction orthogonal to the first direction, moving the held components in the second direction, and placing the components onto the mounting regions, component feeding units for sequentially feeding the components to component feeding positions spaced from the component delivery positions, and component carrying units for holding the components fed to the component feeding positions, moving the held components, and placing the components in the component delivery positions. Therefore, the components can be placed even onto a large substrate with satisfactory working efficiency.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuaki Kosaka, Akira Kabeshita, Nobuhiko Muraoka, Syozo Kadota
  • Publication number: 20130229777
    Abstract: A chip arrangement is provided: the chip arrangement including: a carrier; a chip disposed over the carrier; a ceramic layer formed over the chip and on at least a portion of the carrier; wherein the chip is surrounded by the carrier and the ceramic layer.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Marco Seibt
  • Publication number: 20130223038
    Abstract: A module substrate includes a plurality of electronic components mounted on at least one surface of a base substrate and a columnar terminal connection substrate connected to the one surface of the base substrate on which a plurality of the electronic components are mounted. The terminal connection substrate includes a plurality of conductor portions, at least one corner of the columnar terminal connection substrate is chamfered with a flat surface and/or curved surface, and the terminal connection substrate is connected at a side surface thereof contacting the chamfered surface, to the one surface of the base substrate.
    Type: Application
    Filed: April 16, 2013
    Publication date: August 29, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Murata Manufacturing Co., Ltd.
  • Publication number: 20130219712
    Abstract: Embodiments disclosed herein include a method of manufacturing a multilayer wiring board that includes the steps of forming, on a support substrate, a laminate in which insulating layers and conductor layers are alternately laminated, accommodating a semiconductor chip in an opening of a prepreg which is formed on the surface of the laminate and that includes a sheet-like glass fiber impregnated with resin, and heating and pressurizing the surface of the prepreg in a state where the semiconductor chip is accommodated in the opening.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 29, 2013
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventor: NGK SPARK PLUG CO., LTD.
  • Publication number: 20130223018
    Abstract: A high-density Subscriber Identity Module (SIM) card package and a production method thereof are provided. The SIM card package includes a substrate, an Integrated Circuit (IC) chip, a bonding wire, and a mold cap. The substrate is a two-layer, a four-layer, a six-layer or an eight-layer high-density interlinked and packaged organic laminated substrate that is manufactured through an etching-back process, and a passive device and a crystal oscillator are provided on the organic laminated substrate. Two IC chips are provided side by side, or one of the IC chips is stacked with a third IC chip, the third IC chip being respectively connected to the organic laminated substrate and the IC chip under the third IC chip by the bonding wire.
    Type: Application
    Filed: December 30, 2010
    Publication date: August 29, 2013
    Applicant: TIANSHUI HUATIAN TECHNOLOGY CO., LTD.
    Inventors: Jianyou Xie, Xiaowei Guo, Wenhai He, Wei Mu, Xin Chen
  • Patent number: 8516693
    Abstract: The present invention discloses a printed circuit board. The printed circuit board is made by the method of providing a substrate; forming a first circuit on the substrate; depositing a thin film on the substrate; building an electronic component on the substrate by the thin film and allowing the electronic component to electrically connect the first circuit; forming a blanket dielectric layer enclosing the electronic component; and removing the substrate.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: August 27, 2013
    Assignee: Mutual-Tek Industries Co., Ltd.
    Inventor: Jung-Chien Chang
  • Publication number: 20130215579
    Abstract: One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate.
    Type: Application
    Filed: March 18, 2013
    Publication date: August 22, 2013
    Applicant: MARVELL WORLD TRADE LTD.
    Inventor: MARVELL WORLD TRADE LTD.
  • Publication number: 20130215583
    Abstract: An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Michael B. Vincent
  • Patent number: 8510936
    Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chih-Hong Chuang, Tzu-Wei Huang
  • Patent number: 8510935
    Abstract: A method for producing an assembly of electronic components and assemblies in accord with this, wherein the electronic components have component terminals. A conductive firmament having a first side and a second side is provided. Then the component terminals are connected to the first side of the firmament with an anisotropic conductor. A pattern is applied to the second side of said firmament. And portions of the firmament are removed based on the pattern, such that remaining portions of said firmament form the electrical circuit interconnecting the component terminals.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 20, 2013
    Inventor: Joseph C. Fjelstad
  • Publication number: 20130208433
    Abstract: The invention relates to a circuit module (10) having a circuit carrier (12), at least one circuit (14) mounted on the circuit carrier (12), encapsulated by a protective material (16), and at least one electrical/electronic component (18) encapsulated by a protective coating (20), protecting the at least one electrical/electronic component (18) from the protective material (16), and to a method for producing the circuit module (10). According to the invention, the protective coating (20) protecting the at least one electrical/electronic component (18) is only partially encapsulated by the protective material (16).
    Type: Application
    Filed: December 7, 2010
    Publication date: August 15, 2013
    Applicant: ROBERT BOSCH GMBH
    Inventors: Stephan Mazingue-Desailly, Michael Mueller
  • Publication number: 20130206458
    Abstract: In a suspension board, a conductor layer having a predetermined pattern is formed on the upper surface of a first insulating layer. The first insulating layer has a thick portion having a large thickness and a thin portion having a small thickness. A reinforcing layer is formed on the upper surface of the first insulating layer so as to overlap with a boundary between the thick portion and the thin portion.
    Type: Application
    Filed: November 21, 2012
    Publication date: August 15, 2013
    Applicant: NITTO DENKO CORPORATION
    Inventor: Terukazu IHARA
  • Patent number: 8502339
    Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye
  • Publication number: 20130194764
    Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.
    Type: Application
    Filed: July 31, 2012
    Publication date: August 1, 2013
    Applicant: IBIDEN CO., LTD.
    Inventors: Yukinobu MIKADO, Shunsuke SAKAI, Takashi KARIYA, Toshiki FURUTANI
  • Publication number: 20130188349
    Abstract: A method of manufacturing a multichip package structure includes: providing a substrate body; placing a plurality of light-emitting chips on the substrate body, where the light-emitting chips are electrically connected to the substrate body; surroundingly forming surrounding liquid colloid on the substrate body to surround the light-emitting chips; naturally drying an outer layer of the surrounding liquid colloid at a predetermined room temperature to form a semidrying surrounding light-reflecting frame, where the semidrying surrounding light-reflecting frame has a non-drying surrounding colloid body disposed on the substrate body and a dried surrounding colloid body totally covering the non-drying surrounding colloid body; and then forming a package colloid body on the substrate body to cover the light-emitting chips, where the semidrying surrounding light-reflecting frame contacts and surrounds the package colloid body.
    Type: Application
    Filed: March 21, 2012
    Publication date: July 25, 2013
    Applicant: PARAGON SEMICONDUCTOR LIGHTING TECHNOLOGY CO., LTD.
    Inventors: CHIA-TIN CHUNG, CHAO-CHIN WU, FANG-KUEI WU
  • Publication number: 20130185934
    Abstract: A resin composition sheet for encapsulating electronic parts and a method of producing an electronic part apparatus using the sheet are provided. The method includes: loading, on a substrate, a resin composition sheet for encapsulating electronic parts including a thermosetting resin composition containing an epoxy resin, a phenol resin, an inorganic filler, and a curing accelerator, having a lowest viscosity in a specific range, and a thickness in a specific range; heating the substrate in a chamber in a decompressed state to sag an end portion of the sheet until it is in contact with a surface of the substrate; and releasing a pressure in the chamber to cause the sheet to adhere onto the substrate due to a difference between a pressure in the space between the sheet and the substrate, and the pressure in the chamber after the release, followed by thermal curing.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 25, 2013
    Applicant: NITTO DENKO CORPORATION
    Inventor: NITTO DENKO CORPORATION
  • Patent number: 8490282
    Abstract: According to one feature of the present invention, a method of manufacturing a porous catcher includes providing a catcher face material layer; forming pores in the catcher face material layer using a first etching process that is controlled by a first photolithographic mask; providing a reinforcing structure material layer that is in mechanical contact with the porous catcher face; forming openings in the reinforcing structure material layer using a second etching process that is controlled by a second photolithographic mask; and fluidically connecting the openings in the reinforcing structure and the pores of the catcher face using a material removal process.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: July 23, 2013
    Assignee: Eastman Kodak Company
    Inventors: Shan Guan, Yonglin Xie, Chang-Fang Hsu
  • Publication number: 20130182401
    Abstract: A wiring board includes a substrate which has multiple opening portions and one or more boundary portions separating the opening portions, multiple electronic devices positioned in the opening portions of the substrate, respectively, a conductive pattern formed on a surface of the boundary portion, and an insulation layer formed on the substrate and the conductive pattern on the boundary portion of the substrate such that the insulation layer covers the electronic devices in the opening portions of the substrate.
    Type: Application
    Filed: November 28, 2012
    Publication date: July 18, 2013
    Applicant: IBIDEN CO., LTD.
    Inventor: IBIDEN CO., LTD.
  • Publication number: 20130176746
    Abstract: A component built-in module of the present invention includes: a flexible substrate that includes a first surface and a second surface on an opposite side of the first surface, the first surface including a concave part recessed in a direction from the first surface toward the second surface; a plurality of electronic components that are mounted on the first surface, mounting heights of the electronic components from the first surface to respective upper surfaces of the electronic components differing from each other; and a resin that seals the first surface. Among the plurality of electronic components, at least an electronic component having a highest mounting height is mounted in the concave part.
    Type: Application
    Filed: July 19, 2011
    Publication date: July 11, 2013
    Applicant: NEC CORPORATION
    Inventors: Nozomu Nishimura, Nobuhiro Mikami
  • Publication number: 20130176686
    Abstract: The invention specifies a module comprising a carrier substrate (6) having an electrical wiring and a component chip mounted on the carrier substrate (6) using flip-chip technology, wherein the component chip (1) has, on its surface (2) facing the carrier substrate (6), component structures (3), a supporting frame (4) and supporting elements (5), the supporting elements (5) produce an electrical connection between the component structures (3) and the electrical wiring of the carrier substrate (6), and the height of the supporting elements and the height of the supporting frame (4) correspond. Furthermore, the invention specifies a method for producing the module.
    Type: Application
    Filed: June 15, 2011
    Publication date: July 11, 2013
    Applicant: EPCOS AG
    Inventors: Kim Choong Lee, Marc Huesgen
  • Patent number: 8479384
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar M. Subramanian
  • Patent number: 8474134
    Abstract: A functional element-mounted module can be decreased in size and requires no costly and special members for a light transition member. A substrate is used, on which an optical functional element having an optical function part and bonding pads therearound is mounted by wire bonding, with an upper face of the element upward. A bank to dam a liquid sealing resin is provided around the optical functional element on the substrate, and the liquid sealing resin is dropped and filled between the optical functional element and the bank such that the bonding pads and partial gold wires for the wire bonding are exposed. A package-component member having a hole corresponding to the optical functional element is abutted to the bank such that the hole is opposed to the function part of the functional element. Thereby, the package-component member is contacted to the liquid sealing resin. The package-component member is fixed to the substrate by curing the liquid sealing resin, and the bank is cut away.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 2, 2013
    Assignee: Dexerials Corporation
    Inventors: Yoshihiro Yoneda, Takahiro Asada, Kazuaki Suzuki
  • Publication number: 20130163210
    Abstract: An integrated structure for interconnection of electrical components is provided. In one embodiment, the integrated structure includes a through mold via (TMV) module having a substrate and at least one component coupled to the substrate. A flexible printed circuit board (flex-PCB) is integrated with the substrate of the TMV module. A TMV is provided through a body of the module to allow the flex-PCB to couple with a logic board.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Applicant: Apple Inc.
    Inventors: Emery A. Sanford, Sean A. Mayo
  • Publication number: 20130155639
    Abstract: An electronic component includes a substrate, first electronic components mounted on a first principle surface of the substrate, a first resin layer that covers the first principal surface of the substrate and the first electronic components, a second electronic component mounted on a second principle surface of the substrate, a second resin layer that covers the second principal surface of the substrate and the second electronic component, an electrically conductive shield layer, and a ground electrode arranged in the substrate so as to reach a side surface of the substrate. The shield layer is a single continuous layer that covers the first resin layer, the side surface of the substrate, and a portion of the second resin layer adjacent to the substrate. The shield layer is in contact with and electrically connected to the ground electrode.
    Type: Application
    Filed: February 14, 2013
    Publication date: June 20, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Murata Manufacturing Co., Ltd.
  • Patent number: 8458889
    Abstract: An actuator manufacturing method includes alternately stacking a plurality of dielectric elastomer layers and a plurality of conductive rubber layers along the direction of thickness to form a sheet, and wrapping the sheet formed about a core to form a rolled sheet. When the sheet formed in the step of alternately stacking is wrapped about the core, the sheet is formed by the dielectric elastomer layers and the conductive rubber layers. Therefore, even if the dielectric elastomer layers in the sheet are made to be thin, the thickness of the entire sheet is prevented from being excessively thin.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 11, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yutaka Tsuchikawa, Takashi Maeno, Naoto Kuriyama, Takanori Nakai, Hiromitsu Takeuchi, Yoji Kimura
  • Patent number: 8458901
    Abstract: A method for manufacturing an electronic component embedded connector includes a first step for fixing a terminal to a fixing means; a second step for fixing electronic components to the fixing means; a third step for cutting connecting sections of the terminal fixed to the fixing means; a fourth step for connecting the electronic components fixed to the fixing means, to the terminal in which the connecting sections are cut off; and a fifth step for covering a section of the terminal other than terminal sections, and the electronic components by an insulating cover.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 11, 2013
    Assignees: Union Machinery Co., Ltd., Furukawa Electric Co., Ltd., Furukawa Automotive Systems, Inc.
    Inventors: Shinji Yamaguchi, Tetsu Hirose, Kenichi Abe
  • Publication number: 20130141886
    Abstract: An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Applicant: CYNTEC CO., LTD.
    Inventor: Cyntec Co., Ltd.
  • Patent number: 8453318
    Abstract: A method of making a planar coil is disclosed in the present invention. First, a substrate having a trench is provided. Then, a barrier and a seed layer are formed on the substrate in sequence. An isolative layer is used for guiding a conductive material to flow into a lower portion of the trench such that accumulation of the conductive material at opening of the trench is prevented before the lower portion of the trench is completely filled up, thereby avoiding gap formation in the trench.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: June 4, 2013
    Assignee: Touch Micro-System Technology Corp.
    Inventors: Hung Yi Lin, Ming Fa Chen
  • Patent number: 8456266
    Abstract: A vacuum cast or “solid” transformer coil assembly and a method of manufacturing thereof are provided. A solid transformer coil assembly, according to an embodiment of the invention, includes a dielectric substrate, the coil windings provided around the substrate, and an epoxy compound encapsulating the substrate and the coil windings. The substrate is provided with raised “buttons” comprising the same epoxy material as the epoxy compound used for encapsulation. The buttons maintain a specific distance between the coil and the dielectric substrate. The buttons are arranged such that they support the windings and allow the encapsulating epoxy to flow around them flooding the entire mold without entrapping air or creating voids.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: June 4, 2013
    Assignee: Engineered Products of Virginia, LLC
    Inventor: Curtis Frye
  • Publication number: 20130118010
    Abstract: Microwave or millimeter wave module packaging having a module with a baseplate, transition board and cover. The baseplate includes microwave or millimeter wave components attached thereto. The transition board includes a first connector attached to a first side thereof and operatively connected to the components, and a second connector attached to a second side thereof and operatively connected to the components through the board. The cover and baseplate form a cavity containing the board and components, and the second connector may be operatively connected to a third connector such as a printed circuit board disposed outside of the cavity and on a higher level assembly. The transition board may further include a fourth connector operatively connected to the components for providing a signal to an external component or device or receiving a signal from an external component or device.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 16, 2013
    Applicant: HARRIS STRATEX NETWORKS OPERATING CORPORATION
    Inventor: HARRIS STRATEX NETWORKS OPERATING CORPORATION
  • Publication number: 20130118009
    Abstract: A method for manufacturing a printed circuit board includes the following steps. First, a first copper foil having first and second surfaces is provided. Second, the first copper foil is etched to remove portions of the first copper foil to convert the first copper foil into an intermediate structure having a substrate and first protrusions. Each first protrusion is exposed at the first surface. Third, a first insulation material fills into gaps between the first protrusions. Fourth, a second copper foil is laminated on the first surface. Fifth, the intermediate structure is etched from the second surface to remove portions of substrate to convert the substrate into second protrusions. Sixth, a second insulation material is infilled into gaps between the second protrusions. Seventh, a third copper foil is laminated on the second surface. Finally, the copper foils are patterned to be second and third patterns.
    Type: Application
    Filed: October 23, 2012
    Publication date: May 16, 2013
    Inventor: RUI-WU LIU
  • Publication number: 20130114228
    Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.
    Type: Application
    Filed: September 28, 2012
    Publication date: May 9, 2013
    Applicant: APPLE INC.
    Inventor: Apple Inc.
  • Publication number: 20130112465
    Abstract: A printed circuit board (PCB) is provided comprising a plurality of non-conductive layers with conductive or signal layers in between. The PCB includes a first conductive via traversing the plurality of non-conductive and conductive or signal layers as well as a second conductive via traversing the plurality of non-conductive layers and conductive or signal layers, the second conductive via located substantially parallel to the first conductive via. An embedded electro-optical passive element is also provided that extends perpendicular to and between the first conductive via and the second conductive via. The electro-optical passive element embedded is located within a selected layer at a first depth in the printed circuit board, wherein such first depth is selected to reflect an incident electromagnetic wave back into the printed circuit board to enhance or diminish an electrical signal in the first conductive via by creating a positive or negative electromagnetic interference.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 9, 2013
    Applicant: SANMINA-SCI CORPORATION
    Inventor: SANMINA-SCI CORPORATION
  • Patent number: 8434220
    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: May 7, 2013
    Assignee: RF Micro Devices, Inc.
    Inventors: Jayanti Jaganatha Rao, Thomas Scott Morris, Milind Shah
  • Publication number: 20130105201
    Abstract: An electronic component-embedded printed circuit board and a method of manufacturing the same. The printed circuit board includes a base substrate including a hollow electronic component case, an electronic component inserted into the electronic component case, circuit pattern layers formed on upper and lower surfaces of the base substrate, and an insulating layer formed to cover the circuit pattern layers. Accordingly, since the printed circuit board includes the electronic component case formed therein and the electronic component is inserted into only the printed circuit board, which has no defect after manufacture and final inspection of the printed circuit board, component loss due to yield of the printed circuit board can be reduced.
    Type: Application
    Filed: May 30, 2012
    Publication date: May 2, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong In Ryu, Jin Won Lee, Yul Kyo Chung
  • Publication number: 20130107440
    Abstract: A storage device including a circuit board, an electronic device package and a terminal module is provided. The circuit board has a first surface and a second surface opposite to each other, a plurality of via-holes connecting the first surface and the second surface, a plurality of first pads on the first surface, and a plurality of first pads on the second surface. The electronic device package is disposed on the first surface. The terminal module disposed on the first surface has a plurality of first and second contact parts, and each of the first contact parts passes through the corresponding via-hole and is protruded out of the second surface, and each of the second contact parts is electrically connected to the corresponding first pad. An orthogonal projection area of the electronic device package on the first surface is smaller than an area of the first surface.
    Type: Application
    Filed: December 9, 2011
    Publication date: May 2, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Hung Lin, Hung-I Chung
  • Patent number: 8424175
    Abstract: A process for fabricating a piezoactuated storage device having a tip array and a memory media, which includes but is not limited to: etching the regions on the surface of the silicon wafer to produce substantially pyramidal etch pits by anisotropic etching or chemical etching with potassium hydroxide (KOH); growing an oxide layer on a top surface of the silicon wafer and in the substantially pyramidal etch pits to produce oxidation sharpening of the substantially pyramidal etch pits; forming an array of conductive tips of a nanocarbon film of nanostructured carbon material by deposition, wherein the nanostructured carbon material is ultrananocrystalline diamond (UNCD), ta-C, or diamond-like carbon films; and forming an oxygen diffusion barrier layer by deposition of a TiAl, TaAl, or any other oxygen diffusion barrier layer material on the nanocarbon film.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: April 23, 2013
    Assignee: UChicago Argonne, LLC
    Inventor: Orlando H. Auciello
  • Publication number: 20130094151
    Abstract: Systems, processes, and manufactures are provided that employ a casing associated with an electrical component to provide some, most, substantially all or all electrical insulative protection necessary for the electrical component. This casing may be further employed with potting or other materials to supplement and add additional or different protections for the component. These additional protections can include additional insulative resistance, thermal protection, moisture protection and other buffers to and from the environment.
    Type: Application
    Filed: November 9, 2011
    Publication date: April 18, 2013
    Applicant: SOLARBRIDGE TECHNOLOGIES, INC.
    Inventors: Eduardo Escamilla, Marco Marroquin, William John Morris, John Trevor Morrison, Thomas Paul Parker, Stephen Wurmlinger