With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
  • Patent number: 11515174
    Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Youngik Kwon, Jong Sik Paek
  • Patent number: 11477927
    Abstract: In the component mounting system, when an electronic component having a positioning target is held and mounted onto the upper face of a board, the positioning target is aligned to a predetermined position of the board. The component mounting system detects a positional deviation of the positioning target on the upper face of the electronic component and performs an arrangement operation of arranging a positioning material on the board by correcting the arrangement position in accordance with the detected positional deviation. The component mounting system then performs a mounting operation for mounting the electronic component on the board by aligning the positioning target to the predetermined position of the board on which the positioning material has been arranged.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 18, 2022
    Assignee: FUJI CORPORATION
    Inventors: Takeshi Sakurayama, Kota Niwa
  • Patent number: 11462454
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 4, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
  • Patent number: 11464120
    Abstract: A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-jae Han
  • Patent number: 11457524
    Abstract: A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 27, 2022
    Assignee: NXP B.V.
    Inventors: Mahmoud Mohamed Amin El Sabbagh, Anu Mathew, Siamak Delshadpour
  • Patent number: 11327468
    Abstract: When a specification setting unit sets a specification of a lot number “k+1” after setting a specification of a lot number “k”, a mounting program selector performs a mounting program corresponding to the lot number “k”, and then selects a mounting program corresponding to the lot number “k+1” according to matching between a mounting number from the mounting program and a planned number of products of the lot number “k”. A printing program selector selects a printing program corresponding to the lot number “k”, and then selects a printing program corresponding to the lot number “k+1” according to matching between a sum of a printing number from the printing program and a defective product number and the planned number of products of the lot number “k”. Consequently, on-demand production of an electronic device can easily be manufactured on a manufacturing line.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 10, 2022
    Assignee: OMRON CORPORATION
    Inventor: Wakahiro Kawai
  • Patent number: 11292166
    Abstract: A method, for manufacturing an electronic assembly, such as an antenna or a capacitive sensing device or a coupled inductor, comprising at least a first electrically conductive element and a second electrically conductive element is presented. The method comprises obtaining said electrically conductive elements, such as patch elements, arranging said electrically conductive elements, such as inside of a cavity defined by a mold structure, at a pre-defined distance from each other for establishing an electromagnetic coupling between said electrically conductive elements, and molding, such as injection molding, a molding material layer at least between said electrically conductive elements, wherein the molding material layer has a thickness between said electrically conductive elements defined by the pre-defined distance. In addition, electronic assemblies, antennas, capacitive sensing devices and coupled inductors are presented.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 5, 2022
    Assignee: TACTOTEK OY
    Inventors: Anne Isohätälä, Hasse Sinivaara, Mikko Heikkinen
  • Patent number: 11297718
    Abstract: A method of manufacturing a flexible circuit comprises providing a laminated substrate that includes a conductive layer, an adhesive layer, and a support layer. The method comprises forming conductive traces by removing selected portions of the conductive layer and the adhesive layer by dry milling the laminated substrate. The method comprises applying a protective coating to the conductive traces. The method comprises dispensing a solder material on the protective coating at a first connection point and arranging a first component at the first connection point. The method comprises heating the solder material to remove the protective coating from the first connection point and to connect the first component to one of the conductive traces at the first connection point. The method comprises attaching a second component to the conductive layer at a second connection point that is free of the protective coating by a process other than soldering.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 5, 2022
    Assignee: Gentherm GmbH
    Inventor: Michael Peter Ciaccio
  • Patent number: 11285645
    Abstract: A method, for manufacturing an electronic assembly, such as an antenna or a capacitive sensing device or a coupled inductor, comprising at least a first electrically conductive element and a second electrically conductive element is presented. The method comprises obtaining said electrically conductive elements, such as patch elements, arranging said electrically conductive elements, such as inside of a cavity defined by a mold structure, at a pre-defined distance from each other for establishing an electromagnetic coupling between said electrically conductive elements, and molding, such as injection molding, a molding material layer at least between said electrically conductive elements, wherein the molding material layer has a thickness between said electrically conductive elements defined by the pre-defined distance. In addition, electronic assemblies, antennas, capacitive sensing devices and coupled inductors are presented.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 29, 2022
    Assignee: TACTOTEK OY
    Inventors: Anne Isohätälä, Hasse Sinivaara, Mikko Heikkinen
  • Patent number: 11191186
    Abstract: A system and method for cooling electronic devices disposed within the inner volume of an enclosure. The inner volume of the enclosure contains one or more single phase or multi-phase thermally conductive fluids and may contain solid or sealed hollow structures that displace and direct thermally conductive fluids.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 30, 2021
    Inventor: David Lane Smith
  • Patent number: 11122710
    Abstract: An electronic device comprises a heat dissipating layer disposed on a rear cover, a first shield cover and a second shield cover disposed on a mainboard, and a speaker box disposed on a surface of an antenna panel. The first region of the heat dissipating layer is in contact with the first shield cover, and the second shield cover is in contact with a first region of a middle frame; a second region of the heat dissipating layer is in contact with a surface of a battery, and the other surface of the battery is in contact with a second region of the middle frame, and a third region of the heat dissipating layer is in contact with a surface of the speaker box that is distant from the antenna panel, and the other surface of the antenna panel is in contact with a third region of the middle frame.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 14, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Linfang Jin, Guo Yang, Shuainan Lin
  • Patent number: 10935813
    Abstract: Designs, apparatus and methods to form contact lenses with aesthetic elements on demand are described. In some examples, the method of defining the aesthetic aspect includes printing patterns. Other examples include photochromic or thermochromic elements which may provide patterning on exposure to electromagnetic irradiation. In some further examples, energized components in contact lenses may provide aesthetic characteristics.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Johnson & Johnson Vision Care, Inc
    Inventors: Frederick A. Flitsch, Randall B. Pugh
  • Patent number: 10849258
    Abstract: Provided is an electronic component package for electromagnetic interference shielding. The electronic component package for electromagnetic interference shielding according to an embodiment of the present invention comprises a substrate where electronic components are mounted, a molding member formed on the substrate and the electronic components, a magnetic layer formed on the molding member, and a conductive layer formed on the magnetic layer. Electromagnetic waves generated from the electronic components embeded in the molding member are absorbed in the magnetic layer to thus prevent or reduce harmful influence on other electronic components mounted in adjacent places. In addition, harmful electromagnetic waves generated from the outside may be shielded due to the conductive layer formed on the magnetic layer, thereby protecting electronic components embeded in the molding member from being influenced by the electromagnetic waves.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 24, 2020
    Assignee: NTRIUM INC.
    Inventors: Se Young Jeong, Ki Su Joo, Ju Young Lee, Jeong Woo Hwang, Jin Ho Yoon
  • Patent number: 10667408
    Abstract: A method of encapsulating and hermetically sealing a printed circuit board of a flex cable includes: positioning a printed circuit board portion of a flex cable into a channel defined in a first mold half of a mold, the printed circuit board portion including a substrate and electronic components mounted on the substrate; mounting a second mold half onto the first mold half to enclose the channel of the first mold half and form a cavity within the mold; and filling the cavity of the mold with an encapsulation material through an inlet opening defined through the mold.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 26, 2020
    Assignee: COVIDIEN LP
    Inventors: Anthony Sgroi, Jr., Patrick Mozdzierz, Stephen Paul, David Valentine, Scott Firth
  • Patent number: 10624214
    Abstract: Readily manufactured structures for sealing or encapsulating devices in system-in-a-package modules, such that the modules are easily assembled, have a low-profile, and are space efficient. One example may provide readily manufactured covers for SIP modules. These modules may be easily assembled by attaching the cover to a top side of a substrate. These SIP modules may have a low-profile, for example when their height is reduced using one or more recesses in a bottom surface of a top of the recess, where the one or more recesses are arranged to accept one or more components. These SIP modules may be made space efficient by placing an edge of a cover near an edge of the substrate and connecting the plating of the cover using side plating on, or vias through, the substrate.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 14, 2020
    Assignee: Apple Inc.
    Inventors: Amir Salehi, Takayoshi Katahira, Vu T. Vo, Wyeman Chen, Chang Liu, Dennis R. Pyper, Steven Patrick Cardinali, Lan Hoang, Siddharth Nangia, Meng Chi Lee
  • Patent number: 10600715
    Abstract: A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, and electrically connecting the integrated circuit chip to the embedded conductor.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Young Hoon Kwark
  • Patent number: 10470310
    Abstract: An electronic component includes a first functional element including a pair of first connecting electrode portions formed on a first mounting surface, a pair of pillar electrodes connected to the corresponding first connecting electrode portions, a second functional element that includes a pair of second connecting electrode portions formed on a second mounting surface and that is arranged in a space defined by the first mounting surface of the first functional element and the pair of pillar electrodes, a pair of pad electrodes connected to the corresponding second connecting electrode portions, and a sealing resin that seals the pair of pillar electrodes, the pair of pad electrodes and the second functional element so as to expose the first lower surfaces of the pair of pillar electrodes and the second lower surfaces of the pair of pad electrodes.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 5, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 10466506
    Abstract: Designs, apparatus and methods to form contact lenses with aesthetic elements on demand are described. In some examples, the method of defining the aesthetic aspect includes printing patterns. Other examples include photochromic or thermochromic elements which may provide patterning on exposure to electromagnetic irradiation. In some further examples, energized components in contact lenses may provide aesthetic characteristics.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 5, 2019
    Assignee: Johnson & Johnson Vision Care, Inc.
    Inventors: Frederick A. Flitsch, Randall B. Pugh
  • Patent number: 10453704
    Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chia Y. Poo, Low Siu Waf, Boon Suan Jeung, Eng M. Koon, Chua Swee Kwang
  • Patent number: 10354966
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10283680
    Abstract: An electronic module and method for the production of the electronic module in accordance with some embodiments of the invention are disclosed. The electronic module includes at least one electronic component affixed to a conductive layer by means of sticky electrically insulating layer, where the electronic component is embedded in a transparent foil. The electronic module is produces by providing an electrically conductive layer. At least one electronic component is affixed to the electrically conductive layer by means of a sticky electrically insulating layer and embedded in a transparent foil. The at least one electronic component is electronically contacted with the conductive layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 7, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gregor Langer, Johannes Stahr
  • Patent number: 10162395
    Abstract: The description relates to devices, such as computing devices. One example can include a sandwich structured composite housing. The example can also include a set of electronic components positioned over the sandwich structured composite housing. The set of electronic components can have a profile against the sandwich structured composite housing. The sandwich structured composite housing can have a corresponding negative profile.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 25, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kurt A. Jenkins, Edward Burress, Jaya Narain, Robert J. Bergeson, Andrew W. Hill, Taylor Stellman
  • Patent number: 10120423
    Abstract: Described herein are unibody thermal enclosures for electronic devices. In some instances, the enclosure is a unibody structure formed by injecting a structural material into the tool suspending thermal absorbing/spreading material and thermal insulating material within a cavity of the tool. In other instances, the thermal absorbing/spreading material may be exposed to circuitry of the electronic device and the thermal insulating material may be exposed to the exterior of the electronic device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Bradley David Urban, Troy Hulick, Shelomon Patrick Doblack, Robert Olson, Albert John Yu Sam Chua, Daniel Jones, Adam Kenneth Cybart, Gaurav Soni, William James Carter-Giannini, Matthew Michael Seflic
  • Patent number: 9824948
    Abstract: A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 21, 2017
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Erick Merle Spory
  • Patent number: 9820413
    Abstract: As a thermal conductive material having fluidity is applied on a base plate, probability of a decrease in thermal conductive performance, i.e., probability of a decrease in a heat radiation property caused by a human work, can be suppressed in comparison with the case in which a heat transfer sheet is installed. When the thermal conductive material having fluidity is used, thermal conductive performance is obtained by applying the thermal conductive material is applied and thus reliability is improved. In addition, as stepped sections are formed at sidewalls of circumferential edges of protrusion surfaces on which the thermal conductive material is applied, even when the thermal conductive material having fluidity sticks out of the protrusion surfaces, since the thermal conductive material is accommodated in the stepped sections, the thermal conductive material is suppressed from sticking to another electronic component or the like to improve reliability.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 14, 2017
    Assignee: TDK CORPORATION
    Inventor: Akira Ikezawa
  • Patent number: 9691746
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 9392730
    Abstract: An electronic device having one or more components that generate heat during operation includes a structure for temperature management and heat dissipation. The structure for temperature management and heat dissipation comprises a heat transfer substrate having a surface that is in thermal communication with the ambient environment and a temperature management material in physical contact with at least a portion of the one or more components of the electronic device and at least a portion of the heat transfer substrate. The temperature management material comprises a polymeric phase change material having a latent heat of at least 5 Joules per gram and a transition temperature between 0° C. and 100° C., and a thermal conductive filler.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 12, 2016
    Assignee: OUTLAST TECHNOLOGIES, LLC
    Inventors: Mark Hartmann, Greg Roda
  • Patent number: 9362660
    Abstract: An implantable medical device connector assembly and method of manufacture include a molded, insulative shell having an inner surface forming a connector bore, a circuit member including one or more traces extending through apertures in the connector shell. One or more conductive members, positioned along the connector bore, are electrically coupled to the traces. The sealing members are positioned between the conductive members.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 7, 2016
    Assignee: Medtronic, Inc.
    Inventors: Andrew J Ries, Jeffrey A Swanson, George A Patras
  • Patent number: 9332646
    Abstract: An electronic package module includes a circuit board having a supporting surface, at least one first electronic component, at least one second electronic component, and at least one molding compound. The first and second electronic components are mounted on the supporting surface. The molding compound is disposed on the supporting surface and covers the supporting surface partially. The molding compound encapsulates the first electronic component yet not the second electronic component.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: May 3, 2016
    Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Jen-Chun Chen, Hsin-Chin Chang
  • Patent number: 9317079
    Abstract: A media device, which may take the form of a set top box (STB), includes a housing or chassis that incorporates an interface panel having selectively configured regions that cooperate with components mounted on a printed circuit board. The selectively configured regions of the interface panel may advantageously provide desired clearance or contact between the interface panel and one or more of the components. In addition, the selectively configured regions of the interface panel may be arranged to provide structural support to a top panel of the chassis while providing specific heat transfer pathways between the components and the chassis. In this manner, the interface panel may be controllably designed with a desired thermal mass and/or a desired thermal conductivity in specific regions of the interface panel by varying properties of the interface panel which may include, but are not limited to, the panel thickness and material.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 19, 2016
    Assignee: EchoStar UK Holdings Limited
    Inventor: David Robert Burton
  • Patent number: 9295157
    Abstract: Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. Locations of where the racetrack can be adjusted (for example, narrowed) and/or removed without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, a portion of the racetrack can be removed to create a break and/or a portion of the racetrack can be narrowed in a selected area.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 22, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read, Hoang Mong Nguyen, Anthony James LoBianco, Guohao Zhang, Dinhphuoc Vu Hoang
  • Patent number: 9287478
    Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 15, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 9266267
    Abstract: A method for manufacturing a sensor in which a sensor element, which comprises at least a first housing, is at least partially encapsulation-molded in an encapsulation-molding process. As a result of the encapsulation-molding process a sensor housing is formed. The sensor element is mechanically connected to a support element and/or accommodated by the support element, after which the sensor element and the support element are encapsulation-molded in a common encapsulation-molding process for forming the sensor housing.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 23, 2016
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Edmond De Volder, Dietmar Huber, Andreas Doering, Jakob Schillinger, Martin Watzlawik, Lothar Biebricher
  • Patent number: 9257394
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 9, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kuang-Neng Chung, Hsin-Lung Chung, Tien-Chung Huang, Tsung-Hsien Hsu
  • Patent number: 9252032
    Abstract: A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, WonJun Ko, JaEun Yun
  • Patent number: 9197026
    Abstract: Disclosed is a printed circuit board assembly PBA on which a connector for electrical connection to an external connection element is mounted. Such an assembly may be formed with a molding method of a PBA which includes applying a polymer resin to the PBA to mold the PBA in order to offer stiffness thereto. The foregoing method of molding the PBA according to the present disclosure is a molding method of a PBA including a PCB and a connector mounted on the PCB to electrically connect the same to an external connection element. The method includes combining the connector with a connector cover, applying a resin to the PBA combined with the connector cover to execute molding of the PBA, and separating the connector cover from the molded PBA to expose the electrode terminal for an external connection element.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Tae Kim, Tae Sang Park, Young Jun Moon, Soon Min Hong
  • Patent number: 9177837
    Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 3, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 9171969
    Abstract: A mounting member includes: an insulating substrate, a first die pad unit, first and second terminals. The insulating substrate has a rectangular first surface, a second surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A through hole is provided from the first surface to the second surface. The first die pad unit is provided on the first surface. The first terminal has a conductive region covering the first side surface, the first surface, and the second surface. The second terminal has a conductive region covering the second side surface and the second surface, connected to the first die pad unit by conductive material provided in the through hole or on a side wall of the through hole. The first die pad unit, the first terminal, and the second terminal are apart from one another.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mami Yamamoto, Yoshio Noguchi
  • Patent number: 9165907
    Abstract: In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 20, 2015
    Assignee: Interposers GMBH
    Inventors: Andreas Jakob, Thomas Kaiser
  • Patent number: 9155233
    Abstract: An electromagnetic shield is provided, for example for a printed circuit board. A shield lid fits onto a base structure having at least two, more typically four, opposing sidewalls. The lid includes a top portion and a lip extending downward from the top portion to cap the base structure. The lid includes at least one deformation inhibiting feature extending downward from the top portion, for placement near or against an interior portion of a sidewall, for example against an edge of a folded-over sidewall. The deformation inhibiting feature may include one or more half-dimples stamped into the lid. In response to an external force, the deformation inhibiting feature presses against its adjacent sidewall in order to brace the shield lid. This inhibits the base structure from deforming the lip due to outward pressure of a sidewall onto a portion of the lip, located opposite the deformation inhibiting feature.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Sierra Wireless, Inc.
    Inventors: Bruce Richard John Samuels, Edwin Sy Liu
  • Patent number: 9155204
    Abstract: A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Tomoyuki Aoki
  • Patent number: 9105806
    Abstract: A GaN based light emitting diode device which emits polarized light or light of various degrees of polarization for use in the creation of optical devices. The die are cut to different shapes, or contain some indicia that are used to represent the configuration of the weak dipole plane and the strong dipole plane. This allows for the more efficient manufacturing of such light emitting diode based optical devices.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 11, 2015
    Assignees: SORAA, INC., KAAI, INC.
    Inventors: Rajat Sharma, Eric M. Hall
  • Patent number: 9091609
    Abstract: A protective casing for a household appliance includes an encapsulation and a support fitted therein. The support has an upper recess for the sensor, also housing a cushion with a central hole, and an electrical connector; and the encapsulation with a horizontal structural portion, from which a mechanical engagement, a bed and a connection project. The bed is generally cylindrical, with a flat top with a central hole and an octagonal side surface with alternate round and flat walls, the internal surface delimited by the walls has a similar and/or cooperative geometry with the side surface of the support. Particularly, a bottom surface, the cushion and top of the bed define an open chamber, housing the sensor. The chamber being in fluid communication with the source of the pressure to be measured through the lumen of the connector and the central hole as included on the top of the bed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 28, 2015
    Assignee: EMICOL ELETRO ELECTRONICA S.A.
    Inventor: José Claudio Micai
  • Patent number: 9087924
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: July 21, 2015
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 9054086
    Abstract: A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: June 9, 2015
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Douglas Dean Lopata, John David Weld, Mathew A. Wilkowski
  • Publication number: 20150136451
    Abstract: There is provided an electronic component module including: a substrate on which an electronic component is mounted; at least one insulating member coupled to the substrate and having a surface on which a plating layer is formed; and a molded portion covering the electronic component and the at least one insulating member, wherein the insulating member is bonded to the substrate and a metal layer is formed on a bonding surface between the substrate and the insulating member.
    Type: Application
    Filed: May 2, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Woo PARK, Do Jae YOO, Tae Hyun KIM
  • Publication number: 20150138776
    Abstract: A multiple-ply solid state light fixture is disclosed. A panelized, solid state light fixture includes combined layers of material chemically bonded together without a traditional mechanical housing and with relatively few or no fasteners. In example embodiments, the solid state light fixture includes an LED mounting substrate, a thermal material on a non-LED side of the LED mounting substrate, and an optical material on the LED side of the LED mounting substrate. A plurality of LEDs are disposed or mounted, with or without additional packaging, on the LED side of the LED mounting substrate. A chemical bond is created between the substrate and the other layers. This chemical bond can be created, for example, through use of applied fluid or gelatinous compounds that are then solidified, or through the use of adhesives.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Cree, Inc.
    Inventor: James Michael Lay
  • Publication number: 20150131231
    Abstract: There are provided an electronic component module allowing for a circuit wiring to be disposed outside of a molded part by a plating process, and a manufacturing method thereof, the electronic component module including a substrate; at least one electronic component mounted on the substrate; a molded part sealing the electronic component; a plurality of conductive connectors having one ends bonded to the substrate or one surface of the electronic component and formed in the molded part to penetrate through the molded part; and at least one plane pattern formed on an outer surface of the molded part and electrically connected to at least one of the conductive connectors.
    Type: Application
    Filed: May 1, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Jae YOO, Jong In Ryu, Eun Jung Jo, Jae Hyun Lim, Kyu Hwan Oh
  • Publication number: 20150131230
    Abstract: A module IC package structure for increasing heat-dissipating efficiency includes a substrate unit, an electronic unit, a package unit, a first heat-dissipating unit and a second heat-dissipating unit. The substrate unit includes a circuit substrate. The electronic unit includes a plurality of electronic components disposed on the circuit substrate and electrically connected to the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate for enclosing the electronic components. The first heat-dissipating unit includes a heat-dissipating base layer disposed on the top surface of the package gel body. The second heat-dissipating unit includes a plurality of heat-dissipating auxiliary layers disposed on the top surface of the heat-dissipating base layer. Whereby, the heat-dissipating efficiency of the module IC package structure can be increased by matching the heat-dissipating base layer and the heat-dissipating auxiliary layers.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: AZUREWAVE TECHNOLOGIES, INC.
    Inventor: HUANG-CHAN CHIEN
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado