With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
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Patent number: 12193162Abstract: A module includes: a substrate having a first surface; a first component mounted on the first surface; a resin film that covers the first component along a shape of the first component, and also covers a part of the first surface; a conductor film that covers at least a part of the resin film along the shape of the first component, and covers at least a part of a portion in which the resin film covers the part of the first surface; and a conductor structure disposed to extend over a part of the resin film. The conductor structure includes a first end portion, a second end portion, and an intermediate portion. The first end portion and the second end portion are connected to the first surface. The intermediate portion is in contact with the conductor film.Type: GrantFiled: December 12, 2022Date of Patent: January 7, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshihito Otsubo, Ryoichi Kita
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Patent number: 12185467Abstract: An electronic device includes a component mounting portion, an electronic component disposed on the component mounting portion, a solder between the component mounting portion and the electronic component, a mounting base member, and a supporting beam connecting the component mounting portion and the mounting base member. The supporting beam has a plurality of bent portions. The supporting beam includes a frame, an outer supporting portion connecting the frame and the mounting base member, and an inner supporting portion connecting the frame and the component mounting portion. The inner supporting portion is shifted from the outer supporting portion along the frame. One of the plurality of bent portions is a connecting portion between the frame and the outer supporting portion. Another of the plurality of bent portions is a connecting portion between the frame and the inner supporting portion.Type: GrantFiled: July 18, 2022Date of Patent: December 31, 2024Assignee: DENSO CORPORATIONInventors: Keitaro Ito, Teruhisa Akashi, Hirofumi Funabashi
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Patent number: 12165487Abstract: A wearable locator system includes a washable information beacon, which includes a microprocessor, a rechargeable battery, a wireless power supply, a GPS circuit, a wireless transceiver, and a memory. The washable information beacon is housed in a protective shell that allows for complete watertight encapsulation and thermal insulation thereby protecting the washable information beacon during wear, washing, high-heat drying, and high-heat ironing without impairing a transmission of electromagnetic waves between the washable information beacon and an external reader. The protective shell is formed from a low pressure molding process. The wearable locator system further includes a fabric material having the washable information beacon semi-permanently affixed thereto.Type: GrantFiled: January 27, 2023Date of Patent: December 10, 2024Inventor: Kiyeon Nam
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Patent number: 12159811Abstract: A microelectronic device package may include one or more semiconductor dice coupled to a substrate. The microelectronic device package may further include a lid coupled to the substrate, the lid defining a volume over and around the one or more semiconductor die. The microelectronic device package may further include a thermally conductive dielectric filler material substantially filling the volume defined around the semiconductor die.Type: GrantFiled: May 27, 2022Date of Patent: December 3, 2024Assignee: Micron Technology, Inc.Inventor: Xiaopeng Qu
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Patent number: 12156356Abstract: Methods, devices, and systems are provided for the encapsulation of electronic devices. The encapsulation includes positioning an electronic device in a cavity of a mold, and screen or stencil printing an encapsulant, in a liquid form, around the flexible electronic device. The mold is of a sufficient thickness to allow the encapsulant to completely cover electronic components mounted on a first surface of the electronic device.Type: GrantFiled: April 13, 2021Date of Patent: November 26, 2024Assignee: Flex Ltd.Inventors: Weifeng Liu, Jesus A. Tan, William L. Uy, Dongkai Shangguan
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Patent number: 12156346Abstract: This application provides a circuit board, an electronic device, and a production method for a circuit board. The circuit board includes: a board body; an electronic component, welded to a surface of the board body by using soldering tin; and a reaction particle, disposed on the surface of the board body and adjacent to a weld leg for welding the electronic component. When the circuit board is energized and in an environment with water, the reaction particle reacts with the weld leg to form an insoluble protection layer on an outer surface of the weld leg, and the insoluble protection layer isolates the weld leg from water to prevent dendrite corrosion of the weld leg.Type: GrantFiled: April 27, 2022Date of Patent: November 26, 2024Assignee: Honor Device Co., Ltd.Inventor: Leiwen Gao
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Patent number: 12154709Abstract: A surface-mount passive component includes a passive element and a size conversion unit on which the passive element is mounted. The size conversion unit has a body, a plurality of first external terminals each of which is exposed on an element mount surface of the body and is electrically connected to a corresponding one of passive element external terminals of the passive element, a plurality of second external terminals exposed on a board-side mount surface of the body, and connection wires that electrically connect the first external terminals and the second external terminals. An area of the board-side mount surface is larger than an area of a first main surface of the passive element, and a total area of the plurality of second external terminals on the board-side mount surface is larger than a total area of the passive element external terminals on the first main surface.Type: GrantFiled: June 17, 2021Date of Patent: November 26, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Yoshimasa Yoshioka, Tatsuya Funaki, Shunsuke Abe
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Patent number: 12142332Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.Type: GrantFiled: September 7, 2022Date of Patent: November 12, 2024Assignee: Micron Technology, Inc.Inventors: Chunqiang Weng, Jingwei Cheng
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Patent number: 12135250Abstract: A piezoelectric sensor, comprising: a stress applying layer in which a plurality of stress applying grooves extending in parallel with a first direction are formed in a predetermined region on a whole surface; and a piezoelectric layer that is layered on the stress applying layer and formed from a polymer piezoelectric material containing an optical active polymer.Type: GrantFiled: March 9, 2022Date of Patent: November 5, 2024Assignee: Japan Display Inc.Inventor: Hiroumi Kinjo
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Patent number: 12127335Abstract: An electronic device is provided. The electronic device includes a carrier, a first electronic component, a second electronic component, and an encapsulant. The first electronic component is disposed at a first side of the carrier. The second electronic component is disposed at a second side of the carrier opposite to the first side. The encapsulant encapsulates the first electronic component and has an uneven thickness. The encapsulant is configured to reduce a warpage of the carrier.Type: GrantFiled: February 24, 2022Date of Patent: October 22, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Jhen Ciou, Jenchun Chen, Chang-Fu Lu, Pai-Sheng Shih
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Patent number: 12125753Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.Type: GrantFiled: January 26, 2022Date of Patent: October 22, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Taehyeong Kim, Hyeongmun Kang, Seungduk Baek
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Patent number: 12124905Abstract: In some examples, a transaction instrument includes a body that defines a first face and a second face, a chip assembly comprising an integrated circuit chip, an aperture in a portion of the body that provides access to a portion of the transaction instrument, and an attachment mechanism configured to secure the chip assembly at least partially within the body and hold the chip assembly substantially flush with the first face of the body. At least one of the body, the attachment mechanism, or a portion of the chip assembly is designed to fail in response to a force applied via the aperture in the body, and wherein the failure of the at least one of the body, the attachment mechanism, or the portion of the chip assembly, destroys the integrated circuit chip of the transaction instrument.Type: GrantFiled: December 17, 2021Date of Patent: October 22, 2024Assignee: Wells Fargo Bank, N.A.Inventors: Kristine Ing Kushner, John T. Wright
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Patent number: 12100630Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.Type: GrantFiled: November 13, 2020Date of Patent: September 24, 2024Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Marvin Marbell, Melvin Nava, Jeremy Fisher, Alexander Komposch
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Patent number: 12046535Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.Type: GrantFiled: October 20, 2022Date of Patent: July 23, 2024Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 12031949Abstract: A fluidic device and a method of preventing isolation material from bleed-out therein is described herein. The fluidic device includes a bulk acoustic wave resonator structure defining at least one surface area region on which a functionalization material is disposed and the resonator structure includes a repelling area. The fluidic device also includes isolation material disposed on the resonator structure and away from the at least one surface area region. The repelling area is configured to prevent the isolation material from extending into the at least one surface area region. Further, an electronic board may be operably attached to the resonator structure and the isolation material may be disposed in a gap therebetween to electrically isolate electrical contacts and form a fluidic channel.Type: GrantFiled: June 29, 2020Date of Patent: July 9, 2024Assignee: Qorvo US, Inc.Inventors: Buu Quoc Diep, John Belsick, Matthew Wasilik, Rio Rivas, Bang Nguyen, Derya Deniz
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Patent number: 12008202Abstract: A touch light-emitting module and a manufacturing method thereof are disclosed. The touch light-emitting module includes a printed circuit board and a touch-control conductor. The printed circuit board has a top surface on which a touch-control IC and a luminous unit that is electrically connected are disposed. The touch-control conductor includes a hollowed portion. The touch-control conductor is coated, on the bottom thereof, with a conductive material to combine with the top surface of the printed circuit board, so that the touch-control IC and the luminous unit are located in the hollowed portion. An encapsulation resin is then injected into a space between the printed circuit board and the hollowed portion to complete encapsulation. As such, the present invention offers a simplified structure to achieve an effect of minimization, and also simplifies the manufacturing process and reduces the working time to thereby enhance the yield.Type: GrantFiled: May 11, 2023Date of Patent: June 11, 2024Assignee: LIGITEK ELECTRONICS CO., LTD.Inventors: Yi-Wen Chen, Wen-Chung Chou, I-Hsin Tung
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Patent number: 12006434Abstract: Photocurable compositions and methods of preparation and use of such compositions. More particularly, photocurable compositions useful for forming topographical features on surfaces such as membrane surfaces. Methods of forming topographical features on a membrane surface using photocurable compositions.Type: GrantFiled: September 28, 2020Date of Patent: June 11, 2024Assignee: Henkel AG & Co. KGaAInventors: Michael Izzo, Ivan Johnson, Shuhua Jin
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Patent number: 12004294Abstract: A method of manufacturing a base plate includes the following steps: providing a first substrate, the first substrate including a first base layer, a first copper coating and a second copper coating covered on two sides of the first base layer; opening at least one first hole on the first substrate, the first hole penetrating the first base layer and the first copper; forming a first electroplated coating on the first copper coating, the first copper coating filling the first hole to form a first connecting portion; opening at least one second hole on the first connecting portion and the first electroplated coating to form a plurality of second connecting pins.Type: GrantFiled: May 31, 2022Date of Patent: June 4, 2024Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.Inventor: Zhi Guo
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Patent number: 11991836Abstract: An electrical device, comprising a softening polymer layer, an electrode layer on a surface of the softening polymer layer and a cover polymer layer on the surface of the softening polymer layer. An opening in the polymer cover layer is filled with a reflowed solder, one end of the reflowed solder, located inside the opening, contacts a contact pad site portion of the electrode layer, and another end of the reflowed solder contacts an electrical connector electrode of the device.Type: GrantFiled: January 26, 2023Date of Patent: May 21, 2024Assignee: Board of Regents, The University of Texas SystemInventors: Romil Modi, Jonathan Reeder, Gregory T. Ellson, Walter E. Voit, Alexandra Joshi Imre
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Patent number: 11978700Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.Type: GrantFiled: July 25, 2022Date of Patent: May 7, 2024Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 11935864Abstract: A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a).Type: GrantFiled: October 24, 2022Date of Patent: March 19, 2024Assignee: Kulicke and Soffa Industries, Inc.Inventors: Hui Xu, JeongHo Yang, Wei Qin, Ziauddin Ahmad
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Patent number: 11869996Abstract: A product and a process for encapsulating solar cells in a module using transparent plastics and an optically coupling fluid. A photovoltaic window device of a construction that enables generation of electric power while simultaneously affording transparency.Type: GrantFiled: March 1, 2021Date of Patent: January 9, 2024Assignee: STELLARIS CORPORATIONInventor: James B. Paull
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Patent number: 11869825Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.Type: GrantFiled: October 20, 2022Date of Patent: January 9, 2024Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 11856696Abstract: An electronic device is provided that includes a first circuit board including a first electronic component and a second electronic component disposed on a side of the first circuit board, a second circuit board spaced apart from the first circuit board and having a side facing the side of the first circuit board on which the first electronic component and the second electronic component are disposed, a first interposer disposed between the first circuit board and the second circuit board to form an inner space between the first circuit board and the second circuit board, and a second interposer disposed between the first circuit board and the second circuit board to divide the inner space into a first region and a second region, and wherein the first interposer and the second interposer electrically connect the first circuit board to the second circuit board.Type: GrantFiled: April 25, 2022Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sangwon Ha, Seyoung Jang, Sungjin Kim, Sanghoon Park, Kyungho Lee, Younoh Chi
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Patent number: 11856702Abstract: The present disclosure provides an adapter board, a for manufacturing the same and a circuit board assembly. The adapter board includes a board body, a first component buried in the board body, a first connector located on a first surface of the board body and configured to be connected with a circuit board and a second component, a second connector located on a second surface of the board body and configured to be connected with a second component, a first conductive body and a second conductive body buried in the board body. One end of the first conductive body is connected with the first component. The other end of the first conductive body is connected with the first connector. One end of the second conductive body is connected with the first component. The other end of the second conductive body is connected with the second connector.Type: GrantFiled: September 1, 2021Date of Patent: December 26, 2023Assignee: SHENNAN CIRCUITS CO., LTD.Inventors: Lixiang Huang, Hua Miao
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Patent number: 11842944Abstract: An integrated circuit (IC) assembly comprising an IC die and a frame material that has been dispensed over the assembly substrate to be further adjacent to a perimeter edge of the IC die. The frame material may be selected to have flow properties that minimize slump, for example so a profile of a transverse cross-section through the frame material may retain convex curvature. The frame material may be cured following dispense, and upon application of a thermal interface material (TIM), the frame material may and act as a barrier, impeding flow of the TIM. The frame material may be compressed by force applied through an external thermal solution, such as a heat sink, to ensure good contact to the TIM.Type: GrantFiled: December 26, 2019Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Kyle Arrington, Frederick Atadana, Taylor Gaines, Minseok Ha
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Patent number: 11837588Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.Type: GrantFiled: November 1, 2022Date of Patent: December 5, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Milind S. Bhagavat, Rahul Agarwal
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Patent number: 11825599Abstract: The present invention relates to an electrical device including a printed circuit board (PCB) accommodated in a case, and more particularly, to an air-pocket prevention PCB, an air-pocket prevention PCB module, an electrical device including the same, and a manufacturing method of an electrical device including the same with improved fluidity of a resin material so that air pockets that may occur when the case is filled with the resin material are easily discharged and the resin material may be evenly filled inside the case.Type: GrantFiled: October 13, 2021Date of Patent: November 21, 2023Assignee: SOLUM CO., LTD.Inventors: Jun Kyu Lee, Jeong Man Han, Su Young Kim, Yong Woo Kang, Sang Keun Ji, Dong Kyun Ryu
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Patent number: 11817418Abstract: A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant.Type: GrantFiled: November 24, 2020Date of Patent: November 14, 2023Assignee: Infineon Technologies AGInventors: Wei Lee Lim, Run Hong Toh, Peng Liang Yeap
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Patent number: 11785325Abstract: A camera module and an electronic device having the same, and a method for manufacturing the camera module, wherein the fixed-focus camera module comprises a circuit board; a photosensitive element, which is conductively connected to the circuit board; a molded base, wherein the molded base is integrally molded on the circuit board and the photosensitive element, and the molded base forms a light window, so as to provide a light passage for the photosensitive chip through the light window; and an optical lens, wherein the optical lens is supported on the molded base and corresponds to the light window formed by the molded base, wherein the circuit board comprises a circuit board substrate and at least one electronic component, wherein the at least one electronic component is electrically connected to the circuit board substrate, wherein the circuit board substrate has a blank side, and wherein the blank side of the circuit board substrate is free of the at least one electronic component.Type: GrantFiled: August 3, 2018Date of Patent: October 10, 2023Assignee: NINGBO SUNNY OPOTECH CO., LTD.Inventors: Mingzhu Wang, Bojie Zhao, Zhewen Mei, Nan Guo, Lifeng Yao, Zhenyu Chen
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Patent number: 11778740Abstract: An improved memory module structure includes a printed circuit board, memory units disposed on the printed circuit board, and a connection interface disposed on the printed circuit board for connection with an electronic device. The printed circuit board includes a solder pad zone having solder pads electrically connected with the memory units and the connection interface. A conduction element is combined with the solder pad zone or at least one conductor line electrically connected, in the form of bridge connection, the solder pads, in order to have the solder pads electrically connected. A memory module modification method is also provided, including removing a register from an existing dual inline memory module to expose a solder pad zone, and disposing of a conduction element or arranging a conductor line to have the memory units and the connection interface of electrically connected to thereby form an improved memory module structure.Type: GrantFiled: September 15, 2021Date of Patent: October 3, 2023Inventor: Shih-Hsiung Lien
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Patent number: 11744021Abstract: In one embodiment, an electronic assembly can include: a first electronic device package configured to be mounted on and electrically connected with a system substrate; a second electronic device package electrically connected to the system substrate; and an electrical pathway configured to extend from the system substrate through the first electronic device package and connected to an input terminal of the second electronic device package, the electrical pathway bypassing processing circuitry of the first electronic device package.Type: GrantFiled: January 21, 2022Date of Patent: August 29, 2023Assignee: Analog Devices, Inc.Inventor: Hien Minh Pham
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Patent number: 11742259Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.Type: GrantFiled: June 21, 2021Date of Patent: August 29, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Manish Arora, Nuwan Jayasena
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Patent number: 11706905Abstract: A module includes a substrate, which has a polygonal shape in a plan view, an electronic component and an electronic component, which are mounted on a main surface of the substrate, and side electrodes, which are provided on at least two side surfaces of a plurality of side surfaces that form the polygonal shape of the substrate. A conductor film coupled to the electronic component and a conductor film coupled to the electronic component are provided on the substrate. The conductor film extends to reach a side surface of the at least two side surfaces to be coupled to a side electrode provided on the side surface. The conductor film extends to reach a side surface of the at least two side surfaces, which is different from the side surface, to be coupled to a side electrode provided on the side surface.Type: GrantFiled: January 19, 2021Date of Patent: July 18, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Koji Furutani
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Patent number: 11705541Abstract: A light-emitting device includes a mounting substrate having a first surface and a second surface opposite to the first surface, the mounting substrate having a first end portion at an end of the mounting substrate; light-emitting elements mounted on the first surface of the mounting substrate other than the first end portion; first terminals provided on the first surface at the first end portion of the mounting substrate and connected to the light-emitting elements; and second terminals provided on the second surface at the first end portion of the mounting substrate and connected to the light-emitting elements.Type: GrantFiled: April 21, 2020Date of Patent: July 18, 2023Assignee: NICHIA CORPORATIONInventor: Kimihiro Miyamoto
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Patent number: 11694984Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.Type: GrantFiled: August 30, 2019Date of Patent: July 4, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Wen-Long Lu
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Patent number: 11689790Abstract: An image capture device that includes a housing and a heatsink located partially or completely within the housing. The heatsink comprises a planar surface, a printed circuit board in communication with the heatsink, and a sheet conductor that is a graphite sheet connected to the planar surface of the heatsink and in direct contact with the printed circuit board or components of the printed circuit board.Type: GrantFiled: July 19, 2021Date of Patent: June 27, 2023Assignee: GoPro, Inc.Inventors: Nicholas Vitale, Raul Vargas Gonzalez, Herman Wong
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Patent number: 11688659Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.Type: GrantFiled: August 25, 2020Date of Patent: June 27, 2023Assignee: KIOXIA CORPORATIONInventor: Yoshiaki Goto
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Patent number: 11673302Abstract: A mold for encapsulating a Pin-Fin type power module with resin is disclosed. The power module includes a DBC or IMS, power chips and multiple terminals provided on a first surface of the DBC or IMS and a Pin-Fin structure provided on a second surface of the DBC or IMS. The mold further includes: a cavity for containing the power module; multiple terminal protecting elements corresponding to the terminals, respectively, each for receiving at least a part of a terminal; and an injection hole provided on the bottom of the mold or on the side wall of the mold, The first surface faces the bottom of the mold and the injection hole is below the first surface when the power module is placed in the cavity. A method for manufacturing a power module is also provided.Type: GrantFiled: July 14, 2021Date of Patent: June 13, 2023Assignee: ZF FRIEDRICHSHAFEN AGInventor: Wei Liu
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Patent number: 11664286Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Patent number: 11658130Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.Type: GrantFiled: December 31, 2020Date of Patent: May 23, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tianyi Luo, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Osvaldo Jorge Lopez, Lance Cole Wright
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Patent number: 11658099Abstract: Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.Type: GrantFiled: December 7, 2020Date of Patent: May 23, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventor: Marc Alan Mangrum
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Patent number: 11658046Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.Type: GrantFiled: November 10, 2020Date of Patent: May 23, 2023Assignee: Powertech Technology Inc.Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ting-Yeh Wu
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Patent number: 11652273Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.Type: GrantFiled: February 18, 2022Date of Patent: May 16, 2023Assignee: MediaTek Inc.Inventors: Nai-Wei Liu, Yen-Yao Chi, Yeh-Chun Kao, Shih-Huang Yeh, Tzu-Hung Lin, Wen-Sung Hsu
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Patent number: 11637544Abstract: A crystal oscillator (101) includes: a piezoelectric resonator plate (2) on which a first excitation electrode and a second excitation electrode are formed; a first sealing member (3) covering the first excitation electrode of the piezoelectric resonator plate (2); a second sealing member (4) covering the second excitation electrode of the piezoelectric resonator plate (2); and an internal space (13) formed by bonding the first sealing member (3) to the piezoelectric resonator plate (2) and by bonding the second sealing member (4) to the piezoelectric resonator plate (2), so as to hermetically seal a vibrating part including the first excitation electrode and the second excitation electrode of the piezoelectric resonator plate (2). An electrode pattern (371) including a mounting pad for wire bonding is formed on an outer surface (first main surface (311)) of the first sealing member (3).Type: GrantFiled: November 21, 2017Date of Patent: April 25, 2023Assignee: Daishinku CorporationInventor: Takuya Kojo
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Patent number: 11631528Abstract: The inductor includes a coil including a winding portion formed by winding a conductor wire having an insulating coating and lead-out portions extended from the winding portion, and a body made of a magnetic portion including magnetic powder and resin, and containing the coil, and outer electrodes on a body surface. The body includes a mounting surface, an upper surface opposite the mounting surface, a pair of opposing end surfaces adjacent to the mounting and upper surfaces, and a pair of opposing side surfaces adjacent to the mounting surface, the upper surface, and the end surfaces. End portions of the lead-out portions respectively have a flat portion exposed from the body surface, a covered portion adjacent to the flat portion at at least one of the end portions covered with the magnetic portion, and the flat portion is electrically connected to the outer electrode.Type: GrantFiled: January 29, 2020Date of Patent: April 18, 2023Assignee: Murata Manufacturing Co., Ltd.Inventor: Yuki Kitashima
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Patent number: 11627661Abstract: A method for producing a wired circuit board, the method including the steps of: a first step of providing an insulating layer having an opening penetrating in the thickness direction at one side surface in the thickness direction of the metal plate, a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, a third step of providing a second barrier layer continuously at one side in the thickness direction of the first barrier layer and an inner surface of the insulating layer facing the opening, a fourth step of providing a conductor layer so as to contact the second barrier layer, and a fifth step of removing the metal plate by etching.Type: GrantFiled: June 3, 2021Date of Patent: April 11, 2023Assignee: NITTO DENKO CORPORATIONInventors: Shusaku Shibata, Hayato Takakura, Masaki Ito, Yoshihiro Kawamura, Shuichi Wakaki
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Patent number: 11618110Abstract: A solder paste includes a solder powder; and a flux component containing a compound having at least one carboxyl group protected by a trialkylsilyl group.Type: GrantFiled: October 19, 2020Date of Patent: April 4, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naomichi Ohashi, Koso Matsuno, Yasuhiro Okawa
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Patent number: 11617259Abstract: The present invention relates to an embedded printed circuit board including: an insulation substrate including a cavity; a sensor device disposed on the cavity; an insulating layer disposed on the insulation substrate, having an opening part exposing the sensor device; and a pad part disposed on the lower surface of the opening part exposing the sensor device.Type: GrantFiled: January 27, 2021Date of Patent: March 28, 2023Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Mikael Tuominen, Seok Kim Tay
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Patent number: 11557640Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, the second connection pads spaced apart from the first connection pads in a second direction perpendicular to the first direction, and a driving chip disposed on the board between the first connection pads and the second connection pads. Each of the first connection pads includes a first conductive layer disposed on the board, a second conductive layer which entirely overlaps with the first conductive layer in a plan view, is disposed on the first conductive layer and is formed of a different material from that of the first conductive layer, and a third conductive layer entirely overlapping with the second conductive layer and disposed on the second conductive layer.Type: GrantFiled: March 13, 2020Date of Patent: January 17, 2023Assignee: Samsung Display Co., Ltd.Inventor: Joo-Nyung Jang