With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
  • Patent number: 11869825
    Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: January 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11869996
    Abstract: A product and a process for encapsulating solar cells in a module using transparent plastics and an optically coupling fluid. A photovoltaic window device of a construction that enables generation of electric power while simultaneously affording transparency.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: January 9, 2024
    Assignee: STELLARIS CORPORATION
    Inventor: James B. Paull
  • Patent number: 11856702
    Abstract: The present disclosure provides an adapter board, a for manufacturing the same and a circuit board assembly. The adapter board includes a board body, a first component buried in the board body, a first connector located on a first surface of the board body and configured to be connected with a circuit board and a second component, a second connector located on a second surface of the board body and configured to be connected with a second component, a first conductive body and a second conductive body buried in the board body. One end of the first conductive body is connected with the first component. The other end of the first conductive body is connected with the first connector. One end of the second conductive body is connected with the first component. The other end of the second conductive body is connected with the second connector.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: December 26, 2023
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Lixiang Huang, Hua Miao
  • Patent number: 11856696
    Abstract: An electronic device is provided that includes a first circuit board including a first electronic component and a second electronic component disposed on a side of the first circuit board, a second circuit board spaced apart from the first circuit board and having a side facing the side of the first circuit board on which the first electronic component and the second electronic component are disposed, a first interposer disposed between the first circuit board and the second circuit board to form an inner space between the first circuit board and the second circuit board, and a second interposer disposed between the first circuit board and the second circuit board to divide the inner space into a first region and a second region, and wherein the first interposer and the second interposer electrically connect the first circuit board to the second circuit board.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwon Ha, Seyoung Jang, Sungjin Kim, Sanghoon Park, Kyungho Lee, Younoh Chi
  • Patent number: 11842944
    Abstract: An integrated circuit (IC) assembly comprising an IC die and a frame material that has been dispensed over the assembly substrate to be further adjacent to a perimeter edge of the IC die. The frame material may be selected to have flow properties that minimize slump, for example so a profile of a transverse cross-section through the frame material may retain convex curvature. The frame material may be cured following dispense, and upon application of a thermal interface material (TIM), the frame material may and act as a barrier, impeding flow of the TIM. The frame material may be compressed by force applied through an external thermal solution, such as a heat sink, to ensure good contact to the TIM.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Kyle Arrington, Frederick Atadana, Taylor Gaines, Minseok Ha
  • Patent number: 11837588
    Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: December 5, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal
  • Patent number: 11825599
    Abstract: The present invention relates to an electrical device including a printed circuit board (PCB) accommodated in a case, and more particularly, to an air-pocket prevention PCB, an air-pocket prevention PCB module, an electrical device including the same, and a manufacturing method of an electrical device including the same with improved fluidity of a resin material so that air pockets that may occur when the case is filled with the resin material are easily discharged and the resin material may be evenly filled inside the case.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: November 21, 2023
    Assignee: SOLUM CO., LTD.
    Inventors: Jun Kyu Lee, Jeong Man Han, Su Young Kim, Yong Woo Kang, Sang Keun Ji, Dong Kyun Ryu
  • Patent number: 11817418
    Abstract: A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 14, 2023
    Assignee: Infineon Technologies AG
    Inventors: Wei Lee Lim, Run Hong Toh, Peng Liang Yeap
  • Patent number: 11785325
    Abstract: A camera module and an electronic device having the same, and a method for manufacturing the camera module, wherein the fixed-focus camera module comprises a circuit board; a photosensitive element, which is conductively connected to the circuit board; a molded base, wherein the molded base is integrally molded on the circuit board and the photosensitive element, and the molded base forms a light window, so as to provide a light passage for the photosensitive chip through the light window; and an optical lens, wherein the optical lens is supported on the molded base and corresponds to the light window formed by the molded base, wherein the circuit board comprises a circuit board substrate and at least one electronic component, wherein the at least one electronic component is electrically connected to the circuit board substrate, wherein the circuit board substrate has a blank side, and wherein the blank side of the circuit board substrate is free of the at least one electronic component.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: October 10, 2023
    Assignee: NINGBO SUNNY OPOTECH CO., LTD.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhewen Mei, Nan Guo, Lifeng Yao, Zhenyu Chen
  • Patent number: 11778740
    Abstract: An improved memory module structure includes a printed circuit board, memory units disposed on the printed circuit board, and a connection interface disposed on the printed circuit board for connection with an electronic device. The printed circuit board includes a solder pad zone having solder pads electrically connected with the memory units and the connection interface. A conduction element is combined with the solder pad zone or at least one conductor line electrically connected, in the form of bridge connection, the solder pads, in order to have the solder pads electrically connected. A memory module modification method is also provided, including removing a register from an existing dual inline memory module to expose a solder pad zone, and disposing of a conduction element or arranging a conductor line to have the memory units and the connection interface of electrically connected to thereby form an improved memory module structure.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: October 3, 2023
    Inventor: Shih-Hsiung Lien
  • Patent number: 11742259
    Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: August 29, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Manish Arora, Nuwan Jayasena
  • Patent number: 11744021
    Abstract: In one embodiment, an electronic assembly can include: a first electronic device package configured to be mounted on and electrically connected with a system substrate; a second electronic device package electrically connected to the system substrate; and an electrical pathway configured to extend from the system substrate through the first electronic device package and connected to an input terminal of the second electronic device package, the electrical pathway bypassing processing circuitry of the first electronic device package.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 29, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Hien Minh Pham
  • Patent number: 11706905
    Abstract: A module includes a substrate, which has a polygonal shape in a plan view, an electronic component and an electronic component, which are mounted on a main surface of the substrate, and side electrodes, which are provided on at least two side surfaces of a plurality of side surfaces that form the polygonal shape of the substrate. A conductor film coupled to the electronic component and a conductor film coupled to the electronic component are provided on the substrate. The conductor film extends to reach a side surface of the at least two side surfaces to be coupled to a side electrode provided on the side surface. The conductor film extends to reach a side surface of the at least two side surfaces, which is different from the side surface, to be coupled to a side electrode provided on the side surface.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Koji Furutani
  • Patent number: 11705541
    Abstract: A light-emitting device includes a mounting substrate having a first surface and a second surface opposite to the first surface, the mounting substrate having a first end portion at an end of the mounting substrate; light-emitting elements mounted on the first surface of the mounting substrate other than the first end portion; first terminals provided on the first surface at the first end portion of the mounting substrate and connected to the light-emitting elements; and second terminals provided on the second surface at the first end portion of the mounting substrate and connected to the light-emitting elements.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 18, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Kimihiro Miyamoto
  • Patent number: 11694984
    Abstract: A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 4, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11689790
    Abstract: An image capture device that includes a housing and a heatsink located partially or completely within the housing. The heatsink comprises a planar surface, a printed circuit board in communication with the heatsink, and a sheet conductor that is a graphite sheet connected to the planar surface of the heatsink and in direct contact with the printed circuit board or components of the printed circuit board.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: June 27, 2023
    Assignee: GoPro, Inc.
    Inventors: Nicholas Vitale, Raul Vargas Gonzalez, Herman Wong
  • Patent number: 11688659
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: June 27, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshiaki Goto
  • Patent number: 11673302
    Abstract: A mold for encapsulating a Pin-Fin type power module with resin is disclosed. The power module includes a DBC or IMS, power chips and multiple terminals provided on a first surface of the DBC or IMS and a Pin-Fin structure provided on a second surface of the DBC or IMS. The mold further includes: a cavity for containing the power module; multiple terminal protecting elements corresponding to the terminals, respectively, each for receiving at least a part of a terminal; and an injection hole provided on the bottom of the mold or on the side wall of the mold, The first surface faces the bottom of the mold and the injection hole is below the first surface when the power module is placed in the cavity. A method for manufacturing a power module is also provided.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: June 13, 2023
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Wei Liu
  • Patent number: 11664286
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 11658099
    Abstract: Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 23, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Marc Alan Mangrum
  • Patent number: 11658046
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 23, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ting-Yeh Wu
  • Patent number: 11658130
    Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 23, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Osvaldo Jorge Lopez, Lance Cole Wright
  • Patent number: 11652273
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: May 16, 2023
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Yeh-Chun Kao, Shih-Huang Yeh, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 11637544
    Abstract: A crystal oscillator (101) includes: a piezoelectric resonator plate (2) on which a first excitation electrode and a second excitation electrode are formed; a first sealing member (3) covering the first excitation electrode of the piezoelectric resonator plate (2); a second sealing member (4) covering the second excitation electrode of the piezoelectric resonator plate (2); and an internal space (13) formed by bonding the first sealing member (3) to the piezoelectric resonator plate (2) and by bonding the second sealing member (4) to the piezoelectric resonator plate (2), so as to hermetically seal a vibrating part including the first excitation electrode and the second excitation electrode of the piezoelectric resonator plate (2). An electrode pattern (371) including a mounting pad for wire bonding is formed on an outer surface (first main surface (311)) of the first sealing member (3).
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 25, 2023
    Assignee: Daishinku Corporation
    Inventor: Takuya Kojo
  • Patent number: 11631528
    Abstract: The inductor includes a coil including a winding portion formed by winding a conductor wire having an insulating coating and lead-out portions extended from the winding portion, and a body made of a magnetic portion including magnetic powder and resin, and containing the coil, and outer electrodes on a body surface. The body includes a mounting surface, an upper surface opposite the mounting surface, a pair of opposing end surfaces adjacent to the mounting and upper surfaces, and a pair of opposing side surfaces adjacent to the mounting surface, the upper surface, and the end surfaces. End portions of the lead-out portions respectively have a flat portion exposed from the body surface, a covered portion adjacent to the flat portion at at least one of the end portions covered with the magnetic portion, and the flat portion is electrically connected to the outer electrode.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 18, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuki Kitashima
  • Patent number: 11627661
    Abstract: A method for producing a wired circuit board, the method including the steps of: a first step of providing an insulating layer having an opening penetrating in the thickness direction at one side surface in the thickness direction of the metal plate, a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, a third step of providing a second barrier layer continuously at one side in the thickness direction of the first barrier layer and an inner surface of the insulating layer facing the opening, a fourth step of providing a conductor layer so as to contact the second barrier layer, and a fifth step of removing the metal plate by etching.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 11, 2023
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Hayato Takakura, Masaki Ito, Yoshihiro Kawamura, Shuichi Wakaki
  • Patent number: 11618110
    Abstract: A solder paste includes a solder powder; and a flux component containing a compound having at least one carboxyl group protected by a trialkylsilyl group.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 4, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naomichi Ohashi, Koso Matsuno, Yasuhiro Okawa
  • Patent number: 11617259
    Abstract: The present invention relates to an embedded printed circuit board including: an insulation substrate including a cavity; a sensor device disposed on the cavity; an insulating layer disposed on the insulation substrate, having an opening part exposing the sensor device; and a pad part disposed on the lower surface of the opening part exposing the sensor device.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 28, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Mikael Tuominen, Seok Kim Tay
  • Patent number: 11557640
    Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, the second connection pads spaced apart from the first connection pads in a second direction perpendicular to the first direction, and a driving chip disposed on the board between the first connection pads and the second connection pads. Each of the first connection pads includes a first conductive layer disposed on the board, a second conductive layer which entirely overlaps with the first conductive layer in a plan view, is disposed on the first conductive layer and is formed of a different material from that of the first conductive layer, and a third conductive layer entirely overlapping with the second conductive layer and disposed on the second conductive layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joo-Nyung Jang
  • Patent number: 11557684
    Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chanyuan Liu
  • Patent number: 11538773
    Abstract: An electronic device package includes: a board including first surface and a second surface facing away from each other, and including a first layer adjacent to the first surface and a second layer adjacent to the second surface, wherein a step portion is formed on a side surface between the first layer and the second layer; an electronic device mounted on the first surface; an antenna layer formed in the second layer or on the second surface; a molded portion formed to cover the electronic device on the first surface; and a conductive film formed to cover a surface of the molded portion and a side surface of the first layer, and including an end portion positioned at the step portion.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: December 27, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seok Yoon Hong, Seohyun Park, Hyukki Kwon, Hansu Park
  • Patent number: 11536974
    Abstract: A flexible display device including a first display area including first data lines arranged in a first direction, first scan lines arranged in a second direction intersecting the first direction, a second display area including second data lines arranged in the first direction, second scan lines arranged in the second direction, a first circuit unit adjacent to a side of the first display area, a second circuit unit adjacent to a side of the second display area, and a third circuit unit between the first display area and the second display area.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: December 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Sup Lee, Jae Joong Kwon, Ju Hwa Ha
  • Patent number: 11521906
    Abstract: A circuit module (100) includes: a substrate (10) including a plurality of inner conductors (2); a first electronic component arranged on one main surface (S1) of the substrate (10); a first resin layer (40) provided on the one main surface (S1) and configured to seal the first electronic component; a plurality of outer electrodes (B1) provided on another main surface (S2) of the substrate (10) and including a ground electrode; a conductor film (50) provided at least on an outer surface of the first resin layer (40) and a side surface (S3) of the substrate (10) and connected to the ground electrode with at least one of the plurality of inner conductors (2) interposed therebetween; and a resin film (60).
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: December 6, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Tetsuya Oda, Hideki Shinkai, Toru Koidesawa
  • Patent number: 11515174
    Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Youngik Kwon, Jong Sik Paek
  • Patent number: 11477927
    Abstract: In the component mounting system, when an electronic component having a positioning target is held and mounted onto the upper face of a board, the positioning target is aligned to a predetermined position of the board. The component mounting system detects a positional deviation of the positioning target on the upper face of the electronic component and performs an arrangement operation of arranging a positioning material on the board by correcting the arrangement position in accordance with the detected positional deviation. The component mounting system then performs a mounting operation for mounting the electronic component on the board by aligning the positioning target to the predetermined position of the board on which the positioning material has been arranged.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 18, 2022
    Assignee: FUJI CORPORATION
    Inventors: Takeshi Sakurayama, Kota Niwa
  • Patent number: 11464120
    Abstract: A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-jae Han
  • Patent number: 11462454
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 4, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
  • Patent number: 11457524
    Abstract: A chip includes a plurality of ground conductors that at least partially surround a signal conductor on a same die. The signal conductor carries an interface (e.g., high speed) signal, and the ground conductors filter electromagnetic interference generated by the signal carried by the signal conductor. A chip package includes a plurality of ground pins around a signal pin that carries an interface signal. The ground pins filter electromagnetic interference generated by the signal carried by the signal pin. A printed circuit board includes a plurality of ground conductors around a signal line. The ground conductors are in vias and filter electromagnetic interference generated by an interface signal carried by the signal line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 27, 2022
    Assignee: NXP B.V.
    Inventors: Mahmoud Mohamed Amin El Sabbagh, Anu Mathew, Siamak Delshadpour
  • Patent number: 11327468
    Abstract: When a specification setting unit sets a specification of a lot number “k+1” after setting a specification of a lot number “k”, a mounting program selector performs a mounting program corresponding to the lot number “k”, and then selects a mounting program corresponding to the lot number “k+1” according to matching between a mounting number from the mounting program and a planned number of products of the lot number “k”. A printing program selector selects a printing program corresponding to the lot number “k”, and then selects a printing program corresponding to the lot number “k+1” according to matching between a sum of a printing number from the printing program and a defective product number and the planned number of products of the lot number “k”. Consequently, on-demand production of an electronic device can easily be manufactured on a manufacturing line.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 10, 2022
    Assignee: OMRON CORPORATION
    Inventor: Wakahiro Kawai
  • Patent number: 11297718
    Abstract: A method of manufacturing a flexible circuit comprises providing a laminated substrate that includes a conductive layer, an adhesive layer, and a support layer. The method comprises forming conductive traces by removing selected portions of the conductive layer and the adhesive layer by dry milling the laminated substrate. The method comprises applying a protective coating to the conductive traces. The method comprises dispensing a solder material on the protective coating at a first connection point and arranging a first component at the first connection point. The method comprises heating the solder material to remove the protective coating from the first connection point and to connect the first component to one of the conductive traces at the first connection point. The method comprises attaching a second component to the conductive layer at a second connection point that is free of the protective coating by a process other than soldering.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 5, 2022
    Assignee: Gentherm GmbH
    Inventor: Michael Peter Ciaccio
  • Patent number: 11292166
    Abstract: A method, for manufacturing an electronic assembly, such as an antenna or a capacitive sensing device or a coupled inductor, comprising at least a first electrically conductive element and a second electrically conductive element is presented. The method comprises obtaining said electrically conductive elements, such as patch elements, arranging said electrically conductive elements, such as inside of a cavity defined by a mold structure, at a pre-defined distance from each other for establishing an electromagnetic coupling between said electrically conductive elements, and molding, such as injection molding, a molding material layer at least between said electrically conductive elements, wherein the molding material layer has a thickness between said electrically conductive elements defined by the pre-defined distance. In addition, electronic assemblies, antennas, capacitive sensing devices and coupled inductors are presented.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 5, 2022
    Assignee: TACTOTEK OY
    Inventors: Anne Isohätälä, Hasse Sinivaara, Mikko Heikkinen
  • Patent number: 11285645
    Abstract: A method, for manufacturing an electronic assembly, such as an antenna or a capacitive sensing device or a coupled inductor, comprising at least a first electrically conductive element and a second electrically conductive element is presented. The method comprises obtaining said electrically conductive elements, such as patch elements, arranging said electrically conductive elements, such as inside of a cavity defined by a mold structure, at a pre-defined distance from each other for establishing an electromagnetic coupling between said electrically conductive elements, and molding, such as injection molding, a molding material layer at least between said electrically conductive elements, wherein the molding material layer has a thickness between said electrically conductive elements defined by the pre-defined distance. In addition, electronic assemblies, antennas, capacitive sensing devices and coupled inductors are presented.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 29, 2022
    Assignee: TACTOTEK OY
    Inventors: Anne Isohätälä, Hasse Sinivaara, Mikko Heikkinen
  • Patent number: 11191186
    Abstract: A system and method for cooling electronic devices disposed within the inner volume of an enclosure. The inner volume of the enclosure contains one or more single phase or multi-phase thermally conductive fluids and may contain solid or sealed hollow structures that displace and direct thermally conductive fluids.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 30, 2021
    Inventor: David Lane Smith
  • Patent number: 11122710
    Abstract: An electronic device comprises a heat dissipating layer disposed on a rear cover, a first shield cover and a second shield cover disposed on a mainboard, and a speaker box disposed on a surface of an antenna panel. The first region of the heat dissipating layer is in contact with the first shield cover, and the second shield cover is in contact with a first region of a middle frame; a second region of the heat dissipating layer is in contact with a surface of a battery, and the other surface of the battery is in contact with a second region of the middle frame, and a third region of the heat dissipating layer is in contact with a surface of the speaker box that is distant from the antenna panel, and the other surface of the antenna panel is in contact with a third region of the middle frame.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 14, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Linfang Jin, Guo Yang, Shuainan Lin
  • Patent number: 10935813
    Abstract: Designs, apparatus and methods to form contact lenses with aesthetic elements on demand are described. In some examples, the method of defining the aesthetic aspect includes printing patterns. Other examples include photochromic or thermochromic elements which may provide patterning on exposure to electromagnetic irradiation. In some further examples, energized components in contact lenses may provide aesthetic characteristics.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Johnson & Johnson Vision Care, Inc
    Inventors: Frederick A. Flitsch, Randall B. Pugh
  • Patent number: 10849258
    Abstract: Provided is an electronic component package for electromagnetic interference shielding. The electronic component package for electromagnetic interference shielding according to an embodiment of the present invention comprises a substrate where electronic components are mounted, a molding member formed on the substrate and the electronic components, a magnetic layer formed on the molding member, and a conductive layer formed on the magnetic layer. Electromagnetic waves generated from the electronic components embeded in the molding member are absorbed in the magnetic layer to thus prevent or reduce harmful influence on other electronic components mounted in adjacent places. In addition, harmful electromagnetic waves generated from the outside may be shielded due to the conductive layer formed on the magnetic layer, thereby protecting electronic components embeded in the molding member from being influenced by the electromagnetic waves.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 24, 2020
    Assignee: NTRIUM INC.
    Inventors: Se Young Jeong, Ki Su Joo, Ju Young Lee, Jeong Woo Hwang, Jin Ho Yoon
  • Patent number: 10667408
    Abstract: A method of encapsulating and hermetically sealing a printed circuit board of a flex cable includes: positioning a printed circuit board portion of a flex cable into a channel defined in a first mold half of a mold, the printed circuit board portion including a substrate and electronic components mounted on the substrate; mounting a second mold half onto the first mold half to enclose the channel of the first mold half and form a cavity within the mold; and filling the cavity of the mold with an encapsulation material through an inlet opening defined through the mold.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 26, 2020
    Assignee: COVIDIEN LP
    Inventors: Anthony Sgroi, Jr., Patrick Mozdzierz, Stephen Paul, David Valentine, Scott Firth
  • Patent number: 10624214
    Abstract: Readily manufactured structures for sealing or encapsulating devices in system-in-a-package modules, such that the modules are easily assembled, have a low-profile, and are space efficient. One example may provide readily manufactured covers for SIP modules. These modules may be easily assembled by attaching the cover to a top side of a substrate. These SIP modules may have a low-profile, for example when their height is reduced using one or more recesses in a bottom surface of a top of the recess, where the one or more recesses are arranged to accept one or more components. These SIP modules may be made space efficient by placing an edge of a cover near an edge of the substrate and connecting the plating of the cover using side plating on, or vias through, the substrate.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 14, 2020
    Assignee: Apple Inc.
    Inventors: Amir Salehi, Takayoshi Katahira, Vu T. Vo, Wyeman Chen, Chang Liu, Dennis R. Pyper, Steven Patrick Cardinali, Lan Hoang, Siddharth Nangia, Meng Chi Lee
  • Patent number: 10600715
    Abstract: A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, and electrically connecting the integrated circuit chip to the embedded conductor.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Young Hoon Kwark
  • Patent number: 10466506
    Abstract: Designs, apparatus and methods to form contact lenses with aesthetic elements on demand are described. In some examples, the method of defining the aesthetic aspect includes printing patterns. Other examples include photochromic or thermochromic elements which may provide patterning on exposure to electromagnetic irradiation. In some further examples, energized components in contact lenses may provide aesthetic characteristics.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 5, 2019
    Assignee: Johnson & Johnson Vision Care, Inc.
    Inventors: Frederick A. Flitsch, Randall B. Pugh