With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
  • Patent number: 10354966
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10283680
    Abstract: An electronic module and method for the production of the electronic module in accordance with some embodiments of the invention are disclosed. The electronic module includes at least one electronic component affixed to a conductive layer by means of sticky electrically insulating layer, where the electronic component is embedded in a transparent foil. The electronic module is produces by providing an electrically conductive layer. At least one electronic component is affixed to the electrically conductive layer by means of a sticky electrically insulating layer and embedded in a transparent foil. The at least one electronic component is electronically contacted with the conductive layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 7, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gregor Langer, Johannes Stahr
  • Patent number: 10162395
    Abstract: The description relates to devices, such as computing devices. One example can include a sandwich structured composite housing. The example can also include a set of electronic components positioned over the sandwich structured composite housing. The set of electronic components can have a profile against the sandwich structured composite housing. The sandwich structured composite housing can have a corresponding negative profile.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 25, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kurt A. Jenkins, Edward Burress, Jaya Narain, Robert J. Bergeson, Andrew W. Hill, Taylor Stellman
  • Patent number: 10120423
    Abstract: Described herein are unibody thermal enclosures for electronic devices. In some instances, the enclosure is a unibody structure formed by injecting a structural material into the tool suspending thermal absorbing/spreading material and thermal insulating material within a cavity of the tool. In other instances, the thermal absorbing/spreading material may be exposed to circuitry of the electronic device and the thermal insulating material may be exposed to the exterior of the electronic device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 6, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Bradley David Urban, Troy Hulick, Shelomon Patrick Doblack, Robert Olson, Albert John Yu Sam Chua, Daniel Jones, Adam Kenneth Cybart, Gaurav Soni, William James Carter-Giannini, Matthew Michael Seflic
  • Patent number: 9824948
    Abstract: A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 21, 2017
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Erick Merle Spory
  • Patent number: 9820413
    Abstract: As a thermal conductive material having fluidity is applied on a base plate, probability of a decrease in thermal conductive performance, i.e., probability of a decrease in a heat radiation property caused by a human work, can be suppressed in comparison with the case in which a heat transfer sheet is installed. When the thermal conductive material having fluidity is used, thermal conductive performance is obtained by applying the thermal conductive material is applied and thus reliability is improved. In addition, as stepped sections are formed at sidewalls of circumferential edges of protrusion surfaces on which the thermal conductive material is applied, even when the thermal conductive material having fluidity sticks out of the protrusion surfaces, since the thermal conductive material is accommodated in the stepped sections, the thermal conductive material is suppressed from sticking to another electronic component or the like to improve reliability.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 14, 2017
    Assignee: TDK CORPORATION
    Inventor: Akira Ikezawa
  • Patent number: 9691746
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 9392730
    Abstract: An electronic device having one or more components that generate heat during operation includes a structure for temperature management and heat dissipation. The structure for temperature management and heat dissipation comprises a heat transfer substrate having a surface that is in thermal communication with the ambient environment and a temperature management material in physical contact with at least a portion of the one or more components of the electronic device and at least a portion of the heat transfer substrate. The temperature management material comprises a polymeric phase change material having a latent heat of at least 5 Joules per gram and a transition temperature between 0° C. and 100° C., and a thermal conductive filler.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 12, 2016
    Assignee: OUTLAST TECHNOLOGIES, LLC
    Inventors: Mark Hartmann, Greg Roda
  • Patent number: 9362660
    Abstract: An implantable medical device connector assembly and method of manufacture include a molded, insulative shell having an inner surface forming a connector bore, a circuit member including one or more traces extending through apertures in the connector shell. One or more conductive members, positioned along the connector bore, are electrically coupled to the traces. The sealing members are positioned between the conductive members.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 7, 2016
    Assignee: Medtronic, Inc.
    Inventors: Andrew J Ries, Jeffrey A Swanson, George A Patras
  • Patent number: 9332646
    Abstract: An electronic package module includes a circuit board having a supporting surface, at least one first electronic component, at least one second electronic component, and at least one molding compound. The first and second electronic components are mounted on the supporting surface. The molding compound is disposed on the supporting surface and covers the supporting surface partially. The molding compound encapsulates the first electronic component yet not the second electronic component.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: May 3, 2016
    Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Jen-Chun Chen, Hsin-Chin Chang
  • Patent number: 9317079
    Abstract: A media device, which may take the form of a set top box (STB), includes a housing or chassis that incorporates an interface panel having selectively configured regions that cooperate with components mounted on a printed circuit board. The selectively configured regions of the interface panel may advantageously provide desired clearance or contact between the interface panel and one or more of the components. In addition, the selectively configured regions of the interface panel may be arranged to provide structural support to a top panel of the chassis while providing specific heat transfer pathways between the components and the chassis. In this manner, the interface panel may be controllably designed with a desired thermal mass and/or a desired thermal conductivity in specific regions of the interface panel by varying properties of the interface panel which may include, but are not limited to, the panel thickness and material.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 19, 2016
    Assignee: EchoStar UK Holdings Limited
    Inventor: David Robert Burton
  • Patent number: 9295157
    Abstract: Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. Locations of where the racetrack can be adjusted (for example, narrowed) and/or removed without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, a portion of the racetrack can be removed to create a break and/or a portion of the racetrack can be narrowed in a selected area.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 22, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read, Hoang Mong Nguyen, Anthony James LoBianco, Guohao Zhang, Dinhphuoc Vu Hoang
  • Patent number: 9287478
    Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 15, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 9266267
    Abstract: A method for manufacturing a sensor in which a sensor element, which comprises at least a first housing, is at least partially encapsulation-molded in an encapsulation-molding process. As a result of the encapsulation-molding process a sensor housing is formed. The sensor element is mechanically connected to a support element and/or accommodated by the support element, after which the sensor element and the support element are encapsulation-molded in a common encapsulation-molding process for forming the sensor housing.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 23, 2016
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Edmond De Volder, Dietmar Huber, Andreas Doering, Jakob Schillinger, Martin Watzlawik, Lothar Biebricher
  • Patent number: 9257394
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 9, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kuang-Neng Chung, Hsin-Lung Chung, Tien-Chung Huang, Tsung-Hsien Hsu
  • Patent number: 9252032
    Abstract: A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, WonJun Ko, JaEun Yun
  • Patent number: 9197026
    Abstract: Disclosed is a printed circuit board assembly PBA on which a connector for electrical connection to an external connection element is mounted. Such an assembly may be formed with a molding method of a PBA which includes applying a polymer resin to the PBA to mold the PBA in order to offer stiffness thereto. The foregoing method of molding the PBA according to the present disclosure is a molding method of a PBA including a PCB and a connector mounted on the PCB to electrically connect the same to an external connection element. The method includes combining the connector with a connector cover, applying a resin to the PBA combined with the connector cover to execute molding of the PBA, and separating the connector cover from the molded PBA to expose the electrode terminal for an external connection element.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Tae Kim, Tae Sang Park, Young Jun Moon, Soon Min Hong
  • Patent number: 9177837
    Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 3, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 9171969
    Abstract: A mounting member includes: an insulating substrate, a first die pad unit, first and second terminals. The insulating substrate has a rectangular first surface, a second surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A through hole is provided from the first surface to the second surface. The first die pad unit is provided on the first surface. The first terminal has a conductive region covering the first side surface, the first surface, and the second surface. The second terminal has a conductive region covering the second side surface and the second surface, connected to the first die pad unit by conductive material provided in the through hole or on a side wall of the through hole. The first die pad unit, the first terminal, and the second terminal are apart from one another.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mami Yamamoto, Yoshio Noguchi
  • Patent number: 9165907
    Abstract: In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 20, 2015
    Assignee: Interposers GMBH
    Inventors: Andreas Jakob, Thomas Kaiser
  • Patent number: 9155204
    Abstract: A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Tomoyuki Aoki
  • Patent number: 9155233
    Abstract: An electromagnetic shield is provided, for example for a printed circuit board. A shield lid fits onto a base structure having at least two, more typically four, opposing sidewalls. The lid includes a top portion and a lip extending downward from the top portion to cap the base structure. The lid includes at least one deformation inhibiting feature extending downward from the top portion, for placement near or against an interior portion of a sidewall, for example against an edge of a folded-over sidewall. The deformation inhibiting feature may include one or more half-dimples stamped into the lid. In response to an external force, the deformation inhibiting feature presses against its adjacent sidewall in order to brace the shield lid. This inhibits the base structure from deforming the lip due to outward pressure of a sidewall onto a portion of the lip, located opposite the deformation inhibiting feature.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Sierra Wireless, Inc.
    Inventors: Bruce Richard John Samuels, Edwin Sy Liu
  • Patent number: 9105806
    Abstract: A GaN based light emitting diode device which emits polarized light or light of various degrees of polarization for use in the creation of optical devices. The die are cut to different shapes, or contain some indicia that are used to represent the configuration of the weak dipole plane and the strong dipole plane. This allows for the more efficient manufacturing of such light emitting diode based optical devices.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 11, 2015
    Assignees: SORAA, INC., KAAI, INC.
    Inventors: Rajat Sharma, Eric M. Hall
  • Patent number: 9091609
    Abstract: A protective casing for a household appliance includes an encapsulation and a support fitted therein. The support has an upper recess for the sensor, also housing a cushion with a central hole, and an electrical connector; and the encapsulation with a horizontal structural portion, from which a mechanical engagement, a bed and a connection project. The bed is generally cylindrical, with a flat top with a central hole and an octagonal side surface with alternate round and flat walls, the internal surface delimited by the walls has a similar and/or cooperative geometry with the side surface of the support. Particularly, a bottom surface, the cushion and top of the bed define an open chamber, housing the sensor. The chamber being in fluid communication with the source of the pressure to be measured through the lumen of the connector and the central hole as included on the top of the bed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 28, 2015
    Assignee: EMICOL ELETRO ELECTRONICA S.A.
    Inventor: José Claudio Micai
  • Patent number: 9087924
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: July 21, 2015
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 9054086
    Abstract: A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: June 9, 2015
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Douglas Dean Lopata, John David Weld, Mathew A. Wilkowski
  • Publication number: 20150138776
    Abstract: A multiple-ply solid state light fixture is disclosed. A panelized, solid state light fixture includes combined layers of material chemically bonded together without a traditional mechanical housing and with relatively few or no fasteners. In example embodiments, the solid state light fixture includes an LED mounting substrate, a thermal material on a non-LED side of the LED mounting substrate, and an optical material on the LED side of the LED mounting substrate. A plurality of LEDs are disposed or mounted, with or without additional packaging, on the LED side of the LED mounting substrate. A chemical bond is created between the substrate and the other layers. This chemical bond can be created, for example, through use of applied fluid or gelatinous compounds that are then solidified, or through the use of adhesives.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Cree, Inc.
    Inventor: James Michael Lay
  • Publication number: 20150136451
    Abstract: There is provided an electronic component module including: a substrate on which an electronic component is mounted; at least one insulating member coupled to the substrate and having a surface on which a plating layer is formed; and a molded portion covering the electronic component and the at least one insulating member, wherein the insulating member is bonded to the substrate and a metal layer is formed on a bonding surface between the substrate and the insulating member.
    Type: Application
    Filed: May 2, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Woo PARK, Do Jae YOO, Tae Hyun KIM
  • Publication number: 20150131231
    Abstract: There are provided an electronic component module allowing for a circuit wiring to be disposed outside of a molded part by a plating process, and a manufacturing method thereof, the electronic component module including a substrate; at least one electronic component mounted on the substrate; a molded part sealing the electronic component; a plurality of conductive connectors having one ends bonded to the substrate or one surface of the electronic component and formed in the molded part to penetrate through the molded part; and at least one plane pattern formed on an outer surface of the molded part and electrically connected to at least one of the conductive connectors.
    Type: Application
    Filed: May 1, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Jae YOO, Jong In Ryu, Eun Jung Jo, Jae Hyun Lim, Kyu Hwan Oh
  • Publication number: 20150131230
    Abstract: A module IC package structure for increasing heat-dissipating efficiency includes a substrate unit, an electronic unit, a package unit, a first heat-dissipating unit and a second heat-dissipating unit. The substrate unit includes a circuit substrate. The electronic unit includes a plurality of electronic components disposed on the circuit substrate and electrically connected to the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate for enclosing the electronic components. The first heat-dissipating unit includes a heat-dissipating base layer disposed on the top surface of the package gel body. The second heat-dissipating unit includes a plurality of heat-dissipating auxiliary layers disposed on the top surface of the heat-dissipating base layer. Whereby, the heat-dissipating efficiency of the module IC package structure can be increased by matching the heat-dissipating base layer and the heat-dissipating auxiliary layers.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: AZUREWAVE TECHNOLOGIES, INC.
    Inventor: HUANG-CHAN CHIEN
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Publication number: 20150125050
    Abstract: Disclosed is a fingerprint recognition sensor module including a flexible printed circuit board. The flexible printed circuit board includes a first sensing region formed with a first sensing input unit, a second sensing region formed with a second sensing input unit, a chip mounting region on which an ASIC is mounted to convert a fingerprint sensed through the input units into a digital signal and transmit the digital signal to a connector, and a connection section to which the connector is connected. The chip mounting region and the first and second sensing regions are separated from each other on the same surface, and the flexible printed circuit board is folded such that projection planes of the chip mounting region and the first and second sensing regions are superposed one above another.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jin-Seong LEE, Jong-Hwa KIM, Kyoung-Jun PARK, Ho-Chul JOUNG, Young-Ho KIM
  • Patent number: 9021689
    Abstract: A method of forming a dual port pressure sensor includes forming a first opening and a second opening in a flag of a lead frame. An encapsulant is molded to hold the lead frame in which the encapsulant is over a top of the flag and a bottom of the flag is uncovered by the encapsulant. A first opening in the encapsulant is aligned with and larger than the first opening in the flag and a second opening in the encapsulant aligned with the second opening in the flag. A pressure sensor transducer is attached to the bottom of the flag to cover the first opening in the flag, wherein the pressure sensor transducer provides an electrically detectable correlation to a pressure differential based on a first pressure received on its top side and a second pressure received on its bottom side. An integrated circuit is attached to the bottom of the flag. The integrated circuit is electrically coupled to the pressure sensor. A lid is attached to the encapsulant to form an enclosure around the bottom of the flag.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen R. Hooper, William G. McDonald
  • Patent number: 9009958
    Abstract: A mountable device includes a bio-compatible structure embedded in a polymer that defines at least one mounting surface. The bio-compatible structure includes an electronic component having electrical contacts, sensor electrodes, and electrical interconnects between the sensor electrodes and the electrical contacts. The bio-compatible structure is fabricated such that it is fully encapsulated by a bio-compatible material, except for the sensor electrodes. In the fabrication, the electronic component is positioned on a first layer of bio-compatible material and a second layer of bio-compatible material is formed over the first layer of bio-compatible material and the electronic component. The electrical contacts are exposed by removing a portion of the second layer, a conductive pattern is formed to define the sensor electrodes and electrical interconnects, and a third layer of bio-compatible material is formed over the conductive pattern.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventor: James Etzkorn
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Publication number: 20150085455
    Abstract: Embodiments of the invention provide an electronic component-embedded substrate and a manufacturing method thereof. According to at least one embodiment, the electronic component-embedded substrate includes a cavity formed in a core substrate and including two or more embedding spaces which have a rectangular shape (when viewed on a plane) and are connected to each other by a connecting space, and two or more electronic components separately accommodated in the embedding spaces of the cavity, respectively. According to at least one embodiment, neighboring long sides of first and second embedding spaces are partially connected to each other by the connecting space, and one side (when viewed on the plane) forming a connecting width of the connecting space connecting the first and second embedding spaces to each other coincides with one short side of the first embedding space, and the other side (when viewed on the plane) coincides with the other short side of the second embedding space.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong Won KIM, Kyoung Ro YOON, Bong Soo KIM, Jung Soo BYUN, Kyo Min JUNG, Tae Gon LEE
  • Publication number: 20150085524
    Abstract: A light emitting device includes a support having an interstice and at least one LED located in the interstice and at least one of a waveguide or an optical launch having a transparent material encapsulating the at least one LED located in the interstice.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Ping WANG, Douglas HARVEY, Tyler KAKUDA, Ronald KANESHIRO
  • Publication number: 20150085446
    Abstract: In various embodiments, a substrate is provided. The substrate may include: a ceramic carrier having a first side and a second side opposite the first side; a first metal layer disposed over the first side of the ceramic carrier; a second metal layer disposed over the second side of the ceramic carrier; and a cooling structure formed into or over the second metal layer.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Wolfram Hable, Andreas Grassmann, Frank Winter, Ottmar Geitner, Alexander Schwarz, Alexander Herbrandt
  • Patent number: 8984746
    Abstract: A method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conductor-pattern layers and, if necessary, insulator layers are manufactured on one or both sides of the intermediate product, in such a way that, when manufacturing the first conductor-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages can also be performed on a single manufacturing line.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: March 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm, Antti Lihola
  • Publication number: 20150070851
    Abstract: A circuit module includes a wiring substrate having a mount surface, a conductor pattern, and an insulating protective layer, the mount surface having first and second areas, the conductor pattern being formed along a boundary between the first and second areas on the mount surface, the insulating protective layer being formed on the mount surface, the insulating protective layer covering the mount surface and the conductor pattern; a plurality of electronic components mounted on the first and second areas; an insulating sealing layer having a trench, the insulating sealing layer covering the plurality of electronic components, the trench having a depth such that the trench penetrates the protective layer to reach a surface of the conductive pattern; and a conductive shield having first and second shield portions, the first shield portion covering an outer surface of the sealing layer, the second shield portion being electrically connected to the conductor pattern.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 12, 2015
    Applicant: Taiyo Yuden Co., Ltd.
    Inventors: Kenzo KITAZAKI, Masaya SHIMAMURA, Eiji MUGIYA, Takehiko KAI
  • Patent number: 8973258
    Abstract: A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Ching-Sheng Chen
  • Publication number: 20150062825
    Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Inventors: Peter Ossimitz, Juergen Schaefer, Liu Chen, Markus Dinkel, Stefan MacHeiner
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: Jürgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8966749
    Abstract: A manufacturing method for a protection circuit module of a secondary battery is disclosed. The method includes mounting a die type circuit device to an FPCB. The mounting of the circuit device includes bonding the circuit device to the FPCB by wire bonding. The method may further include forming a protective layer on the FPCB to cover the circuit device. The protective layer may be formed by coating insulation resin on the FPCB.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: March 3, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Bong Young Kim
  • Patent number: 8969736
    Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 3, 2015
    Assignee: Nitto Denko Corporation
    Inventor: Daisuke Yamauchi
  • Publication number: 20150055311
    Abstract: An electronic component includes a circuit board that includes a ground terminal connected to a ground potential, a coil component that is assembled on the circuit board, the coil component includes a T-shaped core and an air-core coil, a ground connection electrode that is assembled on the circuit board next to the coil component and that is connected to the ground terminal, and a mixture of a metal composite magnetic material and a resin that is formed on the circuit board and that covers the coil component and the ground connection electrode as a package. A part of the ground connection electrode is exposed outside the mixture.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: SUMIDA Corporation
    Inventors: Mitsugu KAWARAI, Douglas James MALCOLM
  • Patent number: 8959762
    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: February 24, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Donald Joseph Leahy, Brian D. Sawyer, Stephen Parker, Thomas Scott Morris
  • Patent number: 8959756
    Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: February 24, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Publication number: 20150049446
    Abstract: Disclosed is an embedded electronic component which can improve reliability of connection with external wiring and efficiency of an embedding process by including: a contact pad provided on at least one surface of a body portion and made of a conductive material; a first insulating layer for covering the at least one surface of the body portion; a first pad in contact with a surface of the contact pad and made of a conductive material; a rearrangement portion provided on a surface of the first insulating layer to be in contact with the first pad; a second pad provided on the surface of the first insulating layer to be in contact with the rearrangement portion; and a second insulating layer having an opening to expose a portion of the second pad while covering the first insulating layer, the first pad, the rearrangement portion, and the second pad.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 19, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Doo Hwan LEE
  • Publication number: 20150047897
    Abstract: Some embodiments comprise apparatuses providing an electrical conductor guide for use with an irrigation device comprising: a housing having a volume and containing an electronic component and one or more electrical conductors coupled thereto; a support structure having one or more apertures each configured to allow at least one of the one or more electrical conductors to extend therethrough; and a potting material at least partially filling and sealing the volume from an external environment, wherein the one or more electrical conductors extend out of the potting material and the housing; wherein the support structure is cooperated with the one or more electrical conductors and is configured to inhibit movement of the one or more electrical conductors relative to the potting material due to external forces applied to the one or more electrical conductors to reduce the forces applied to the potting material or to electronic component.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 19, 2015
    Inventors: Daniel B. Zimet, Bashir Z. Eslam, Roger S. Neitzel, Douglas S. Busch