With Selective Destruction Of Conductive Paths Patents (Class 29/847)
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Patent number: 7093356Abstract: A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.Type: GrantFiled: September 15, 2003Date of Patent: August 22, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe
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Patent number: 7089636Abstract: The present invention provides a piezoelectric thin film element with superior piezoelectric properties in which the condition of the crystal of the piezoelectric thin film is appropriately controlled, and a manufacturing method thereof, as well as a inkjet recording head, inkjet printer, or other liquid ejecting apparatus employing the same. The piezoelectric thin film element 40 comprises a top electrode 44, a bottom electrode 42, and a piezoelectric thin film 43 formed between the top electrode 44 and the bottom electrode 42, wherein the piezoelectric thin film 43 is structured so as to comprise a first layer 431 located nearest to the bottom electrode and second layers (433–436) that are located nearer to the top electrode than the first layer and that each have a thickness greater than that of the first layer 431.Type: GrantFiled: November 6, 2003Date of Patent: August 15, 2006Assignee: Seiko Epson CorporationInventor: Masami Murai
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Rigid-flexible PCB having coverlay made of liquid crystalline polymer and fabrication method thereof
Patent number: 7082679Abstract: Disclosed are a rigid-flexible PCB and a method for fabricating the rigid-flexible PCB. Characterized by using a liquid crystalline polymer for the formation of coverlay over flexible regions, the all-layer processing method has the advantage of preventing interlayer delamination, thereby providing a highly reliable rigid-flexible PCB which thus meets the recent requirements of electric appliances for low energy consumption, high frequency adoption, and slimness.Type: GrantFiled: October 20, 2004Date of Patent: August 1, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Bum-Young Myoung, Dek-Gin Yang, Dong-Kuk Kim -
Patent number: 7082669Abstract: A two-phase rotary encoder is provided which includes a substrate for the encoder which is double-faced and has a copper-foil-bonded substrate etched thereon, a first ring-shaped electrode pattern and a second ring-shaped electrode pattern formed concentrically around a center hole on the substrate, a smooth, level ring-shaped comb electrode pattern formed on an outermost periphery of the substrate, wiring patterns which cover the electrode patterns through each of external connecting terminals provided on the substrate, and a common external connecting terminal provided on an edge of the substrate, formed on a surface thereof via the center hole or a through hole. The rotary encoder further includes a resin-molded case, a shaft, a gear-shaped rotor, a click mechanism and a tact switch mechanism.Type: GrantFiled: June 27, 2003Date of Patent: August 1, 2006Assignee: Tsubame Musen, Inc.Inventor: Masao Imamura
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Patent number: 7080447Abstract: A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.Type: GrantFiled: March 16, 2004Date of Patent: July 25, 2006Assignee: Ultratera CorporationInventors: Chong-Ren Maa, Wan-Kuo Chih, Ming-Sung Tsai
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Patent number: 7076870Abstract: A surface-mount package for an oscillator crystal blank is made from a metal sheet substrate. Half-etched cavities are formed on one side of the sheet. The half-etched cavities are filled in with an insulator. The center of the insulator is drilled until metal is reached, leaving insulator on the sidewalls of the resulting drilled via. The bottom of the drilled via is plated with a contact metal such as nickel-gold, and then the entire drilled via is filled in with metal such as copper to form via-metal. An external metal surface-mount pad is formed on the surface of each via-metal. The metal sheet is flipped over, and a larger inner cavity etched through until the contact metal over the via-metal is reached. Conductive epoxy is placed on the contact metal, and electrodes on the crystal blank are attached to conductive epoxy.Type: GrantFiled: August 16, 2004Date of Patent: July 18, 2006Assignee: Pericom Semiconductor Corp.Inventor: Wen-Lo Hsieh
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Patent number: 7073246Abstract: A method of making a biosensor is provided. The biosensor includes an electrically conductive material on a base and electrode patterns formed on the base, the patterns having different feature sizes. The conductive material is partially removed from the base using broad field laser ablation so that less than 90% of the conductive material remains on the base and that the electrode pattern has an edge extending between two points. A standard deviation of the edge from a line extending between two points is less than about 6 ?m.Type: GrantFiled: June 20, 2003Date of Patent: July 11, 2006Assignee: Roche Diagnostics Operations, Inc.Inventors: Raghbir S. Bhullar, Eric R. Diebold, Brian S. Hill, Nigel A. Surridge, Douglas P. Walling
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Patent number: 7069645Abstract: A method for producing a circuit board having a metal circuit pattern on an insulating substrate is provided, including the steps of joining a metal plate onto a surface of the insulating substrate using a hard brazing member containing an active element and removing unnecessary conductive layer portions adjacent a metal circuit pattern of the metal plate to at least partially expose a portion of the surface of the insulating substrate.Type: GrantFiled: March 27, 2002Date of Patent: July 4, 2006Assignee: NGK Insulators, Ltd.Inventors: Takahiro Ishikawa, Masahiro Kida, Shuhei Ishikawa, Nobuaki Nakayama
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Patent number: 7069651Abstract: The invention provides abrasion resistant electrodes that comprise metal-coated conductive valleys between protrusions having a fractured metal coating thereon; electrical devices made from a plurality of said electrodes; and methods of making said devices.Type: GrantFiled: November 6, 2003Date of Patent: July 4, 2006Assignee: 3M Innovative Properties CompanyInventors: Paul D. Graham, Douglas A. Huntley
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Patent number: 7065869Abstract: Disclosed is a design method for plating of a printed circuit board (PCB) strip, in which a main plating line is optionally formed on a component side, a solder side, or an inner layer of the PCB strip by modifying a sub-plating line of the PCB strip used to manufacture a semiconductor chip package, and a method of manufacturing the semiconductor chip package using the same. Therefore, an excellent semiconductor chip package is manufactured without a short when the PCB strip is cut using a sawing machine because misalignment of main plating lines of the solder side and the component side of the PCB strip is avoided, and an interval between PCB units is reduced to desirably increase the number of PCB units in the PCB strip without the short when the PCB strip is cut.Type: GrantFiled: February 7, 2003Date of Patent: June 27, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Tae-Hyeog Kang, Sang-Kab Park, Kwang-Ho Yoon, Bong-Kyu Choi
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Patent number: 7065847Abstract: A piezoelectric element with stable and excellent piezoelectric properties is made by: a step of forming a diaphragm 30 (31, 32) on a substrate 20 (S1); a step of forming a bottom electrode 33 on the diaphragm 30 (S2); a step of forming a first piezoelectric layer 43a on the bottom electrode 33 (S3); a step of patterning both the piezoelectric layer 43a and the bottom electrode 33 (S4); a step of forming a second piezoelectric layer on the piezoelectric layer 43a and on the diaphragm 30 to mature a piezoelectric film 43 (S5); and a step of forming a top electrode 44 on the piezoelectric film 43 (S6).Type: GrantFiled: January 16, 2004Date of Patent: June 27, 2006Assignee: Seiko Epson CorporationInventor: Masami Murai
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Patent number: 7062845Abstract: A laser drilling system for drilling blind vias in printed circuit board panels, multichip modules and chipscale packages with top and bottom surfaces and which include multiple dielectric polymer and metal layers. The system includes a first laser module comprising a laser able to form at least one via per pulse through one or more polymer layers. The vias are circular or non-circular in shape. An articulated arm is adapted to move at a speed of about 200 inches per second and at an acceleration of about 5 g's or more. A beam delivery unit is attached to the articulated arm and a conveyor adapted to move panels at a constant speed. The first laser module positioned on a separate track from the conveyor moves at a faster rate than the conveyor to drill the top surface. A second laser module is positioned to move on another separate track from the conveyor movable at a faster rate so as to drill the bottom surface.Type: GrantFiled: March 14, 2003Date of Patent: June 20, 2006Assignee: Laservia CorporationInventor: Larry W. Burgess
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Patent number: 7059039Abstract: A method for producing printed wiring boards comprises the steps of perforating through holes at predetermined positions in an adhesive insulator sheet, filling the through holes with a conductive material such as a conductive paste or metal balls, transferring conductive wiring patterns that have been formed on surfaces of releasable supporting sheets onto the surfaces of the adhesive insulator sheet by heat and pressure. Simultaneously, interlayer via-connections are performed by means of the conductive material filled into the through holes.Type: GrantFiled: January 21, 2004Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahide Tsukamoto, Masanaru Hasegawa, Hideo Hatanaka
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Patent number: 7056448Abstract: A method for forming a circuit pattern includes at least a step (a) of subjecting a non-conductor to electroless copper plating to form a copper film and a step (b) of etching the copper film so as to form a circuit pattern. As a catalyst for the electroless copper plating, a silver colloidal solution is used containing as essential components at least the following: (I) silver colloidal particles; (II) one or more of ions of metal having an electric potential which can reduce silver ions to metal silver in the solution and/or ions which result from oxidation of the ion at the time of reduction of the silver ions; and (III) one or more of hydroxycarboxylate, condensed phosphate and/or amine carboxylate ions. The silver colloidal particles (I) are produced by the ion (II) of the metal having an electric potential which can reduce silver ions to metal silver. The circuit pattern may be formed on a printed wiring board.Type: GrantFiled: May 20, 2003Date of Patent: June 6, 2006Assignee: Daiwa Fine Chemicals Co., Ltd.Inventors: Yoshiaki Okuhama, Keigo Obata, Masakazu Yoshimoto, Shingo Kitamura, Seiichiro Nakao, Osamu Masuyama, Hidenori Tsuji
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Patent number: 7051430Abstract: Methods of manufacturing a printed board assembly. In one embodiment, a substrate is coated with an electrically conducting material; electrical components are mounted on some areas of the substrate; non-conducting material is disposed in areas between the electrical components; the substrate, electrical components and non-conducting material are sandwiched between two sheets of resin coated conducting foil, wherein the resin on the foils faces the substrate and buries the electrical components; circuit patterns are etched in the exposed surfaces of the resin coated conducting foils; and, electrical connections are established between at least one of the resin coated conducting foils and the electronic components.Type: GrantFiled: February 19, 2003Date of Patent: May 30, 2006Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Leif Bergstedt, Per Ligander, Katarina Boustedt
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Patent number: 7051437Abstract: A method for making an inkjet head, including a step of irradiating laser light onto an inkjet head material for removing a part of the inkjet head material. The laser light is emitted from a solid laser and has a wavelength of not longer than 355 nm.Type: GrantFiled: April 28, 2003Date of Patent: May 30, 2006Assignee: Konica CorporationInventor: Tetsuo Okuno
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Patent number: 7040011Abstract: A wiring substrate is manufactured in short TAT. Wirings of the wiring substrate are formed by an exposure treatment using a photomask which has shade patterns each containing at least nano particles and a binder.Type: GrantFiled: January 15, 2002Date of Patent: May 9, 2006Assignee: Renesas Technology Corp.Inventors: Toshihiko Tanaka, Masaharu Kubo, Takashi Hattori
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Patent number: 7040013Abstract: A method, system, and product for routing nets along a printed circuit board through an obstacle field and a circuit board having traces produced in accordance with the routed nets is disclosed. The nets are routed by identifying a general path for each of a pair of nets between adjacent rows of obstacles within an obstacle field, selectively lengthening at least one of the nets by shifting at least one portion of the net toward a position between adjacent pads in one of the rows, thereby increasing the length of the net, and selectively increasing the mean spacing between the pair of nets by shifting at least one portion of at least one net of the pair away from the other net of the pair toward a position between adjacent pads in one of the rows, thereby reducing cross-talk between the nets.Type: GrantFiled: March 17, 2003Date of Patent: May 9, 2006Assignee: Unisys CorporationInventors: Daniel A. Jochym, Christian E. Shenberger, Robert Fix
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Patent number: 7036218Abstract: A method for producing a wafer interposer (210) for use in a wafer interposer assembly is disclosed. The wafer interposer (210) is produced by attaching solder bumps (140) to a lower surface of a support (120). First electrical terminals (130) are attached to an upper surface of the support (120) and substantially correspond to the solder bumps (140). First electrical pathways are provided that passes through the support (120) and connect the solder bumps (140) to the first electrical terminals (130). Second electrical terminals (310) are attached to the upper surface of the support (120). Second electrical pathways (320) connect the first electrical terminals (130) to the second electrical terminals (310).Type: GrantFiled: February 24, 2003Date of Patent: May 2, 2006Assignee: Eaglestone Partners I, LLCInventor: John L. Pierce
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Patent number: 7036221Abstract: A method of manufacturing a semiconductor mounting board includes providing a base member and linear conductive members formed of metallic wires. The conductive members are constructed so that they extend linearly between a semiconductor element-mounting face and a circuit board-mounting face of a base member, and are integrally molded within the base member. For this purpose, a resin material for forming the base member is injected into a mold wherein the conductive members are linearly arranged beforehand.Type: GrantFiled: February 20, 2004Date of Patent: May 2, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaaki Higashida, Koichi Kumagai, Takahiro Matsuo
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Patent number: 7030033Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.Type: GrantFiled: September 16, 2003Date of Patent: April 18, 2006Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
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Patent number: 7028377Abstract: A method of producing an ink jet recording head, which includes (1) fixing a passage unit in which a nozzle pate having a nozzle opening, a spacer forming a common ink chamber, and an elastic plate having a thick portion abutting against an end of a piezoelectric vibrating element are stacked, to an opening of a frame having an overhang portion which overhangs to a vicinity of the thick portion, (2) inserting a vibrating element unit into the frame, the vibrating element unit being configured by fixing piezoelectric vibrating elements operating in a longitudinal vibration mode to a fixing substrate, and (3) injecting an adhesive into a groove formed in a region opposing the fixing substrate of the frame.Type: GrantFiled: April 30, 2003Date of Patent: April 18, 2006Assignee: Seiko Epson CorporationInventors: Shinji Yasukawa, Minoru Usui, Takahiro Naka, Tsuyoshi Kitahara, Noriaki Okazawa, Hideaki Sonehara
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Patent number: 7022251Abstract: Disclosed is a method for forming a conductor on a dielectric. The method commences with the deposition of a conductive thickfilm on the dielectric, followed by a “subsintering” of the conductive thickfilm. Either before or after the subsintering, the conductive thickfilm is patterned to define at least one conductor. After subsintering, the conductive thickfilm is etched to expose the conductor(s), and the conductor(s) are then fired. A brief chemical etch may be used after the final firing step if improved wire-bondability is required.Type: GrantFiled: June 19, 2003Date of Patent: April 4, 2006Assignee: Agilent Technologies, Inc.Inventors: John F. Casey, Lewis R. Dove, Ling Liu, James R. Drehle, R. Frederick Rau, Jr., Rosemary O. Johnson
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Patent number: 7022609Abstract: A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode in a semiconductor substrate in which a device and a wiring pattern have been already fabricated. This manufacturing method includes the steps of forming a first silicon oxide film 12 on a principal surface of the semiconductor substrate 11, forming a small hole 13 through the semiconductor substrate 11 from the opposite the step to reach to the first silicon oxide film 12, covering the inside of the small hole 13 with the second silicon oxide film 14, forming a first thin metal film 15 and a second thin metal film 16 on the first silicon oxide film 12, partially removing the first silicon oxide film 12 corresponding to the end of the small hole 13, and filling the small hole 13 with the conductive material to form a through hole electrode 17.Type: GrantFiled: August 25, 2003Date of Patent: April 4, 2006Assignees: Fujikura Ltd., Olympus Optical Co., Ltd.Inventors: Satoshi Yamamoto, Takashi Takizawa, Tatsuo Suemasu, Masahiro Katashiro, Hiroshi Miyajima, Kazuya Matsumoto, Toshihiko Isokawa
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Patent number: 7013563Abstract: A method for testing opening patterns in an active area of a PCB wherein two arrays of test patterns of apertured pads are analyzed following drilling therethrough in accordance with a specified manner. Specifically, the outer patterns are first tested and if failure results in one or more of said patterns, an inner array of patterns closer to the active area are then tested and, significantly, only the respective test pattern nearest the associated array of openings is used to determine whether said array of openings meets the designated spacing criteria.Type: GrantFiled: July 11, 2003Date of Patent: March 21, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventor: John Durkot
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Patent number: 7014784Abstract: In one embodiment, a plurality of thickfilm dielectric layers are printed on a substrate, with each successive layer being printed over a previous layer, and with each layer having sloped walls. After printing a first subset of the plurality of thickfilm dielectric layers, a first conductive thickfilm is printed over at least the walls of the first subset of dielectric layers. Then, after printing a second subset of the plurality of thickfilm dielectric layers, a second conductive thickfilm is printed over the second subset of dielectric layers (with the first and second conductive thickfilms being electrically coupled).Type: GrantFiled: March 3, 2004Date of Patent: March 21, 2006Assignee: Agilent Technologies, Inc.Inventors: Lewis R. Dove, John F. Casey
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Patent number: 7010837Abstract: A method for manufacturing an electronic component includes the steps of forming an electrode layer including ?-tungsten on a substrate at a substrate temperature of about 100° C. to about 300° C. by a sputtering process, processing the electrode layer so as to have a desired shape, and heat-treating the electrode layer. An electronic component includes a substrate and an electrode layer that is disposed on the substrate directly or indirectly, includes ?-tungsten, and has a specific resistance of about 15 ??.cm or less and a warpage of about 120 ?m or less. A surface acoustic wave filter includes a piezoelectric substrate and an electrode layer, disposed on the piezoelectric substrate, including ?-tungsten.Type: GrantFiled: April 9, 2003Date of Patent: March 14, 2006Assignee: Murata Manufacturing Co., Ltd.Inventors: Eiichi Takata, Yasuji Yamamoto, Genji Inuidani, Michio Kadota
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Patent number: 7008549Abstract: Composite member 2 consisting of ceramic insulator substrate 3 and two metal layers 4A and 4B such as aluminum sheets is subjected to milling in order to remove the unwanted areas of metal layer 4A (where inter-element spacings are to be formed). In order to suppress cracking due to substrate warpage, a small bottom portion of 4A is left intact as residual metal layer 4Aa which is preferably removed by etching. Milling is performed after thin-film layer of etching resist 5 is applied to the surface of metal layer 4A. By milling in two stages, a step is formed at the bottom of lateral sides of a pattern element to make a skirt which contributes to reducing external stresses.Type: GrantFiled: January 29, 2004Date of Patent: March 7, 2006Assignee: Dowa Mining Co., Ltd.Inventors: Masahiro Hara, Hideyo Osanai
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Patent number: 7007375Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.Type: GrantFiled: March 31, 2003Date of Patent: March 7, 2006Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, David J. Corisis, Tyler J. Gomm
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Patent number: 7003875Abstract: A method for manufacturing a piezo-resonator including: a first step of forming an upper electrode layer 20 on the piezoelectric film 14, a second step of coating the upper electrode layer 20 with a resist 21 and of performing patterning on the resist so as to have a shape of the upper electrode, a third step of masking the patterned resist 21 and removing the upper electrode layer 20 other than masked portions and forming two or more first upper electrodes 15a, a fourth step of removing the resist 21, a fifth step of coating the first upper electrodes 15a with a resist and performing patterning on the resist so that the first upper electrodes 15a are partially exposed, a sixth step of etching each of the exposed first upper electrodes 15a by a specified thickness to form a second upper electrode 15b, and a seventh step of removing the resist 22.Type: GrantFiled: October 21, 2004Date of Patent: February 28, 2006Assignee: TDK CorporationInventors: Masaaki Imura, Kenji Inoue, Eiju Komuro, Hisatoshi Saitou
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Patent number: 7003857Abstract: An ink-jet printing head comprises: a pressurizing chamber substrate having first and second sides opposing each other; a plurality of pressurizing chambers formed on the first side of the pressurizing chamber substrate; channels formed on the second side of the pressuring chamber substrate to be opposite to the pressuring chambers, respectively; oscillating plate films for pressurizing ink within the respective pressurizing chambers; and piezoelectric thin-film elements, each having upper and lower electrodes and a piezoelectric film sandwiched between the upper and lower electrodes, the piezoelectric thin-film being formed in the channel, wherein at least the upper electrode is formed to have a narrower width than that of the pressurizing chamber. And a method for producing the ink-jet head.Type: GrantFiled: June 22, 2000Date of Patent: February 28, 2006Assignee: Seiko Epson CorporationInventors: Masato Shimada, Tetsushi Takahashi, Tsutomu Nishiwaki, Tsutomu Hashizume
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Patent number: 6996883Abstract: A transducer is tuned to a desired impedance by building piezoelectric assemblies of multiple layers, each layer acting as a parallel capacitor. Piezoelectric layers are preferably constructed by plating or otherwise placing a conducting perimeter around a piezoelectric substrate. Gaps are suitably formed in the conducting layer by dicing or otherwise to form distinct electrical conducting regions on each layer. Piezoelectric layers are then suitably placed such that positive and negative conducting regions on each layer contact positive and negative regions on other layers. Layers are suitably joined by epoxy or by any other joining technique.Type: GrantFiled: January 24, 2003Date of Patent: February 14, 2006Assignee: General Electric CompanyInventors: Sanjay Chandran, David Chartrand
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Patent number: 6996901Abstract: A production method of a wired circuit board can prevent corrosion of a first thin metal film inwardly of a conductor layer, due to the forming of an undercut portion caused by a skirt portion of a plating resist. A first thin metal film is formed on an insulating base layer. A plating resist is formed in a reversal pattern to a wiring circuit pattern on the first thin metal film, and a conductor layer is formed in the wiring circuit pattern on the first thin metal film exposed from the plating resist. Thereafter, the plating resist is removed and, then, a second thin metal film is formed on the conductor layer and first thin metal film. Thereafter, the second thin metal film and then all portions of the first thin metal layer, except portions thereof where the conductor layer is formed, are removed.Type: GrantFiled: November 19, 2004Date of Patent: February 14, 2006Assignee: Nitto Denko CorporationInventors: Mitsuru Honjo, Toshiki Naito
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Patent number: 6997781Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.Type: GrantFiled: April 4, 2002Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventors: Dinesh Chopra, Gundu Sabde
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Patent number: 6996884Abstract: In a method for manufacturing a piezo-electric vibrator, a vibrator is provided having a vibrator piece and a frame surrounding a periphery of the vibrator piece. A first exciting electrode is formed on the vibrator piece. A weight is disposed on the vibrator piece in spaced-apart relation to the first exciting electrode. A characteristic of the vibrator is then adjusted. The first exciting electrode is removed and a metal film is formed on a surface of the vibrator. The metal film is patterned and a second exciting electrode is formed on the vibrator piece.Type: GrantFiled: February 5, 2003Date of Patent: February 14, 2006Assignee: Seiko Instruments Inc.Inventors: Kiyoshi Aratake, Masayoshi Shiraishi
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Patent number: 6990734Abstract: Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21?) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21?), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21?) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).Type: GrantFiled: October 2, 2002Date of Patent: January 31, 2006Assignee: Motorola, Inc.Inventors: Jeffrey A. Underwood, John K. Arledge, Thomas J. Swirbel, Joaquin Barreto
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Patent number: 6981319Abstract: Devices capable of protecting electronic components during the occurrence of a disturbance event using printed circuit board manufacturing techniques. A three (3) layer structure is formed comprising a polymer-based formulation sandwiched between two electrode layers. The devices can be manufactured in panel form providing high quantities of devices which can be removed from the panel and applied directly to the component to be protected. Desired patterns can be formed on either one of the electrode layers by photo-etch techniques thereby providing a process that can be tailored to a large number of applications.Type: GrantFiled: February 13, 2003Date of Patent: January 3, 2006Inventor: Karen P. Shrier
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Patent number: 6977345Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.Type: GrantFiled: January 8, 2002Date of Patent: December 20, 2005Assignee: International Business Machines CorporationInventors: Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser, David B. Stone
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Patent number: 6973703Abstract: A method for manufacturing an ink-jet head, including forming a mark for indicating the positions of pressure chambers on a surface of a passage unit; preparing a member containing a piezoelectric sheet on which a common electrode is supported; attaching the member to the surface of the passage unit; and forming individual electrodes, based on the mark, on a face of the member facing the direction opposite to the attached face thereof to the passage unit.Type: GrantFiled: February 19, 2003Date of Patent: December 13, 2005Assignee: Brother Kogyo Kabushiki KaishaInventors: Atsuo Sakaida, Yuji Shinkai, Takeshi Asano, Atsushi Hirota
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Patent number: 6973719Abstract: A method of making a thermal management material for a circuit board panel comprising the steps of cutting a thermally conductive, rigid substrate from a larger sheet of heat conducting material, degreasing the thermally conductive substrate, mechanically abrading at least one surface of the thermally conductive substrate, acid cleaning the at least one abraded surface of the thermally conductive substrate, rinsing the thermally conductive substrate, passivating the at least one abraded surface of the thermally conductive substrate to render the at least one surface chemically inert, rinsing the thermally conductive substrate, drying the thermally conductive substrate and baking the thermally conductive substrate at an elevated temperature.Type: GrantFiled: November 22, 2003Date of Patent: December 13, 2005Inventors: Rati M. Patel, Roy English
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Patent number: 6971160Abstract: A hybrid integrated circuit fabrication method in which an insulating substrate member and its metallic substrate carrier are made to be mating with precision through use of computer controlled machining performed on each member. A combination of disclosed specifically tailored software and commercially available software are used in the method to generate code for controlling a precision milling machine during the fabrication of substrate and substrate carrier members. The method for precision mating of substrate and substrate carrier enable disposition of a precision recess in the substrate carrier and the location of recess pillars and pedestals (the latter being for integrated circuit die mounting use) at any carrier recess location desirable for electrical, thermal or physical strength reasons.Type: GrantFiled: January 3, 2002Date of Patent: December 6, 2005Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Ryan J. Welch, Tony K. Quach
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Patent number: 6971165Abstract: An improved method for manufacturing a matching pair of electrodes comprises the steps of: fabricating a first electrode with a substantially flat surface; depositing islands of an oxidizable material over regions of the surface; depositing a layer of a third material over the surface of the first electrode to form a second electrode; separating the first electrode from the second electrode; oxidizing the islands of oxidizable material, which causes the islands to expand; bringing the upper electrode and the lower electrode into close proximity, whereupon the expanded island of oxidizable material touches the upper surface and creates an insulating gap between the two surfaces, thereby forming a matching pairs of electrodes.Type: GrantFiled: April 17, 2003Date of Patent: December 6, 2005Assignee: Borealis Technical LimitedInventor: Avto Tavkhelidze
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Patent number: 6964087Abstract: A method for manufacturing the dielectric ceramic layer and the internal polar layer of the multiple layer ceramic capacitor by the vacuum sputtering process in which the dielectric ceramic layer and the internal polar layer of the MLCC has a finest thinness of 1˜5 ?m for the dielectric ceramic layer and 0.1 ˜0.5 ?m for the internal polar layer. Comparing the size and the voltage resistance with the MLCC formed by the traditional dot blade method—both the dry process and the wet process, the MLCC produced by the vacuum sputtering process is finer and thinner; comparing the layer number and the capacitance with the MLCC formed by the tradition dot blade method, the MLCC produced by the vacuum sputtering process has greater layer number and larger capacitance in the same size. When comparing with the layer number and the capacitance, the MLCC formed by the vacuum sputtering process has lesser layers.Type: GrantFiled: May 26, 2004Date of Patent: November 15, 2005Inventor: Lei-Ya Wang
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Patent number: 6961981Abstract: The invention concerns a piezoelectric resonator piece of a piezoelectric resonator having electrode patterns for forming exciting electrodes each of which is composed of an under a metal layer. Each of the electrode patterns for forming conduction electrodes is composed of the under metal layer except the curved or bent portions of the sides of the piezoelectric resonator piece and each of the electrode patterns in these portions are composed of the under metal layer and a gold electrode layer. It is thus possible to provide a piezoelectric resonator in which, even when noble metal layers are partially removed for increasing adhesion of surface protecting films, exciting electrodes are not brought into an open state between the upper side and the lower side of a piezoelectric resonator piece.Type: GrantFiled: September 22, 2003Date of Patent: November 8, 2005Assignee: Seiko Epson CorporationInventors: Mitsuru Nagai, Yoshiharu Kasuga
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Patent number: 6959490Abstract: Disclosed are a method f manufacturing a silicon device and a method of manufacturing a liquid jet head, which are capable of surely preventing damage of a piezoelectric element in manufacturing. In forming a thin-film pattern on one surface of a silicon wafer 100, a first moisture permeation preventive layer 96, which is so as to surround the entire thin-film pattern of the silicon wafer 100, is formed in the same layer as a first conductive layer 96 on the silicon wafer 100, a second moisture permeation preventive layer 114 having a narrower width than the first moisture permeation preventive layer 96 is formed in the same layer as an insulation layer 100 on the first moisture permeation preventive layer 96, and a third moisture permeation preventive layer 121 is formed in the same layer as a second conductive layer 120 on the second moisture permeation preventive layer 114 so as to cover the second moisture permeation preventive layer 114. Thus, a moisture permeation preventive pattern 130 is formed.Type: GrantFiled: August 8, 2003Date of Patent: November 1, 2005Assignee: Seiko Epson CorporationInventor: Yoshinao Miyata
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Patent number: 6952871Abstract: It consists of making a first engraving over a first face of a panel of electro-conducting material to form some reliefs and depressions corresponding to future tracks and intermediate tracks; subjecting said first face to a black oxide treatment (40); applying a layer of an adhesive material over said first face previously engraved and treated with black oxide; applying by injection moulding a dielectric material (20) over said previously engraved first face, treated and with the adhesive applied, covering said reliefs and filling said depressions; and carrying out a second selective engraving over a second face, opposite to the first one, of the mentioned panel to eliminate the material thereof corresponding to said future intermediate tracks, so that some finished tracks (16) remain insulated from each other, partially embedded on a face of said dielectric material (20) and separated by intermediate tracks (18).Type: GrantFiled: December 31, 1999Date of Patent: October 11, 2005Assignee: Lear Automotive (EEDS) Spain, S.L.Inventors: José Antonio Cubero Pitel, Luis Ara Alonso
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Patent number: 6951047Abstract: A SAW element of the present invention includes a plurality of inter-digital transducer (IDT) electrodes on a piezoelectric substrate, grating reflector electrodes disposed on the sides of the IDT electrodes, and a plurality of pad electrodes led from the IDT electrodes and the grating reflector electrodes. A plurality of the pad electrodes includes isolated pad electrodes not directly opposed to the outer periphery of the SAW element, and adjacent pad electrodes directly opposed to the outer periphery thereof A connecting electrode between the isolated pad electrode and the adjacent pad electrode is removed by etching at least before dicing in order to prevent discharge from occurring due to pyroelectricity, and to prevent the electrodes from being damaged.Type: GrantFiled: July 30, 2003Date of Patent: October 4, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Muneko Tomioka, Kiyoharu Yamashita, Mitsuhiro Furukawa
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Patent number: 6949470Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.Type: GrantFiled: September 17, 2003Date of Patent: September 27, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
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Patent number: 6944922Abstract: A of forming an acoustic resonator of one inventive aspect includes depositing at least one primer layer, depositing an electrode layer containing Molybdenum on the upper surface of the primer layer, and depositing a layer may piezoelectric material on the uppermost electrode layer. The primer layer may included a generally crystalline material, the upper surface of which has an atomic spacing that matches the atomic spacing of the electrode layer to within about 15% and is not of cubic crystalline form.Type: GrantFiled: August 11, 2003Date of Patent: September 20, 2005Assignee: Trikon Technologies LimitedInventors: Christine Janet Shearer, Carl David Brancher, Rajkumar Jakkaraju
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Patent number: 6941648Abstract: A method for making a printed wiring board reduced in weight by reducing the size and the thickness of a substrate in its entirety. The printed wiring board includes a rigid substrate 2, comprised of a core material 11 at least one side of which carries a land 23, and flexible substrates 3, 4, 5, and 6 comprised of core materials 33, 36 on at least one surface of which a bump 32 for electrical connection to the land 38 is formed protuberantly. The rigid substrate 2 and the flexible substrates 3 to 6 are molded as one with each other, with the interposition of an adhesive in-between, so that the land and the bump face each other.Type: GrantFiled: February 12, 2003Date of Patent: September 13, 2005Assignee: Sony CorporationInventors: Kazuhiro Shimizu, Nobuo Komatsu, Soichiro Kishimoto