With Selective Destruction Of Conductive Paths Patents (Class 29/847)
  • Publication number: 20040158979
    Abstract: A method of manufacturing a semiconductor mounting board includes providing a base member and linear conductive members formed of metallic wires. The conductive members are constructed so that they extend linearly between a semiconductor element-mounting face and a circuit board-mounting face of a base member, and are integrally molded within the base member. For this purpose, a resin material for forming the base member is injected into a mold wherein the conductive members are linearly arranged beforehand.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 19, 2004
    Inventors: Takaaki Higashida, Koichi Kumagai, Takahiro Matsuo
  • Publication number: 20040154162
    Abstract: A method for fabricating a multi-layer printed circuit board can include forming an etching resist layer on a first metal layer having plating grooves that selectively expose the first metal layer, forming a plated layer at the surface of the first metal layer exposed by the plating groove through a plating process to form connection protrusion, removing the etching resist layer, forming an insulation layer at the first metal layer and positioning a second metal layer at the surface of the insulation layer coupled to an end portion of the connection protrusion. By forming the connection protrusion through the plating process, a loss of material can be reduced and a strength of the connection protrusion can be increased. Further, a complexity of the fabrication process is reduced to reduce costs and increase productivity.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Applicant: LG Electronics Inc.
    Inventors: Sung-Gue Lee, Jung-Ho Hwang, Joon-Wook Han, Sang-Min Lee, Tae-Sik Eo, Yu-Seock Yang
  • Patent number: 6772514
    Abstract: A method of machining a glass substrate by using a laser, in which a low-permittivity, low-dielectric-loss glass substrate capable of coping with mass production processes is made applicable as the substrate of a high-frequency circuit intended for microwave and millimeter-wave bands in particular. For that purpose, a glass substrate is provided in which the amount of air bubbles in glass is arbitrarily controlled to improve the workability of the substrate itself. Then, the glass substrate is machined while being irradiated with a pulsed laser for a plurality of times, thereby improving the machining shape of the glass substrate. Since glass substrates which are typically difficult to machine can be easily applied to the fabrication of high-frequency circuits, it becomes possible to supply high-performance circuits and apparatuses widely to the public.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Ogura, Yuji Hashidate, Hiroyoshi Yajima, Yoshikazu Yoshida
  • Patent number: 6772515
    Abstract: To provide a method of producing a multilayer printed wiring board that can be intended to have low-profile, light-weight and high-density wiring of a printed wiring board, and a multilayer printed wiring board produced by the method of producing a multilayer printed wiring board, the double-sided substrate is produced by the steps of forming an insulating resin layer on a metal foil; of forming a via hole in the insulating resin layer; of forming a first circuit pattern on the insulating resin layer and forming a conductive layer in the via hole, by plating; and of etching the metal foil to form it into a second circuit pattern. The produced double-sided substrate is used as a core substrate for producing multilayer printed wiring board by a laminate-en-bloc or a build-up method.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 10, 2004
    Assignees: Hitachi, Ltd., Nitto Denko Corporation
    Inventors: Tokihito Suwa, Atsushi Tanaka, Satoshi Tanigawa, Hirofumi Fujii, Kazunori Mune
  • Patent number: 6772512
    Abstract: A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in the substrate to be substantially raised to an elevated flat surface where a groove is then formed to surround the exit of the vent hole. During a molding process, when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the groove in the elevated flat surface over the dummy pad, thereby preventing it from flashing to nearby solder-ball pads.
    Type: Grant
    Filed: January 13, 2001
    Date of Patent: August 10, 2004
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Chou Tsai, Jen-Yi Tsai
  • Patent number: 6769177
    Abstract: A method of producing an ink-jet recording head using ion milling is provided. The method includes the steps of forming a piezoelectric layer subsequent to an electrode layer on a substrate by using a thin-film deposition technology, forming an energy-generating element for generating energy for ink ejection by etching the electrode layer and the piezoelectric layer simultaneously by ion milling, and removing a fence formed by deposits of mixed fine powders including those etched off the electrode layer and the piezoelectric layer.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 3, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Shuji Koike, Yoshiaki Sakamoto, Tomohisa Shingai, Seigen Otani, Toshihiko Osada, Kazuaki Kurihara
  • Patent number: 6769158
    Abstract: A piezo-electric printhead is formed from a first piezo-electric actuator disposed parallel to a second piezo-electric actuator. The first and second piezo-electric actuators have a shared inner electrode disposed between them, a first control electrode disposed on an outside surface of the first piezo-electric actuator and a second control electrode disposed on an outside surface of the second piezo-electric actuator. The actuators are formed from a block having a piezo-electric layer disposed on a ceramic base, in which the piezo-electric layer has two parallel, distinct electrode patterns embedded therein in the form of a metal paste.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 3, 2004
    Assignee: Illinois Tool Works, Inc.
    Inventors: Jean-Marie Gutierrez, Hongsheng Zhang
  • Patent number: 6768316
    Abstract: A laminate comprising an insulation layer sandwiched between a pair of electrically conductive layers is prepared for electrical insulation testing by using a laser to remove a strip from at least one of the conductive layers proximate the edge of the laminate to electrically isolate a central, bulk portion of the conductive layer from the edges of the laminate. Conductive material that may be smeared across an edge of the laminate will not therefore provide an electrical short between the portion of the conductive layer surrounded by the slot and the second conductive layer on the opposite side of the insulation layer.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: July 27, 2004
    Assignee: Polyclad Laminates, Inc.
    Inventors: Yeo Kong Hoo, Christopher Vernon Smith
  • Patent number: 6766579
    Abstract: A method for manufacturing an ink jet head, which is provided with a discharge port member having discharge ports arranged for discharging ink, comprises the step of forming the discharge port member by a first photosensitive resin layer, and a second photosensitive resin layer having water-repellency, which is laminated on the first photosensitive resin layer, and the step of giving pattern-exposure and development to these layers for the formation of a structure having the portion where both the first photosensitive resin layer and the second photosensitive resin layers are removed, and the portion where the second photosensitive resin layer is partially removed.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: July 27, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Norio Ohkuma
  • Publication number: 20040139600
    Abstract: A process for massively producing tape type flexible printed circuits is provided. The steps of pressing, etching and insulating are executed on a flexible insulation tape in reel-to-reel fashion. Thereafter, the flexible insulation tape is punched to form sprocket holes and cut along the parallel lines where the sprocket holes arrange on to become several winds of narrower flexible circuit tapes. Each flexible circuit tape has tape type flexible printed circuits and sprocket holes at two sides.
    Type: Application
    Filed: January 12, 2004
    Publication date: July 22, 2004
    Applicant: MEKTEC CORPORATION
    Inventors: Jung-Chou Huang, Wen-Yann Su, Kuei-Hao Pang, Grow-Hao Lo, Che-Hui Chu
  • Patent number: 6757968
    Abstract: A circuit assembly has a heat sink assembly and a chip scale package assembly. The chip scale package assembly has an integrated circuit die coupled to a first printed wiring board. The heat sink assembly has an integrated circuit die coupled to a second printed wiring board. Preferably, the heat sink assembly and the chip scale package assembly are assembled separately then assembled together. The circuit pads on the first printed wiring board correspond with circuit pads on the second printed wiring board. The circuit pads may be coupled together by solder or adhesive bonding. The circuit pads on the first printed wiring board may have solder balls formed of high temperature solder that do not melt when the heat sink assembly is assembled with chip scale package assembly. The solder balls allow chip scale package assembly to maintain a predetermined distance from the circuit pads on the second printed wiring board.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: July 6, 2004
    Assignee: The Boeing Company
    Inventors: Ching P. Lo, Daniel A. Huang, Pete Hudson
  • Patent number: 6757970
    Abstract: A multicontact electrode array suitable for implantation in living tissue includes a distal end having multiple spaced-apart ring contacts or a pattern of spaced-apart electrode contacts carried on a flexible carrier. Each electrode contact is resistance welded to a respective wire that is wound helically inside a silicon tube. The center of the helix defines a lumen wherein a positioning stylet, or other suitable positioning tool, may be removably inserted when the electrode array is implanted. The electrode array is made using a method that includes, as an initial step, winding lead wires around a suitable mandrel forming a helix configuration. Next, a non-conductive silicone tube jacket is placed around the wound wires, exposing the distal lead ends of the wires at a distal end of the tube. A welding process is then used to bond each wire tip to a corresponding metal electrode contact which has been preassembled by resistance welding to a metal foil structural carrier.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: July 6, 2004
    Assignee: Advanced Bionics Corporation
    Inventors: Janusz A. Kuzma, William Vanbrooks Harrison, Lani A. Smith
  • Patent number: 6759596
    Abstract: The invention provides multilayer circuit boards and methods for formation of a sequential build circuit board. Among other things, glass fiber reinforced copper clad epoxy substrates, required to provide strength or rigidity to prior boards, are not required for preferred circuit boards of the invention.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: July 6, 2004
    Assignee: Shipley Company
    Inventors: James G. Shelnut, Charles R. Shipley, Robert L. Goldberg
  • Publication number: 20040124468
    Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.
    Type: Application
    Filed: September 8, 2003
    Publication date: July 1, 2004
    Inventors: Philippe Coronel, Christophe Regnier, Francois Wacquant, Thomas Skotnicki
  • Publication number: 20040123449
    Abstract: The invention seeks to provide a thin-film coil of high space factor and of a low resistance in an easy and reliable manner. In a thin-film coil in which a first coil and a second coil each having a desired number of winding are electrically connected in series and mounted in the thin-film coil, the second coil is formed between winding portions of the first coil on substantially the same plane, and only an insulating film is interposed between the first coil and the second coil.
    Type: Application
    Filed: December 16, 2003
    Publication date: July 1, 2004
    Inventor: Teruo Inaguma
  • Patent number: 6754952
    Abstract: A process facilitates manufacturing a multiple layer wiring board having therein a thin-film capacitor The process includes: forming a metallic film layer having a barrier metal layer and a metal layer to be sequentially anode oxidized on an insulating layer first conductor pattern; covering a lower electrode forming region of the thin film capacitor in the first conductor pattern with a first resist film; etching to remove an uncovered portion of the metallic film layer; removing the first resist film and covering the first conductor pattern, except for part of the metallic film layer, with a second resist film; forming an anodic oxidation film on the exposed metallic film layer; removing the second resist film and attaching an adherence layer and a metal seed layer, sequentially, on the anodic oxidation film end on the first conductor pattern; and forming an upper electrode second conductor pattern on the anodic oxidation film.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 29, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akihito Takano, Akira Fujisawa, Akio Rokugawa
  • Patent number: 6751847
    Abstract: A detection coil for use in nuclear resonance magnetic (NMR) spectroscopy and a method of manufacture thereof. At least two film layers of material are deposited on an outer surface of a cylindrical tube of dielectric material. The layers are patterned to form a solenoid on the tube. At least one of the deposited materials is a conductor.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: June 22, 2004
    Assignee: FSU Research Foundation, Inc.
    Inventors: William W. Brey, Susan D. Allen
  • Patent number: 6745463
    Abstract: The present invention relates to a manufacturing method of rigid flexible printed circuit board. Inner layer circuit are etched on two side of a flexible basefilm and a flat cable for connecting the inner layer circuit on lateral sides is disposed on the middle part thereof. Then layer of outer copper foil without bondfilm made of reinforced fiber on the bottom side thereof is laminated on both sides of the flexible basefilm respectively and drilled a number of through holes on connecting points of preset circuitry thereof. Subsequently, each through hole is metalized and plated for electrically connecting outer copper foil and inner layer circuit on flexible basefilm by means of such plated layer. The copper foil on the top of the flat cable that is on the middle of the flexible basefilm is removed and out layer circuit is made on outer copper foil. At last, the outer layer circuit is covered by solder resist mask.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: June 8, 2004
    Assignee: Unitech Printed Circuit Board Corp.
    Inventor: Cheng-Hsien Chou
  • Patent number: 6742250
    Abstract: A method for manufacturing a wiring substrate 1 includes a conductor layer forming step for forming a second conductor layer 29, through electroless copper plating and copper electroplating, on a first resin dielectric layer 7, which is surface-roughened to a predetermined roughness and to which palladium adheres; a cyan treatment step for cleaning a substrate 41 on which the second conductor layer 29 is formed, using a cyanide-containing solution; and an upper resin dielectric layer forming step for forming a second resin dielectric layer 9 on the first resin dielectric layer 7 and the second conductor layer 29 of the cyan-treated substrate 41.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 1, 2004
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Kazuyuki Takahashi
  • Patent number: 6739048
    Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
  • Patent number: 6739040
    Abstract: The present invention relates to a method of manufacturing a multilayered printed wiring board by a buildup system in which a conductive circuit layer and an insulating layer are alternately piled up. This method also involves using an adhesive film to facilitate manufacturing the multilayered printed wiring board having excellent surface smoothness at satisfactory yields.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: May 25, 2004
    Assignee: Ajinomoto Co., Inc.
    Inventors: Shigeo Nakamura, Tadahiko Yokota
  • Patent number: 6739041
    Abstract: A method 10, 90 for making a multi-layer electronic circuit board 82, 168 including the steps of forming at least one protuberance 15, 100 upon an electrically conductive member 12, 92 and adding additional electrically conductive layers of material 34, 56, 58, 104, 114, 138, 140 to the member 12, 92 while selectively extending the protuberance 15, 100 within the layers 82, 168, thereby forming a circuit board 82, 168. A portion of the formed circuit board may be etched in order to selectively create air-bridges 86 or interconnection portions 164.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 25, 2004
    Assignee: Visteon Global Tech., Inc.
    Inventors: Bharat Z. Patel, Jay D. Baker, Mohan R. Paruchuri
  • Patent number: 6739047
    Abstract: A package for an electronic component includes a metal support substrate having a pattern of openings therethrough and a body of an insulating material, such as glass or ceramic, on and bonded to the surface of the support substrate. The body is formed from a plurality of layers of an insulating material, and conductive vias extending through the plurality of layers to the support substrate; said insulating body having an opening therein, an electronic component directly mounted in said opening to the patterned base plate. The base plate can be cut into one or more modules and directly soldered to a motherboard having additional devices mounted thereon.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 25, 2004
    Assignee: Lamina Ceramics, Inc.
    Inventors: Mark Stuart Hammond, Ellen Schwartz Tormey, Barry Jay Thaler, Leszek Hozer, Hung-tse Daniel Chen, Bernard Dov Geller, Gerard Frederickson
  • Patent number: 6739039
    Abstract: Disclosed is a manufacturing method of a circuit of a printed circuit board using a dry film resist in forming a circuit pattern on a copper overlaid laminate as a normal printed circuit board, in which a modification of the manufacturing process can enhance the resolution and fine weldability of the resist to realize a fine structure of the circuit pattern. The method includes: laminating the dry film resist on the top surface of the printed circuit board; exposing the dry film resist to ultraviolet (UV) radiations using a photomask in which a desired circuit pattern is formed; annealing the resulting material of the previous step with infrared (IR) radiations; and removing unexposed areas of the resist by development.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: May 25, 2004
    Assignee: Kolon Industries Inc.
    Inventors: Jun Hyeak Choi, Kook Hyeon Han, Jan Hun Kim
  • Publication number: 20040090500
    Abstract: The present invention provides a piezoelectric thin film element with superior piezoelectric properties in which the condition of the crystal of the piezoelectric thin film is appropriately controlled, and a manufacturing method thereof, as well as a inkjet recording head, inkjet printer, or other liquid ejecting apparatus employing the same. The piezoelectric thin film element 40 comprises a top electrode 44, a bottom electrode 42, and a piezoelectric thin film 43 formed between the top electrode 44 and the bottom electrode 42, wherein the piezoelectric thin film 43 is structured so as to comprise a first layer 431 located nearest to the bottom electrode and second layers (433-436) that are located nearer to the top electrode than the first layer and that each have a thickness greater than that of the first layer 431.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 13, 2004
    Applicant: Seiko Epson Corporation
    Inventor: Masami Murai
  • Publication number: 20040091821
    Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.
    Type: Application
    Filed: September 17, 2003
    Publication date: May 13, 2004
    Applicant: International Business Machines Corporation
    Inventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
  • Patent number: 6729023
    Abstract: A method for making a multi-layer circuit board 116 having apertures 96, 98 which may be selectively and electrically isolated from electrically grounded member 46 and further having selectively formed air bridges and/or crossover members 104 which are structurally supported by material 112. Each of the apertures 96, 98 selectively receives electrically conductive material 114.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: May 4, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Achyuta Achari, Andrew Zachary Glovatsky, Robert Edward Belke, Brenda Joyce Nation, Delin Li, Lakhi N. Goenka, Mohan R. Paruchuri, Robert Joseph Gordon, Thomas Bernd Krautheim
  • Patent number: 6729002
    Abstract: A pressurizing chamber 1 is formed as a recess by half etching of a silicon single-crystal substrate 2. A nozzle communicating hole 6 through which the pressurizing chamber 1 is connected to a nozzle opening 5 is formed as a through hole which is smaller in width than the pressurizing chamber 1. The pressurizing chamber 1 is connected to the nozzle opening 5 in the other face via the nozzle communicating hole 6 while reducing the volume of the pressurizing chamber 1 to a degree as small as possible. The silicon single-crystal substrate is used as a member constituting a spacer so that an ink drop of a reduced ink amount suitable for high density printing flies with high positioning accuracy.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: May 4, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Shinji Yasukawa, Minoru Usui, Takahiro Naka, Tsuyoshi Kitahara, Noriaki Okazawa, Hideaki Sonehara
  • Patent number: 6729024
    Abstract: A fabrication method for printed circuit boards is provided, in which a conductive layer of a conductive material is formed over an insulating layer. Portions of the conductive layer are removed to define a circuit pattern and at least one rail area. The rail area comprises conductive material arranged to span substantially the length of the circuit board adjacent to an associated edge thereof, and is electrically isolated from the circuit pattern. Portions of the conductive material within the rail area are eliminated such that no continuous length of conductive material extends substantially across the length of the circuit board.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Publication number: 20040078970
    Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 29, 2004
    Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
  • Publication number: 20040078968
    Abstract: Method for producing a printed circuit board on a substrate comprising five steps: (a) printing a predeterrnmined circuit pattern onto the substrate using a conductive material, (b) applying additional connection traces onto the substrate, (c) depositing a metal onto the printed circuit pattern by electroplating or electroforming a metal onto the substrate, (d) applying an adhesion and insulation glue layer over portions of the metal that comprises the desired circuit pattern, and (e) removing any undesired connection traces from the substrate.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 29, 2004
    Inventor: Sul Kay Wong
  • Patent number: 6725528
    Abstract: A photosensitive material is coated on an insulating material (13) stacked on a substrate (1) (FIG. 16A), and exposed and developed using a mask having a light-shielding film capable of controlling a light transmittance from 100% to 0% annularly and continuously to form a spiral photosensitive material (FIG. 16B). After conducting treatment at a high temperature, the insulating material under the photosensitive material is spirally formed by etching (FIG. 16C). A metal (12) is stacked on the substrate (FIG. 16D), and a photosensitive material is coated (FIG. 16E). The photosensitive material is exposed and developed using a mask having an annular light-shielding film with a light transmittance of 0% to leave the photosensitive material covering only the metal on the base of the spiral structure (FIG. 16F). After treatment at a high temperature is conducted and the metal exposed is etched (FIG. 16G), the photosensitive material is removed (FIG. 16H).
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: April 27, 2004
    Inventor: Takashi Nishi
  • Patent number: 6725513
    Abstract: A method for manufacturing a surface acoustic wave apparatus decreases a specific resistance of an electrode film by removing hydrogen occluded in the electrode film that is primarily composed of tantalum, so that the device properties are stabilized. An electrode film primarily composed of tantalum is formed on a piezoelectric substrate. Subsequently, this electrode film is heat-treated in a vacuum at a temperature of about 200° C. to about 700° C. for several hours. Thereafter, the electrode film is patterned so as to produce an interdigital electrode transducer.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: April 27, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masatoshi Nakagawa, Makoto Tose, Yoshihiro Koshido, Koji Fujimoto, Takeshi Nakao
  • Publication number: 20040074088
    Abstract: The invention relates a method for producing a multilayer circuit board (50) for a semiconductor device, comprising using a composite metal sheet (14) in which two metal sheets are combined, forming, on each side of the composite metal sheet, pads for connecting to a semiconductor element, the pads being made of a metal material which is substantially not etched by an etchant for the metal sheet, and an insulating layer having openings exposing the pads, forming, on the insulating layer, a wiring line layer (26) connected to the pads and having pads for connecting to another wiring line layer to be subsequently formed, subsequently fabricating a multilayer circuit board body (20) by necessary numbers of insulating layers and wiring line layers alternately formed, forming, on the outermost insulating layer of the multilayer circuit board body, an insulating layer provided with through-holes exposing pads for external connecting terminals, which are located on the outermost insulating layer, then dividing the c
    Type: Application
    Filed: November 14, 2003
    Publication date: April 22, 2004
    Inventors: Jyunichi Nakamura, Shunichiro Matsumoto, Tadashi Kodaira, Hironari Aratani, Takanori Tabuchi, Takeshi Chino, Kiyotaka Shimada
  • Patent number: 6722035
    Abstract: A method of manufacturing a substrate of an ink ejecting device in which an electrode formed at the bottom surface of an air chamber is removed with a diamond disk, without erroneously removing an electrode formed at an actuator forming the internal surface of the air chamber, by forming the air chamber with a width not smaller than that of an ink channel. The diamond disk for removing the bottom surface of the electrode of the air chamber may be the same as or have the same dimensions (width) as the ink channel.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: April 20, 2004
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Manabu Yoshimura
  • Publication number: 20040065471
    Abstract: A circuit board is made from a polymer material and includes a predetermined portion which has magnetic or dielectric or resistive properties. The portion with the magnetic or dielectric or resistive properties is made first and arranging within a mold. A polymer is then applied to the mold to form a board incorporating the portion with the magnetic or dielectric or resistive properties.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Applicant: The Hong Kong Polytechnic University
    Inventors: Chak Yin Tang, Ka Wai Eric Cheng
  • Patent number: 6715204
    Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: April 6, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Kiyotaka Tsukada, Masaru Takada, Kenji Chihara
  • Publication number: 20040060174
    Abstract: A method for producing a wiring substrate provided with bumps protruding from a surface of the substrate, the method comprising the steps of: covering one side of a metallic base with an electrical insulating film and forming open holes in the insulating film so as to expose at the bottoms thereof the base, etching the base using the insulating film having the open holes formed as a mask to form concavities in the base, electroplating the interior face of each of the concavities using the base as a plating power supply layer to form a barrier metal film on the interior face of each concavities, filling the concavities with a material for the bump by electroplating using the base as a plating power supply layer, forming a barrier layer on the surface of the material for the bump filled in each of the concavities using the base as a plating power supply layer, forming a stack of a predetermined number of wiring patterns on the insulating film, the adjacent wiring patterns in the stack being separated from each
    Type: Application
    Filed: September 15, 2003
    Publication date: April 1, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.
    Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe
  • Patent number: 6711814
    Abstract: A method for increasing the impedance of a via for providing a conductive path through a printed circuit board is disclosed. The method comprises the steps of forming a conductive pad on the printed circuit board, forming a non-threaded opening extending through the conductive pad and through the printed circuit board to form an annular conductive pad surrounding the non-threaded opening, forming a conductive metal barrel lining the inner wall of the non-threaded opening connected to the annular conductive pad, and cutting material from the metal barrel to leave at least one conductive strip extending axially along the inner wall of the opening without cutting material from the annular conductive pad so that the at least one conductive strip is connected to an undivided annular conductive pad.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: March 30, 2004
    Assignee: Robinson Nugent, Inc.
    Inventors: Alexander W. Barr, Samuel C. Ramey, Larry Edward Moser
  • Publication number: 20040055128
    Abstract: The present invention relates a manufacturing method of ceramic device either comprising the steps of forming by layer accumulation of a lower electrode, a piezoelectric/electrostrictive layer, and an upper electrode on a substrate using a mixture of photosensitive resin and metal or piezoelectric/electrostrictive ceramic; and patterning by light exposure at a single time, or repeating the step of patterning by light exposure after formation for layer by layer, or a manufacturing method of ceramic device either comprising the steps of forming by layer accumulation of a piezoelectric/electrostrictive layer and an upper electrode on a metal substrate using a mixture of photosensitive resin and metal or piezoelectric/electrostrictive ceramic; and patterning by light exposure at a single time, or repeating the step of patterning by light exposure after formation for layer by layer, thereby ceramic device of high shape ratio can be produced and precision degree is very high so as to produce a ceramic device very p
    Type: Application
    Filed: October 17, 2003
    Publication date: March 25, 2004
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventors: Sang Kyeong Yun, Dong Hoon Kim, Sung June Park
  • Publication number: 20040057222
    Abstract: A center bond flip chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a plurality of conductive traces. A cut out portion is formed in each trace at a position within a gap of a layer of elastomeric material provided over the traces. Each cut out portion is sized and configured to receive a solder ball for electrically connecting the carrier with a semiconductor die.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 25, 2004
    Inventors: Tongbi Jiang, Alan G. Wood
  • Publication number: 20040055126
    Abstract: A liquid emission device includes a chamber having a nozzle orifice. Separately addressable dual electrodes are positioned on opposite sides of a central electrode. The three electrodes are aligned with the nozzle orifice. A rigid electrically insulating coupler connects the two addressable electrodes. To eject a drop, an electrostatic charge is applied to the addressable electrode nearest to the nozzle orifice, which pulls that electrode away from the orifice, drawing liquid into the expanding chamber. The other addressable electrode moves in conjunction, storing potential energy in the system. Subsequently the addressable electrode nearest to the nozzle is de-energized and the other addressable electrode is energized, causing the other electrode to be pulled toward the central electrode in conjunction with the release of the stored elastic potential energy. This action pressurizes the liquid in the chamber behind the nozzle orifice, causing a drop to be ejected from the nozzle orifice.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Applicant: Eastman Kodak Company
    Inventors: Michael J. DeBar, Gilbert A. Hawkins, James M. Chwalek
  • Patent number: 6708405
    Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 23, 2004
    Assignee: Infineon Technologies AG
    Inventors: Barbara Hasler, Rainer Florian Schnabel, Guenther Schindler, Volker Weinrich
  • Patent number: 6708399
    Abstract: A method for fabricating an interconnect for testing semiconductor components forms contacts on a substrate configured to support and electrically engage bumped contacts on the components. Each contact includes a support member suspended on the substrate on cantilevered spring segment leads. The method includes the steps of forming a polymer material on the substrate, forming a metal layer on the polymer material and the substrate, forming the support member and leads in the metal layer, and then removing the polymer material to suspend the support member. In a first embodiment the polymer material fills a recess in the substrate and the support member is suspended on the recess. In a second embodiment the polymer material is formed as a bump, and the support member is suspended on a surface of the substrate.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: March 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram
  • Publication number: 20040050586
    Abstract: A circuit board includes a substrate having a top surface and a bottom surface and including circuit patterns disposed on the top and bottom surfaces thereof, the substrate defining a connection hole therein; an upper terminal electrically connected to a circuit pattern formed on the top surface of the substrate; a lower terminal electrically connected to a circuit pattern formed on the bottom surface of the substrate, the lower terminal being located opposite to the upper terminal; and wherein the upper terminal and the lower terminal are bonded inside the connection hole of the substrate for electrical connection there-between. A method of fabricating the circuit board is also disclosed.
    Type: Application
    Filed: June 10, 2003
    Publication date: March 18, 2004
    Inventor: Hyoung-ho Roh
  • Patent number: 6705006
    Abstract: Electrical nets are prepared by bonding an electrically conductive element in a deleted plated via. The electrically conductive element has a headed portion that contacts the bottom of the laminate and the other end of the electrically conductive element electrically connects to a BGA pad or surface trace line.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Baechtle, Stephen R. Howland
  • Publication number: 20040048420
    Abstract: An air dielectric printed circuit board fabrication method is disclosed based on the principles of suspended substrate transmission lines as used in microwave assemblies.
    Type: Application
    Filed: June 23, 2003
    Publication date: March 11, 2004
    Inventor: Ronald Brooks Miller
  • Patent number: 6701613
    Abstract: In a method of manufacturing a multilayer circuit board, cable patterns in a plurality of cable layers can be precisely formed, and the cable layer are formed with higher density, with higher reliability. The multilayer circuit board comprises: a plurality of cable layers, each of which includes electric conductive sections; a plurality of first insulating layers, each of which encloses the electric conductive sections in each cable layer and fills spaces between the electric conductive sections; and post vias electrically connecting the electric conductive sections in one cable layer to those in another cable layer. Height of the electric conductive sections in each cable layer are equal to that of the first insulating layer enclosing those electric conductive sections.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 9, 2004
    Assignee: Fujitsu Limited
    Inventor: Kenji Iida
  • Publication number: 20040040148
    Abstract: A novel process is provided for the high speed fabrication of flexible printed circuit boards in continuous roll form and at a cost which is substantially less than the cost of existing fabrication processes. A web of substrate material is supplied from a roll and one or both surfaces are sputter coated with a tie-coat of Monel or chrome and a copper seed layer. The tie-coat is typically of a thickness of about 50-300 angstroms, and the copper seed layer has a thickness of about 200-4000 angstroms. Plated through holes are provided for double sided printed circuit boards, the holes being provided by laser or other suitable drilling equipment in an intended pattern on the substrate. A plating mask is provided with a negative image to allow subsequent selective electrodeposition of copper onto the unmasked areas of the substrate surfaces. The web is then passed through a continuous copper plating cell which provides a plate-up of copper on the unmasked areas of the seed layer.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Applicant: PARLEX CORPORATION
    Inventors: Arthur DeMaso, Darryl J. McKenney, Laurea J. Doiron
  • Patent number: 6699395
    Abstract: A method of forming a conductive device includes forming a conductive layer on a substrate; etching the conductive layer to form a plurality of conductive traces; etching the conductive layer to form at least one mask feature; and removing substrate material that is not covered by the at least one mask feature so as to form at least one mechanical alignment feature.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: March 2, 2004
    Assignee: Storage Technology Corporation
    Inventors: John W. Svenkeson, John D. Hamre