Abstract: The present disclosure relates to a backplane, a backlight source, a display device, and a manufacturing method of the backplane. The backplane includes: a substrate; a plurality of barriers disposed on a surface of the substrate; and a first metal layer disposed on the surface of the substrate and including a plurality of metal patterns spaced apart by the plurality of barriers, wherein the barrier and the metal pattern are connected by a concave-convex mating structure.

Abstract: A thermoelectric generation module includes a first substrate and a second substrate, a plurality of first electrodes and second electrodes that are arranged on the first substrate and the second substrate, a thermoelectric conversion element arranged between the first electrode and the second electrode, and a terminal pin connected to the second electrode. The second substrate includes an insulator layer made of an electrical insulating material, a through-hole that penetrates the insulator layer for insertion of the terminal pin, and an annular metal layer arranged at a peripheral portion of the through-hole. A space between the terminal pin and the through-hole is sealed by solder.

Abstract: Loss reduction methods are described. A first transmission loss associated with signal transmission through a trace in a first circuit board design is determined. The trace is routed from an integrated circuit disposed on a circuit board to a circuit element disposed on the circuit board. It is determined that the first transmission loss is greater than a threshold transmission loss. The first circuit board design is altered to obtain a second circuit board design. In the second circuit board design, the trace is routed from the integrated circuit to a connector disposed on the circuit board, and the connector is electrically coupled to the circuit element by a cable. A second transmission loss associated with signal transmission between the integrated circuit and the circuit element in the second circuit board design is less than the threshold transmission loss.

Abstract: A multilayer wiring board that improves the reliability of connection at a via hole connection portion, and a method for producing the multilayer wiring board. In a multilayer wiring board comprising a plurality of metal wiring layers alternately laminated with insulating layers interposed therebetween are electrically connected to each other via a via hole plated layer, wherein a dissimilar metallic layer, made from material different from that of the metal wiring layers, is interposed between each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer, and the dissimilar metallic layer interposed between the each of the metal wiring layers on the bottom surface of the via hole and the via hole plated layer is arranged in a concave shape on the surface of the concave portion formed in the metal wiring layer on the bottom surface of the via hole.

Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.

Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.

Abstract: A method for constructing an external circuit structure is provided. The method is applied to an inner circuit substrate, wherein, the method comprises: laminating a copper foil and a prepreg on the inner circuit substrate; wherein, the prepreg is laminated between the copper foil and the inner circuit substrate; drilling at least one blind via from the copper foil to reach the copper circuit of the inner circuit substrate; removing smear generated in the at least one blind via during the drilling process; corroding off the copper foil; electroless copper plating on the prepreg to form an electroless plating copper layer on the prepreg; wherein, during the electroless copper plating process, a swelling process without desmearing process is implemented.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.

Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.

Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.

Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.

Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

Abstract: A circuit board and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A substrate having a first surface and a second surface opposite to each other is provided. A first circuit layer is formed on the first surface. A stress is applied to the first circuit layer and the substrate using a awl tool, such that the first circuit layer and the substrate are deformed to form a through hole. A portion of the first circuit layer is located on the sidewalls of the through hole and an end of the through hole is protruded from the second surface. A printing process is performed to form a second circuit layer on the second surface. The second circuit layer is connected to the first circuit layer located in the through hole.

Abstract: A printed circuit board includes a base, a circuit pattern, a solder mask, an activated metal layer, a plurality of metal seed layers, and a plurality of metal bumps. The conductive circuit pattern is formed on the base, to include a plurality of conductive pads. The solder mask is formed on a surface of the conductive circuit pattern and portions of the base are exposed from the circuit pattern. The solder mask includes blind vias corresponding to the pads, and laser-activated catalyst. The activated metal layer is obtained by laser irradiation at the wall of the blind via. The activated metal layer is in contact with the solder mask. The metal seed layer is formed on the activated metal layer and the pads. Each metal bump is formed on the metal seed layer, and each metal bump protrudes from the solder mask.

Abstract: A multilayer wiring board includes an insulating resin layer, wirings laid on their respective opposite surfaces of the insulating resin layer, and a via-hole conductor for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes first metal regions including a joined unit made of copper particles for connecting the wirings, second metal regions mainly composed of, for example, tin, a tin-copper alloy, or a tin-copper intermetallic compound, and third metal regions mainly composed of bismuth and in contact with the second metal regions. The copper particles forming the joined unit are in plane contact with one another to form plane contact portions, and the second metal regions at least partially are in contact with the first metal regions.

Abstract: A suspension board with circuit includes a conductive pattern. The conductive pattern includes a first terminal provided on the front face of the suspension board with circuit and electrically connected with a magnetic head; and a second terminal provided on the back face of the suspension board with circuit and electrically connected with an electronic device.

Abstract: A wiring board includes a plurality of wirings laid via an insulating resin layer, and a via-hole conductor provided for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes a region made of copper particles, a first metal region mainly composed of tin, a tin-copper alloy, or a tin-copper intermetallic compound, and a second metal region mainly composed of bismuth, and has Cu/Sn of from 1.59 to 21.43. The copper particles are in contact with one another, thereby electrically connecting the wirings, and at least part of the first metal region covers around and extends over the portions where the copper particles are in plane contact with one another.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: During mounting to an inlay substrate, at least one end portion (including end) of an antenna wire is positioned directly over a terminal of the chip module for subsequent connecting thereto. A sonotrode is disclosed with a cutter above the capillary for nicking the wire. The antenna may comprise two separate stubs, each having an end portion (including end) positioned over a terminal of the chip module. Additional techniques for mounting the antenna wire are disclosed.

Abstract: One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Abstract: A method of manufacturing a circuit board includes the steps of preparing a fiber piece housing paste, fabricating a filtered recovery paste, fabricating a reuse paste, sticking a protective film, forming a hole, and filling the hole with the reuse paste. Furthermore, the method includes the steps of forming a protruded portion constituted of the reuse paste, disposing a metallic foil on both sides of a second prepreg to carry out pressurization, heating the second prepreg to cure the second prepreg and the reuse paste, and processing the metallic foil into a wiring pattern.

Abstract: A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads.

Abstract: A method of making a semiconductor package substrate includes laser-ablating channels in the substrate. After the channels are ablated in the substrate, conductive material is added to fill the channels and cover the surface of the substrate. Then a photomask etching process simultaneously forms a circuit pattern above the surface of the substrate and removes excess metal above the channels, by removing metal above the surface only in patterned regions. The result is a two-level circuit pattern having conductors within and above the substrate.

Abstract: Methods of backdrilling printed circuit boards (PCBs) to remove via stubs and related apparatuses. The method may include removing a via stub through a combination of backdrilling and chemical etching. The backdrilling may remove a masking layer from the via stub. Portions of an underlying layer may remain in the region of the via stub after the backdrilling is completed. The remaining portions of the underlying layer may be removed in a subsequent etching process thereby removing the via stub from the PCB. As the backdrilling step may be used for the limited purpose of removing the outer layer and portions of the underlying layer remaining in the via can be tolerated, the diameter of the backdrilling need not be as large as traditional backdrilling where all layers within the via must be ensured of being completely removed.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: A method of manufacturing a printed circuit board is provided. The method includes preliminarily forming a plurality of test pattern layers for detecting the depth of an inner layer in a multilayer printed circuit board such that at least a part of a lower test pattern layer is not overlaid with any upper test pattern layer when viewed from a drill entrance side, and preliminarily forming a surface conductor layer; applying a voltage between the surface conductor layer and the test pattern layers; performing drilling toward one test pattern layer, and detecting a current produced when the drill comes into contact with the test pattern to measure the depth of the layer (D1); performing drilling toward the other test pattern layer, and measuring the depth of the layer (D2); and performing drilling up to just before the conductor-wiring layer based on a depth calculated from D1 and D2.

Abstract: A production process of a perforated porous resin base, comprising Step 1 of impregnating the porous structure of a porous resin base with a liquid or solution; Step 2 of forming a solid substance from the liquid or solution impregnated; Step 3 of forming a plurality of perforations extending through from the first surface of the porous resin base having the solid substance within the porous structure to the second surface in the porous resin base; and Step 4 of melting or dissolving the solid substance to remove it from the interior of the porous structure, and a production process of a porous resin base with the inner wall surfaces of the perforations made conductive, comprising the step of selectively applying a catalyst only to the inner wall surfaces of the perforations to apply a conductive metal to the inner wall surfaces.

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract: A method for manufacturing a FPCB substrate includes the following steps. First, a FPCB material including an insulation layer and an electrically conductive layer formed on the insulation layer is provided. The electrically conductive layer has a first surface and an opposite second surface. The insulation layer has a third surface and an opposite fourth surface. The third surface comes into contact with the second surface. Secondly, a through hole extends from the first surface to the fourth surface is formed. The through hole includes a metal hole in the electrically conductive layer and an insulation hole in the insulation layer. Thirdly, the insulation hole is enlarged to expose a portion of the electrically conductive layer around the metal hole. Finally, the exposed portion is bent to form a hook which passes through the enlarged insulation hole and protrudes out from the fourth surface of the insulation layer.

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract: A method of manufacturing a printed wiring board with solder bumps includes forming a solder-resist layer having small and large apertures exposing a respective conductive pad of the printed wiring board, loading a solder ball in each of the small and large apertures using a mask with aperture areas corresponding to the apertures of the solder-resist layer, forming a first bump having a first height, from the solder ball in the small aperture, and a second bump having a second height, from the solder ball in the large aperture, the first height being greater than the second height, and pressing a top of the first bump such that the first height becomes substantially the same as the second height. A multilayer printed wiring board includes a solder-resist layer with apertures of differing sizes and solder bumps having substantially equal volumes but a difference in height no greater than 10 ?m.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract: A method for manufacturing a light reflecting metal wall including a step (a) forming a cavity structure on a metal plate on which back surface a substrate is laminated, the cavity structure including on its side wall a light reflecting wall, the step (a) including the steps of (b) forming a first mask on a surface of the metal plate, the first mask having a mask opening portion corresponding to an opening portion of the cavity structure, and (c) forming the light reflecting wall on a side wall of the metal plate by carrying out wet etching with respect to the metal plate with the first mask, in the step (c), in the middle of the wet etching, the first mask being bent by press working along the light reflecting wall formed by the wet etching. As a result, the light reflecting metal wall is stably formed by securing both (i) an area of an LED chip mounting surface and (ii) a thickness of the light reflecting metal wall even if a packaged light-emitting element has a narrow lateral width of its short side.

Abstract: One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Abstract: A three-dimensional PWB is provided that may include two or more layers stacked together forming a top surface, a bottom surface, and one or more side surfaces, and one or more solder pad situated on at least one of the one or more side surfaces. The one or more solder pads may include exposed voids in the one or more side surfaces. In some cases, the top surface and/or the bottom surface may have one or more solder pad. The one or more solder pads on at least one of the one or more side surfaces may be electrically connected to the one or more solder pads on the top surface and/or the bottom surface. In the illustrative PWB, the top surface and/or the bottom surface may be adapted to be mounted with an inertial sensor. The one or more side surfaces may be adapted to be mounted to a printed wiring board.

Abstract: An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Abstract: A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: A method of fabricating a substrate includes forming a first conductive layer on a dielectric layer, forming a resist layer on the first conductive layer, and forming laser-ablated artifacts through the first resist layer, through the first conductive layer, and at least partially into the dielectric layer. A second conductive layer is formed within the laser-ablated artifacts. The laser-ablated artifacts are filled to form an overfilled circuit pattern. The resist layer and the first conductive layer are removed. Further, a portion of the overfilled circuit pattern is removed to form an embedded circuit pattern embedded within the dielectric layer.

Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

Abstract: A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.

Abstract: A printed circuit board having via arrangements for reducing crosstalk is disclosed. The printed circuit board includes a first layer and a second layer. The printed circuit board also includes a first via and a second via, both traveling from the first layer to the second layer. The first via is orthogonal to the second via in a three dimensional space. In addition, the printed circuit board may include a third via traveling from the first layer to the second layer, and the third via is orthogonal to the first and second vias in the three dimensional space.

Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.

Abstract: A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally unsupported within a thickness of the substrate and extending beyond a side thereof. Dual-sided compliant contact structures, methods of forming compliant contact structures, a method of testing a semiconductor device and a testing system are also disclosed.

Abstract: A method of manufacturing a solid-state imaging device. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element. The wirings are made of thin metal plate leads, the base is made up of a resin molded member in which the thin metal plate leads are embedded, and at least a part of a side edge face of the thin metal plate leads is embedded in the base. The rigidity of the base is enhanced by the thin metal plate leads, thus reducing a curl and a warp of the base.

Abstract: Three magnetic substrates are provided, the first substrate forms the rotor and the other two form the outer stator. A series of spaced concentric grooves and spaced spiral grooves are formed in the central region of both faces of the first substrate. A hole is placed at the center of the spiral grooves, and filled with magnetic material. A conductor is then deposited into the spiral grooves, forming a central wheel. A series of spaced serpentine grooves and generally radial grooves are formed on each active face of the other two substrates. A conductor is then deposited into the serpentine grooves, and a magnetic material is deposited into the generally radial grooves. The two outer substrates are then bonded against the first substrate such that the outer end of each magnetic path overlays a filled hole in the first substrate, creating the stator of an axial air gap reluctance motor.

Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.

Abstract: A method for fabricating an electrical connection structure of a circuit board is proposed. The circuit board is provided with a plurality of pads on a surface thereof and with a plurality of conductive structures therein for electrically connecting the pad. A plurality of openings is formed penetrating through an insulating layer provided on the circuit board to expose the pad. Subsequently, a conductive base is attached to one surface of the circuit board for electrically connecting the pad. By such arrangement, a conductive material can be formed on the pad located on the other surface of the circuit board by an electroplating process via the conductive base, the pad on the surface, and the conductive structure within the circuit board.

Abstract: A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.