With Encapsulating Patents (Class 29/855)
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Patent number: 6395374Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.Type: GrantFiled: May 26, 2000Date of Patent: May 28, 2002Assignee: Merrimac Industries, Inc.Inventors: Joseph McAndrew, James J. Logothetis
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Patent number: 6395584Abstract: A flat plate mold with special treatment or a metallic flat plate mold is adopted to flatten the resin painted over on IC chips during package dispensing process, such that it is able to maintain a consistent flatness of the surface of IC products after dispensing for laser or ink marking. And heat sinks can be attached to the flat plate mold to increase the heat-dissipating rate of IC products after dispensing.Type: GrantFiled: December 26, 2000Date of Patent: May 28, 2002Assignee: FICTA Technology Inc.Inventors: Chi-Hsing Hsu, Chin-Hsing Chung, Wen-Fu Hsu
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Patent number: 6371808Abstract: In a wire module (1), a terminal (4, 5) is pressed to be clamped to each of opposite end portions of a wire (6) to thereby provide a terminal-assembled wire member (2), and molded connector members (10, 11) and a wire circuit member (12) are formed in such a manner that a plurality of terminal-assembled wire members are arranged in an insulative covering layer (3). In the case where the terminals (4) are of the female type, the molded connector member comprises a connector housing, in which the terminal-assembled wire members (2) are inserted, and a terminal holder attached to a terminal-inserting side of the connector housing. The connector housing is of the waterproof type, and includes a waterproof wall which is formed in a bulged manner on an outer peripheral surface of a housing body, receiving the terminals therein, and extends in a direction away from the terminal-inserting side.Type: GrantFiled: April 5, 2001Date of Patent: April 16, 2002Assignee: Yazaki CorporationInventor: Masaharu Sakaguchi
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Publication number: 20010050183Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.Type: ApplicationFiled: July 19, 2001Publication date: December 13, 2001Inventors: Kenneth J. Lubert, Curtis L. Miller, Thomas R. Miller, Robert D. Sebesta, James W. Wilson, Michael Wozniak
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Patent number: 6317965Abstract: A method of manufacturing a noise-cut filter having distributed inductances and distributed capacitances is produced wherein conductive spiral coil patterns are formed on the opposite surfaces of a dielectric sheet, such that the spiral coil patterns are aligned with each other in a direction perpendicular to the plane of the dielectric sheet, and a main circuit pattern is constructed by bonding a main circuit conductor to the spiral coil pattern formed on one of the opposite surfaces of the dielectric sheet. The main circuit conductor is formed by stamping with a punch press so that the conductor has a cross sectional area large enough to allow the passage of current of a main circuit, and has substantially the same shape as the spiral coil pattern.Type: GrantFiled: January 24, 2000Date of Patent: November 20, 2001Assignee: Fuji Electric Co., Ltd.Inventors: Kenji Okamoto, Shinji Uchida, Takao Maeda, Takashi Aihara, Yoshihiro Matsumoto, Naoto Fukasawa
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Publication number: 20010037568Abstract: This invention is related to a method for encapsulating bond regions in electronic components comprising, for example, metallic bond regions, the method comprising the steps of exposing an electronic component having at least one bond region through a primary gas atmosphere comprising unstable or excited gaseous species, the gaseous species being substantially devoid of any electrical charges, the primary gas atmosphere having a pressure ranging from about 0.5×105 Pa to about 3.0×105 Pa, thereby forming a treated, non-encapulated electronic component, then encapsulating the electronic component.Type: ApplicationFiled: March 23, 2001Publication date: November 8, 2001Inventors: Jason R. Uner, Thierry Sindzingre, Claude Carsac
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Patent number: 6294411Abstract: A semiconductor component includes, before molding, a lead frame, a semiconductor chip mounted on the lead frame, and bonding wires for connecting pads of the semiconductor chip to inner leads. This component is inserted between a lower mold and an upper mold having a mold cavity moving unit, and these molds are clamped. Thereafter, an inner space formed by these clamped molds is filled with resin to form a package. Particularly, before resin filling, the mold cavity moving unit is moved downward and presses upper portions of the bonding wires to regulate the wire height. In this state, the inner space of these molds is filled with the resin. Before the filling resin is cured, the mold cavity moving unit is returned to the upper surface position of the package to form a nonfilling space in these molds. Thereafter, the nonfilling space is filled with the resin.Type: GrantFiled: February 10, 1999Date of Patent: September 25, 2001Assignee: Nippon Steel Semiconductor CorporationInventor: Akihito Nishibayashi
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Publication number: 20010012201Abstract: In a biometric sensor and a method for its production, a sensor chip is provided with connecting contacts in the form of electrically conductive bumps. The sensor chip is inserted into a chip housing, the bumps making contact with corresponding connecting leads belonging to the chip housing. At the same time as this contact is made, the sensor chip is bonded adhesively into the chip housing by an adhesive layer, which surrounds the sensor field in a sealing manner.Type: ApplicationFiled: January 16, 2001Publication date: August 9, 2001Inventors: Manfred Fries, Thomas Munch, Reinhard Fischbach
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Patent number: 6248424Abstract: A novel method and apparatus for indicating a degree of manufacture of an insert molded component useable in an end use assembly by forming a removable appendage protruding from the insert molded component, or article, manufactured to an intermediate degree, the insert molded component having a lead frame at least partially embedded in a molded housing member, and the removable appendage coupled to at least one or both of the lead frame and the molded housing member, the lead frame having at least two electrical conductors coupled separably by a tie member, the removable appendage removable upon or after electrical isolation of the electrical conductors in a subsequent processing step, whereby the presence of the removable appendage is indicative that the electrical conductors are not electrically isolated, or that the insert molded component has not been tested or inspected subsequent to electrical isolation of the electrical conductors, and whereby the removable appendage is configured to prevent use of theType: GrantFiled: March 17, 1997Date of Patent: June 19, 2001Assignee: Illinois Tool Works Inc.Inventors: Ernest H. Lindsay, Jr., Jon M. Patterson
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Patent number: 6247229Abstract: Methods for forming packages for housing an integrated circuit device are disclosed. In one embodiment, step 1 provides a plastic sheet having an adhesive first surface. Step 2 provides a patterned metal sheet on the first surface of the plastic sheet. The patterned metal sheet includes an array of package sites. Each package site is formed to include a die pad and a plurality of leads around the die pad. Step 3 places an integrated circuit device on each of the die pads. Step 4 connects a conductor between the integrated circuit device and the leads of the respective package site. Step 5 applies an encapsulating material onto the array. Step 6 hardens the encapsulating material. Step 7 removes the first plastic sheet. Step 8 applies solder balls to the exposed surfaces of the leads. Finally, step 9 separates individual packages from the encapsulated array.Type: GrantFiled: August 25, 1999Date of Patent: June 19, 2001Assignee: Ankor Technology, Inc.Inventor: Thomas P. Glenn
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Patent number: 6243945Abstract: The method of manufacturing electronic parts comprises the steps of: preparing a mother board; mounting element parts on the mother board; providing a thermosetting resin on a surface of the mother board surface on which the element parts are mounted; semi-curing the thermosetting resin so as to be in a range of a stage B condition of the thermosetting resin; splitting the mother board with the thermosetting resin into individual electronic parts each having a divided mother board, at least one element part and the thermosetting resin thereon; and heating the individual electronic parts so that the thermosetting resin in the stage B condition melts first and is then cured permanently.Type: GrantFiled: June 18, 1999Date of Patent: June 12, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Isamu Fujimoto, Tohru Yaso, Tetsuo Tatsumi
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Patent number: 6240637Abstract: The connecting plates 10, 10′ for a battery holder are characterized in that a molded resin plate 11 for integrally molding bus bars 16, 16′ for connecting a plurality of batteries A at intervals corresponding to an arrangement of the plurality of batteries incorporates voltage detection terminals 17 for detecting voltages of the desired batteries in such a condition as to be connected to the bus bars.Type: GrantFiled: September 29, 2000Date of Patent: June 5, 2001Assignee: Yazaki CorporationInventors: Tomohiro Ikeda, Yasuyoshi Fukao
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Patent number: 6229441Abstract: The present invention provides electronic devices and methods of forming electronic devices. One embodiment of the present invention provides an electronic device which includes a substrate having a support surface; a first conductor over the support surface of the substrate, the first conductor including a predetermined portion which defines a first area and a second area of the support surface; at least one electrical component coupled with the first conductor; and a second conductor comprising a conductive adhesive, the second conductor being positioned over the support surface of the substrate and across the predetermined portion of the first conductor, the conductive adhesive being configured to electrically couple the first area with the second area.Type: GrantFiled: February 25, 2000Date of Patent: May 8, 2001Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
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Patent number: 6218628Abstract: A method for the manufacture of printed circuit boards, foil circuit boards and semifinished products for printed and foil circuit boards formed from preliminary products with electrically conductive coatings (7, 8) structurable to conductor patterns and structurable substrates (4), for the formation of connectors (V), contours (K) and conductor patterns (L), the connectors (V), contours (K) and conductor patterns (L) being structured simultaneously or in the same method steps from the preliminary products, and the connectors (V) and contours (K) are part of the structured preliminary product substrate, the connectors (V) being brought for electrical or mechanical connection into a position in which they are connectable and the finished conductor patterns (L) can be separated at contours (K).Type: GrantFiled: January 18, 1996Date of Patent: April 17, 2001Assignee: Dyconex Patente AGInventors: Walter Schmidt, Marco Martinelli
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Patent number: 6191955Abstract: An electronic module comprises (a) an electrical assembly of electrical components and a cap. The cap surrounds a portion of the electrical assembly of electrical components to form a pocket between a portion of the electrical assembly of electrical components and the cap. The cap has at least one sidewall, each of the at least one sidewalls having an end, one of at least one sidewalls proximately positioned to at least one electrical lead and having at least one notch positioned in the end, the pocket filled with an encapsulant. A process comprises providing a cap and filling the cap with encapsulant, placing an electrical assembly of electrical components in the cap filled with the preselected amount of encapsulant, and allowing the electrical assembly to seat to a proper depth.Type: GrantFiled: January 21, 1998Date of Patent: February 20, 2001Assignee: Dallas Semiconductor CorporationInventors: Joe Guillot, Michael Quan Dinh, Bill Roberts, Linda M. McLemore
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Patent number: 6161281Abstract: Battery mounting apparatuses, electronic devices, and methods of forming electrical connections are described. In one implementation, a flexible circuit substrate has an area within which an electrical component, e.g. a thin-profile battery terminal housing member, is to be adhered. A conductive contact node pattern is disposed within the area and sized to be conductively adhered with the component. In one aspect, the conductive contact node pattern comprises an outer conductive node on the substrate at least a portion of which is positioned within the outermost 25% of the area. An electrical component is conductively bonded with the contact node pattern and encapsulating material is provided over and underneath the component. In a preferred aspect, the substrate and electrical component are vacuum processed sufficiently to redistribute the encapsulating material under the component.Type: GrantFiled: February 24, 1999Date of Patent: December 19, 2000Assignee: Micron Technology, Inc.Inventors: Ross S. Dando, Rickie C. Lake, Krishna Kumar
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Patent number: 6134118Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.Type: GrantFiled: April 3, 1997Date of Patent: October 17, 2000Assignee: Cubic Memory Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 6105245Abstract: In a method of manufacturing a resin-encapsulated semiconductor package, a protective film is formed on the surface of a semiconductor chip on which chip electrodes are formed, and openings are formed in the protective film to expose at least part of each chip electrode. Subsequently, conductive balls serving as external connecting terminals are fitted in these openings and connected to the chip electrodes, and all surfaces of the semiconductor chip and the conductive balls are encapsulated with a resin. Finally, the surface of the resin formed on the conductive balls is polished to partially expose the conductive balls. Since a mold need not have pins run against the chip electrode for forming external connecting terminals, damage to the chip electrodes and an increase in cost of the mold can be prevented, and the package can be manufactured inexpensively without deteriorating the reliability.Type: GrantFiled: February 17, 1998Date of Patent: August 22, 2000Assignee: Nippon Steel Semiconductor CorporationInventor: Yuichiro Furukawa
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Patent number: 6099677Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.Type: GrantFiled: November 25, 1998Date of Patent: August 8, 2000Assignee: Merrimac Industries, Inc.Inventors: James J. Logothetis, Joseph McAndrew
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Patent number: 6060343Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.Type: GrantFiled: February 25, 1999Date of Patent: May 9, 2000Assignee: Micron Technology, Inc.Inventors: J. Mike Brooks, Jerrold L. King, Kevin Schofield
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Patent number: 6055724Abstract: A method and device for sealing an IC chip are provided, by which a sealing material is surely discharged onto the upper surface of a circuit board, and the occurrence of imperfect sealing can be eliminated. A first gap (h1) is provided between an application nozzle (15) and a circuit board (13) on which an IC chip (12) is mounted before discharging the sealing material (17), after which a second gap (h2) which is greater than the first gap (h1) is provided between the application nozzle (15) and the circuit board (13) while discharging the sealing material (17), thereby accomplishing the sealing of the IC chip (12), and ensuring that the sealing operation is performed after the sealing material (17) has completely come to contact with the upper surface of the circuit board (13).Type: GrantFiled: October 2, 1998Date of Patent: May 2, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenichi Nishino, Shinji Kanayama, Hiroyuki Otani, Kohei Enchi, Hiroyuki Yoshida
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Patent number: 6043745Abstract: The present invention provides electronic devices and methods of forming electronic devices. One embodiment of the present invention provides an electronic device which includes a substrate having a support surface; a first conductor over the support surface of the substrate, the first conductor including a predetermined portion which defines a first area and a second area of the support surface; at least one electrical component coupled with the first conductor; and a second conductor comprising a conductive adhesive, the second conductor being positioned over the support surface of the substrate and across the predetermined portion of the first conductor, the conductive adhesive being configured to electrically couple the first area with the second area.Type: GrantFiled: November 13, 1997Date of Patent: March 28, 2000Assignee: Micron Technology, Inc.Inventor: Rickie C. Lake
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Patent number: 5983493Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.Type: GrantFiled: April 15, 1997Date of Patent: November 16, 1999Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
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Patent number: 5979046Abstract: A method is provided for fabricating a composite structure having an externally accessible electrical device embedded therein. At least one supporting ply is initially provided that has first and second depressions. An electrical device having at least one electrical lead is disposed in the first depression and a connector tow having at least one tube with opposed first and second ends is disposed in the second depression. The first end of the tube of the connector tow is electrically connected to the electrical lead. Thereafter, at least one additional ply is stacked on the supporting ply such that the electrical device and the connector tow are embedded. The stacked plies can then be consolidated to form an integral laminate structure. Following the consolidation, the second end of the tube of the connector tow can be accessed through the edge surface of the laminate structure to thereby define an externally accessible electrical port for receiving a corresponding connector.Type: GrantFiled: July 30, 1998Date of Patent: November 9, 1999Assignee: McDonnell Douglas CorporationInventors: Robert A. Glowasky, Jack H. Jacobs, Bruce E. McIlroy, Matthew M. Thomas
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Patent number: 5978230Abstract: Battery mounting apparatuses, electronic devices, and methods of forming electrical connections are described. In one implementation, a flexible circuit substrate has an area within which an electrical component, e.g. a thin-profile battery terminal housing member, is to be adhered. A conductive contact node pattern is disposed within the area and sized to be conductively adhered with the component. In one aspect, the conductive contact node pattern comprises an outer conductive node on the substrate at least a portion of which is positioned within the outermost 25% of the area. An electrical component is conductively bonded with the contact node pattern and encapsulating material is provided over and underneath the component. In a preferred aspect, the substrate and electrical component are vacuum processed sufficiently to redistribute the encapsulating material under the component.Type: GrantFiled: February 19, 1998Date of Patent: November 2, 1999Assignee: Micron Communications, Inc.Inventors: Ross S. Dando, Rickie C. Lake, Krishna Kumar
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Patent number: 5896653Abstract: A low voltage, low current power supply and chemical etching tool includes a container and a D.C. voltage source sealed within the container. The D.C. voltage source may be one or more batteries that together generate less than 18 volts and 1.7 amps. Electrical leads are connected to the D.C voltage source, and lead from the container through openings in the container cap. The electrical leads have no splices external to the container. The openings through which the electrical leads pass are sealed. One of the electrical leads is connected to an electro-chemical etching head. The other electrical lead is connected to a connecting clip to be attached to the part to be marked by the etching process.Type: GrantFiled: July 15, 1997Date of Patent: April 27, 1999Assignee: Northrop Grumman CorporationInventors: Carl R. Rhoads, Michael H. Granneman, Kelly G. Ralston
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Patent number: 5885427Abstract: A solid high silicon cast iron elongated anode has a midpoint electrical connection keeping the connection as far as possible from the ends to combat the deleterious pencil effect. The anode is made by casting using a hollow or shell core to form a small axial hole extending from one end. The sand or foundry material of the core is removed and the wall of the hole at the blind end of the hole is at least partially finished to receive a diagonally split slug to which a lead wire is connected. Alternatively the hole is formed by a steel pipe which is left in place as a hole liner. The pipe may be supported by one or more chaplets. The slug is fastened in the blind end of the hole by a driving tool rotating a threaded headed bolt with both axial and rotational force to hold the connection in the blind end of the hole as it is secured in place. The hole is filled with a potting compound sealing the connection in the center of the solid cast iron anode.Type: GrantFiled: June 12, 1997Date of Patent: March 23, 1999Assignee: Corrpro Companies, Inc.Inventors: Ian Pickering, John Chase
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Patent number: 5875545Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.Type: GrantFiled: June 5, 1996Date of Patent: March 2, 1999Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
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Patent number: 5847930Abstract: Improved edge terminals for electronic circuit modules such as single- or multi-chip modules and hybrid circuits, and methods of making the edge terminals are disclosed. The improved edge terminals are formed on the edges of the modules, where they do not take up appreciable surface area from the module, and are formed of heat resisting metal and are of larger size as compared to conventional surface terminal pads which simplifies making connections to the module. In one embodiment, ends of pins are inserted in holes in a substrate along lines which will be the edges of the finished modules. After encapsulating in epoxy, the substrate is cut along the lines to bisect the pins, leaving the halves of the pins as embedded terminals flush with the edge of the module. In another embodiment, terminals are formed by attaching the terminal pieces to pads on the substrate, either in the form of widened zones in a grid structure, or an array of terminal plates.Type: GrantFiled: October 13, 1995Date of Patent: December 8, 1998Assignee: HEI, Inc.Inventor: Scott J. Kazle
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Patent number: 5834084Abstract: A low particulating circuit board for a disc drive flex assembly, and a method for forming the same, are disclosed. The circuit board comprises a conductive metal substrate which has sufficient thickness to provide mechanical support and backplane suppression for the circuit board and to efficiently sink heat generated by preamplifier circuitry housed by the circuit board. The substrate has dielectric layers formed on the top and bottom surfaces thereof, the dielectric layers comprising an epoxy interleaved with nonparticulating fibers, such as tetrafluorethylene (TFE) fibers. Traces and pads are provided on the dielectric layers to provide the necessary electrical connections for the preamplifier circuitry. A plurality of circuit boards are formed from a panel and subsequently cut therefrom. Particulate generation is minimized through the use of the metal substrate, as well as recession of the substrate and the solder masks to reduce the amount of material cut during the cutting operation.Type: GrantFiled: June 5, 1997Date of Patent: November 10, 1998Assignee: Seagate Technology, Inc.Inventor: Mark S. Maggio
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Patent number: 5829128Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.Type: GrantFiled: November 15, 1995Date of Patent: November 3, 1998Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
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Patent number: 5822848Abstract: A method of detachably mounting a heat sink to a lead frame and then an IC die to the heat sink including the steps of first providing a lead frame that has lead fingers and a multiplicity of tie bars extending inwardly from the lead frame, each tie bar has a fixed end integral with the lead frame and a free end equipped with an attachment means, and then providing a heat sink that has a multiplicity of receptacle means adapted to receive the attachment means on the tie bars as well as at least one opening through the thickness of the heat sink, and detachably engaging the attachment means on the tie bars to the receptacle means on the heat sink. The invention is also directed to a lead frame/heat sink assembly that may have a single IC die or a multiple of IC dies mounted on top of the heat sink. A single IC die or a multiple of IC dies that are mounted to the heat sink can be tested in a KGD or KGS test before being assembled to a lead frame.Type: GrantFiled: June 4, 1996Date of Patent: October 20, 1998Assignee: Industrial Technology Research InstituteInventor: Cheng-Lien Chiang
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Patent number: 5804467Abstract: A semiconductor device includes a substrate having top and bottom surfaces, a semiconductor element mounted on the top surface of the substrate, and a resin package made of a resin and encapsulating the semiconductor element. The substrate includes at least one resin gate hole enabling the resin to be introduced from the bottom surface of the substrate via the resin gate hole when encapsulating the semiconductor element by the resin.Type: GrantFiled: May 13, 1997Date of Patent: September 8, 1998Assignees: Fujistsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Shinya Nakaseko, Mitsunada Osawa, Shinichirou Taniguchi, Mayumi Osumi, Hiroyuki Ishiguro, Yoshitugu Katoh, Junichi Kasai
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Patent number: 5787569Abstract: An encapsulated package for a power magnetic device and a method of manufacture therefor. The power magnetic device has a magnetic core subject to magnetostriction when placed under stress. The package includes: (1) compliant material disposed about at least a portion of the magnetic core and (2) an encapsulant substantially surrounding the compliant material and the magnetic core, the compliant material providing a medium for absorbing stress between the encapsulant and the magnetic core, the compliant material reducing the magnetostriction upon the magnetic core caused by the stress from the encapsulant. In one embodiment, the encapsulant includes a vent to an environment surrounding the package. The vent provides pressure relief for the compliant material, allowing the compliant material to substantially eliminate the magnetostrictive effects.Type: GrantFiled: February 21, 1996Date of Patent: August 4, 1998Assignee: Lucent Technologies Inc.Inventors: Ashraf Wagih Lotfi, John David Weld, Karl Erich Wolf, William Lonzo Woods
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Patent number: 5785543Abstract: A high voltage flashlamp connector includes a housing having a well formed therein intersecting a flashlamp supporting opening and having a female connector positioned in the well and aligned with the intersecting flashlamp opening. An electrical conductor is attached through the well to the female connector and the well is filled with an encapsulate forming a seat for the housing. The method includes forming the outer shell of the apparatus of a glass-filled polyphenylene oxide having a well and a flashlamp insert opening having an annular groove formed therein and attaching a high voltage electrical conductor to the female connector which is placed in the outer shell well positioned within the flashlamp opening, and cleaning the shell surfaces, and filling the shell with an encapsulate with a mold pin positioned in the flashlamp opening, and then inserting an O-ring seal and attaching a flashlamp.Type: GrantFiled: December 4, 1995Date of Patent: July 28, 1998Assignee: Litton Systems, Inc.Inventor: Mark C. Dietrich
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Patent number: 5779839Abstract: The present invention teaches a method of manufacturing a enclosed transceiver, such as a radio frequency identification ("RFID") tag. Structurally, in one embodiment, the tag comprises an integrated circuit (IC) chip, and an RF antenna mounted on a thin film substrate powered by a thin film battery. A variety of antenna geometries are compatible with the above tag construction. These include monopole antennas, dipole antennas, dual dipole antennas, a combination of dipole and loop antennas. Further, in another embodiment, the antennas are positioned either within the plane of the thin film battery or superjacent to the thin film battery.Type: GrantFiled: September 26, 1997Date of Patent: July 14, 1998Assignee: Micron Communications, Inc.Inventors: Mark E. Tuttle, John R. Tuttle, Rickie C. Lake
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Patent number: 5776278Abstract: The present invention teaches a method of manufacturing an enclosed transceiver, such as a radio frequency identification ("RFID") tag. Structurally, in one embodiment, the tag comprises an integrated circuit (IC) chip, and an RF antenna mounted on a thin film substrate powered by a thin film battery. A variety of antenna geometries are compatible with the above tag construction. These include monopole antennas, dipole antennas, dual dipole antennas, a combination of dipole and loop antennas. Further, in another embodiment, the antennas are positioned either within the plane of the thin film battery or superjacent to the thin film battery.Type: GrantFiled: January 9, 1997Date of Patent: July 7, 1998Assignee: Micron Communications, Inc.Inventors: Mark E. Tuttle, John R. Tuttle, Rickie C. Lake
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Patent number: 5761804Abstract: A method of assembling a shielded circuit of electronic components and loading them directly into a shell without arranging electronic components on a board. A hybridized electronic circuit, for example a rectifier circuit is made with a bottom shell formed from a transparent plastic, into which is loaded an electronic part. The bottom shell has a connector section as well as a slot which joins the terminals of the electronic components to a top shell also formed from the same plastic, and the various electronic components; the slots in the bottom shell is such that after the electronic component terminals are intersected they can be positioned; then after the electronic components are loaded, the top shell is placed as a cover, and the intersecting terminals as well as the electronic components are ultrasonically sealed at the same time.Type: GrantFiled: October 20, 1995Date of Patent: June 9, 1998Assignee: AUE Co. Research CenterInventor: Yoshio Adachi
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Patent number: 5735040Abstract: A method of producing a thin IC card having a built-in battery includes forming a through-hole including an edge in a circuit board having obverse and reverse main surfaces, a circuit pattern being present on a first of the main surfaces of the circuit board; mounting a functional part on the first of the main surfaces of the circuit board; molding said circuit board and said functional part in a resin with a second main surface of said circuit exposed and forming a battery lodging section in the resin molding defined by the through-hole; and mounting a battery in said battery lodging section and electrically connecting the circuit pattern to the battery.Type: GrantFiled: September 19, 1996Date of Patent: April 7, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsunori Ochi, Seiji Takemura, Syojiro Kodai, Tuguo Kurisu
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Patent number: 5711066Abstract: The present invention teaches a boot system for protecting plugs and connectors or receptacles for use in commercial and industrial environments or applications. A boot is provided for each of the plugs and connectors to be joined, with the boots being formed with triple-sealing cooperative surfaces which contact one another upon the boots being matingly joined. Each boot is further formed with stepped sealing means for receiving a cable to be wired to the device housed by the respective boot. Each boot is yet further formed with outer scalloped longitudinally extending surfaces adapted to receive the fingers of a user.Type: GrantFiled: February 12, 1997Date of Patent: January 27, 1998Assignee: Leviton Manufacturing Co., Inc.Inventor: Cosmo Castaldo
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Patent number: 5692296Abstract: The present invention provides a method for fabricating an integrated circuit package, as well the resulting integrated circuit package, which retains a heatsink in close communication with a mold cavity. This precludes any encapsulant from flowing between the heatsink and the inner surface of a mold cavity. As a consequence, the bottom of the heatsink is not encapsulated and is thus exposed. This is accomplished by including posts, attached to the leadframe assembly, which have the function of exerting a downward force on a leadframe assembly and, in turn, on the heatsink. Tie bars, which are non-functional parts of a leadframe assembly, can be utilized as posts by bending the posts into an upright position.Type: GrantFiled: July 29, 1996Date of Patent: December 2, 1997Assignee: LSI Logic CorporationInventor: Patrick Variot
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Patent number: 5685885Abstract: Semiconductor chip assemblies are fabricated by assembling flexible, sheetlike elements bearing terminals to a wafer, connecting the terminals of each sheetlike element to contacts on the chip, and subsequently severing the chips from the wafer to provide individual assemblies. Each assembly includes a sheetlike element and a chip, arranged so that the terminals on the flexible element.Type: GrantFiled: October 7, 1994Date of Patent: November 11, 1997Assignee: Tessera, Inc.Inventors: Igor Y. Khandros, Thomas H. Distefano
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Patent number: 5664320Abstract: A subminiature circuit protector includes a substrate carrying a metal fuse element hermetically sealed in a glass sleeve cartridge. The fuse element may comprise a film deposited on the substrate, or, alternatively a metal strip or wire. Leads extend from opposing ends of the sleeve for connection in a circuit, and a gas is sealed in the sleeve to provide a suitable environment to improve operating lifetime and interrupting capability. A method for making a circuit protector includes placing a substrate carrying a fuse element in a glass sleeve and placing leads in contact with the fuse element. The assembly is heated in the presence of a gas below atmospheric pressure to a temperature sufficient to soften the glass. The pressure is then increased to cause the ends of the glass sleeve to form a hermetic seal about the leads.Type: GrantFiled: March 23, 1995Date of Patent: September 9, 1997Assignee: Cooper IndustriesInventor: Leon Gurevich
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Patent number: 5647117Abstract: In a switch device, a switch is provided in a tightly closed switch chamber in a casing, and an operating element is advanceably and retreatably inserted into the switch chamber through an opening in the casing. An actuating member, connected to an inner end of the operating element for operating the switch, is provided in the switch chamber and has a fitting hole which including a small diameter portion and a large diameter portion. The inner end of the operating element is passed through a sealing member for sealing between the operating element and the opening, and is fitted into the small diameter portion of the fitting hole to form an annular seal clamping portion between an inner peripheral surface of the large diameter portion of the fitting hole and an outer peripheral surface of the operating element. An outer peripheral surface of the sealing member is secured to the casing, and an inner peripheral surface of the sealing member is clamped by the seal clamping portion.Type: GrantFiled: September 28, 1995Date of Patent: July 15, 1997Assignee: Kabushiki Kaisha Honda LockInventor: Tsutomu Kurita
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Patent number: 5628099Abstract: A method of producing a device including an impedance element provided so as to effect a series resonance, includes a step of connecting connection portions such as terminals or electrodes to be electrically connected in the device, using conductive adhesive resin. This step of connecting connection portions includes a sub-step of applying an alternating current signal which has a frequency lying in close vicinity of a resonant frequency of the device, and which has an enough amplitude to destroy an insulation film parasitically formed in the conductive adhesive resin, to input/output terminals of the device. By executing the sub-step, it is possible to substantially remove a fluctuation in impedance characteristics in dependence on the driving level, and thus to realize a stable operation of the device.Type: GrantFiled: March 17, 1995Date of Patent: May 13, 1997Assignee: Fujitsu LimitedInventors: Noboru Wakatsuki, Masaaki Ono, Kenji Fukayama, Masanori Yachi
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Patent number: 5622898Abstract: A composite containing an integrated circuit chip having conductive site thereon and electrically conductive leads that are interconnected to the conductive site by electrically conductive wire; wherein the wire is coated with a dielectric material. Also, a method for fabricating the composite is provided.Type: GrantFiled: May 19, 1995Date of Patent: April 22, 1997Assignee: International Business Machines CorporationInventor: John H. Zechman
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Patent number: 5620928Abstract: A method of manufacturing an integrated circuit package assembly including (i) an integrated circuit die having a bottom surface and a plurality of input/output terminals, (ii) electrically conductive traces and/or contacts accessible from outside the assembly, and (iii) an encapsulating material encapsulating the integrated circuit die and portions of the electrically conductive traces and/or contacts will be disclosed. The method includes the following steps. First, a temporary support substrate or carrier having a top surface is provided for supporting the integrated circuit package as the package is being assembled. Then, the integrated circuit die is detachably supported on the top surface of the temporary support substrate. Each of the input/output terminals on the integrated circuit die are electrically connected to the electrically conductive traces and/or contacts.Type: GrantFiled: May 11, 1995Date of Patent: April 15, 1997Assignee: National Semiconductor CorporationInventors: Shaw W. Lee, Anthony E. Panczak, Jagdish G. Belani
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Patent number: 5613294Abstract: The present invention provides a method of manufacturing a gas sensor having multiple quadrupoles formed in an array by positioning a plurality of rods in an array of quadrupoles, forming a glass bead on the rods, positioning a source of electrons proximate to one end of the rods to ionize gas molecules, positioning an electrical lens proximate to the source of electrons to induce ionized gas molecules, positioning a collector proximate to the rods and displaced from the lens to receive the ionized gas molecules, providing electrical connections through the glass bead to the source of electrons, to the lens, to the collector and to the rods, and heating the glass beads formed on a plurality of rods positioned in the array of quadrupoles to grip and hold the rods in a cantilevered position to thereby seal the electrical connections.Type: GrantFiled: March 24, 1995Date of Patent: March 25, 1997Assignee: Ferran ScientificInventor: Robert J. Ferran
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Patent number: 5611129Abstract: A packaged piezoelectric oscillator is provided which comprises an insulating package body, a piezoelectric element, and a lid member. The package body has an upwardly open housing groove which has a bottom surface formed with oscillator electrodes at both ends of the housing groove. The piezoelectric element is fixedly received in the housing groove of the insulating package body and held in electrical conduction with the respective oscillator electrodes. The lid member is attached to the package body to close the housing groove. The housing groove has an intermediate wider width portion, and each end of the housing groove is provided with a pair of end positioning walls projecting toward each other for providing a narrower width portion between the pair of end positioning walls.Type: GrantFiled: June 6, 1995Date of Patent: March 18, 1997Assignee: Rohm Co., Ltd.Inventors: Hisaya Yoshimoto, Shigeru Kambara, Ikuo Matsumoto
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Patent number: RE35496Abstract: A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms pan of a resin package.Type: GrantFiled: September 8, 1995Date of Patent: April 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Ken Yamamura, Naoto Ueda, Kazunari Michii, Hitoshi Fujimoto, Kiyoaki Tsumura, Hitoshi Sasaki, Takashi Miyamoto