With Encapsulating Patents (Class 29/855)
  • Patent number: 7578057
    Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: August 25, 2009
    Assignee: FormFactor, Inc.
    Inventors: Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
  • Patent number: 7559140
    Abstract: In a method for mounting a plurality of multishaft servo-amplifier modules, each of which has an identical shape and an identical function to each other and carries semiconductor power elements, on a multishaft servo-amplifier for driving motors, a plurality of multishaft servo-amplifier modules (1) through (6) are mounted on both the surfaces of a multishaft interface substrate (7) as a base plate in parallel with the surfaces of the substrate (7) to constitute a multishaft servo-amplifier function unit for a host controller.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: July 14, 2009
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventor: Shoichiro Shimoike
  • Patent number: 7552532
    Abstract: A method is provided to produce a hermetic encapsulation for an electronic component, which may be an optical and at least partially light-permeable component or a surface wave component, comprises attaching and electrically contacting a component based on a chip to a carrier comprising electrical connection surfaces, such that a front of the chip bearing component structures facing the carrier is arranged to clear it, covering a back of the chip with a film made of synthetic material, such that edges of the film overlap the chip; tightly bonding the film and carrier in an entire edge region around the chip; structuring the film such that the film is removed around the edge region in a continuous strip parallel to the edge region; and applying a hermetically sealing layer over the film, such that this layer hermetically terminates with the carrier in a contact region outside of the edge region.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: June 30, 2009
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krueger, Gregor Feiertag, Ernst Christl
  • Patent number: 7506436
    Abstract: The present invention provides a method for preparing a conforming shield enclosure for shielding a semiconductor device of an electronic component assembly comprising the steps of: (a) metalizing a sheet of a thermoformable polymer with an admixture of a conductive metal and a resin; and (b) thermoforming the metalized thermoformable polymer from step (a) to form a conforming shield enclosure; wherein the conforming shield enclosure has dimensions conforming to the inside of a housing of the electronic component assembly and enclosing and thereby shielding the semiconductor device from electromagnetic frequencies, wherein the conforming shield enclosure is prepared by paint metalization.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: March 24, 2009
    Assignee: Spraylat Corporation
    Inventor: Bruce Bachman
  • Publication number: 20090044496
    Abstract: An apparatus for sealing a glass package by applying a force to a glass assembly while simultaneously irradiating a sealing material disposed between the two glass substrates with a beam of radiation. The applied force is translated in unison with the radiation beam. The radiation cures and/or melts the sealing material, depending upon the sealing material. The applied force beneficially improves contact between the glass substrates and the sealing material during the sealing process, therefore assisting in achieving a hermetic seal between the substrates.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Inventors: John W. Botelho, Margaret Helen Gentile, Kenneth Spencer Morgan, William Robert Powell, Lu Zhang
  • Publication number: 20090038140
    Abstract: A seismic streamer includes a jacket covering an exterior of the streamer. At least one strength member extends along the length of the streamer and is disposed inside the jacket. At least one seismic sensor is disposed in a sensor spacer affixed to the at least one strength member. An encapsulant is disposed between the sensor and the sensor spacer. The encapsulant is a substantially solid material that is soluble upon contact with a void filling material. A void filling material is disposed in the interior of the jacket and fills substantially all void space therein. The void filling material is introduced to the interior of the jacket in liquid form and undergoing state change to substantially solid thereafter.
    Type: Application
    Filed: October 14, 2008
    Publication date: February 12, 2009
    Inventors: Andre Stenzel, Bruce William Harrick, Troy L. McKey, III, James Andrew Langley, III
  • Publication number: 20090035890
    Abstract: A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied encasement material to harden (e.g., heating the encasement material in a curing oven, applying radiation, providing a chemical catalyst, etc.). Application and hardening of the encasement material may take place shortly after circuit board assembly (e.g., by automated equipment at a manufacturing facility in order to treat newly assembled boards) or at some later time in the field (e.g., by a technician servicing a legacy board).
    Type: Application
    Filed: May 20, 2008
    Publication date: February 5, 2009
    Applicant: TEXTRON SYSTEMS CORPORATION
    Inventor: Louis H. Feinstein
  • Patent number: 7479694
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: January 20, 2009
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7475460
    Abstract: A method for producing an airtight terminal having an annular stem, a lead passing through the stem and formed of a conductive material, and a filler for fixing the lead in the stem includes (1) a lead contour formation step of disposing a base and a lead formation portion on a plate- or strip-shaped conductive material and forming a contour of the lead on the lead formation portion with at least one end of the lead connected to the base, (2) a filler shaping and sintering step of filling the lead having a contour with the filler in a predetermined position and shaping and sintering the filler, (3) a stem mounting step of mounting the stem to a perimeter of the sintered filler, (4) a firing step of heating, melting, and cooling the sintered filler in the stem and bringing the lead into close contact with the stem to fix the lead to the stem through the filler, (5) a metal film formation step of forming a metal film on a surface of the lead, and (6) a cutting step of separating the one end of the lead from the
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: January 13, 2009
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Nishino, Hiroaki Uetake, Yuki Hoshi
  • Publication number: 20080313895
    Abstract: A method of manufacturing an electronic component minimizes the occurrence of voids and degradation of characteristics in a resin-sealed portion, while reducing the costs thereof. A sealing step for sealing surface acoustic wave elements by a sealing resin member formed from a resin film is performed by mounting the surface acoustic wave elements on a collective mounting substrate and the resin film in a bag with a gas-barrier property, and causing the resin film to infiltrate between the surface acoustic wave elements mounted on the reduce-pressured-packed collective mounting substrate to be hermetically sealed by the pressure difference between the inside and the outside of the bag.
    Type: Application
    Filed: December 7, 2004
    Publication date: December 25, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato Higuchi, Hideki Shinkai, Osamu Ishikawa
  • Publication number: 20080307642
    Abstract: There are provided the steps of mounting a semiconductor chip on a first substrate, providing an underfill resin between the semiconductor chip and the first substrate, forming a through hole on a second substrate, providing an electrode on the second substrate, bonding the first and second substrates to include the semiconductor chip through the electrode, and filling a sealing resin between the first and second substrates at a filling pressure capable of correcting a warpage generated on the semiconductor chip and the first substrate while discharging air from the through hole.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 18, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Nobuyuki Kurashima, Tadashi Arai, Hajime Iizuka
  • Patent number: 7444726
    Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance, a printed circuit board having the capacitor mounted thereon, and a method of making. Sheets of green-state ceramic dielectric material and glass/metal composite material are laminated together, diced into individual chips, and fired to sinter the glass and the ceramic together. The composite material contains an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the printed circuit board. Vertically-oriented surface mountable capacitors and hybrid capacitors are provided.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: November 4, 2008
    Assignee: Presidio Components, Inc.
    Inventors: Alan Devoe, Lambert Devoe, Hung Trinh
  • Publication number: 20080216887
    Abstract: Methods and systems for interconnecting back contact solar cells. The solar cells preferably have reduced area busbars, or are entirely busbarless, and current is extracted from a variety of points on the interior of the cell surface. The interconnects preferably relieve stresses due to solder reflow and other thermal effects. The interconnects may be stamped and include external or internal structures which are bonded to the solder pads on the solar cell. These structures are designed to minimize thermal stresses between the interconnect and the solar cell. The interconnect may alternatively comprise porous metals such as wire mesh, wire cloth, or expanded metal, or corrugated or fingered strips. The interconnects are preferably electrically isolated from the solar cell by an insulator which is deposited on the cell, placed on the cell as a discrete layer, or laminated directly to desired areas of the interconnect.
    Type: Application
    Filed: December 23, 2007
    Publication date: September 11, 2008
    Applicant: ADVENT SOLAR, INC.
    Inventors: Peter Hacke, David H. Meakin, James M. Gee, Sysavanh Southimath, Brian Murphy
  • Patent number: 7392581
    Abstract: A plate member includes a frame portion (51) provided in a state of coupling both one end portion and other end portion and mounting terminal portions (44) protruding from the one end portion and the other end portion of said frame portion (51) to approach each other, from which a PCB joint portions (46) to be a mounting portion to a PCB are formed by cutting and bending when manufacturing a magnetic element. Further, a winding number adjustment means (41), which is capable of selecting joint portions with ends of a coil and adjusting the winding number of the coil in accordance with the selection, protrudes from the one end portion and the other end portion to approach each other farther as compared to the mounting terminal portions (44).
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: July 1, 2008
    Assignee: Sumida Corporation
    Inventors: Kan Sano, Satoru Yamada
  • Patent number: 7387740
    Abstract: An exemplary method of manufacturing a metal cover (1) with blind holes (3) therein includes: step (60), preparing a metal substrate; step (62), covering the metal substrate with a protective film formed by electrophoretic deposition; step (64), forming holes in the protective film according to an intended pattern of the blind holes in the metal cover, thus exposing the metal surface through the holes; step (66), etching the metal substrate in the exposed areas to form the blind holes; and step (68), removing a remainder of the protective film from the metal substrate, thereby obtaining the finished metal cover. The method involving etching is relatively low-cost. Additionally, because electrophoretic deposition is used to cover the metal substrate with the protective film, the protective film can be formed on all surfaces of the metal substrate. Thus the method is especially advantageous for manufacturing a metal cover having a three-dimensional shape.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 17, 2008
    Assignee: Sutech Trading Limited
    Inventor: Wen-Te Lai
  • Patent number: 7334324
    Abstract: A method of manufacturing a, in order to accommodate the words range and to clarify the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 26, 2008
    Assignees: Sony Corporation, Mitsubishi Plastics, Inc.
    Inventors: Minoru Ogawa, Masahiro Izumi, Shigeyasu Itoh, Shingetsu Yamada, Shuuji Suzuki, Hiroo Kurosaki
  • Patent number: 7332376
    Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: February 19, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Chad A. Cobbley
  • Patent number: 7310873
    Abstract: An implantable lead body for a medical device with improved conductor lumens separates and insulates conductors while permitting access to the conductors through the implantable lead outer surface. The implantable lead comprises a lead body, a stylet lumen, at least one conductor lumen, and at least one axial slit in the lead body. The lead body has a proximal end, a distal end, an internal portion, and an external portion. The stylet lumen is formed in the internal portion. The conductor lumen is formed in the internal portion and positioned near an outer surface of the internal portion such that there is only a web between the conductor lumen and the outer surface of the internal portion. The axial slit is formed in the lead body distal end between the conductor lumen and the outer surface of the internal portion.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: December 25, 2007
    Assignee: Medtronic, Inc.
    Inventors: Xavier E. Pardo, Shahn S. Sage, Scott B. Kokones, Jeffrey S. Gagnon
  • Patent number: 7310872
    Abstract: A computing device having an improved enclosure arrangement is disclosed. One aspect of the enclosure pertains to enclosure parts that are structurally bonded together to form a singular composite structure. In one embodiment, structural glue is used to bond at least two unique parts together. Another aspect of the enclosure pertains to enclosure parts that are electrically bonded together to form a singular integrated conductive member. In one embodiment, conductive paste is used to bond at least two unique parts together. The improved enclosure is particularly useful in portable computing devices such as laptop computers.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: December 25, 2007
    Assignee: Apple Inc.
    Inventors: Michael Kriege, Dan Hong, John DiFonzo, Stephen Zadesky, David Lynch, David Lundgren, Nick Merz
  • Patent number: 7299548
    Abstract: Sealing material is injected into a cap receiving an electric cable joint without remaining air bubbles. The cap has an opening at both ends and receives the joint, the electric cable being in the upper side and the joint being in the lower side. The sealing material is injected into the cap from the lower opening. The joint is inserted into the cap from the upper opening. Or, the joint is received in the cap, the sealing material is injected into the cap from the upper opening, and the cap position is reversed. Or, the sealing material is injected into the cap, from the upper opening, the joint is inserted into the cap, and the cap is reversed. A cap holder receives the cap such that the upper and/or lower opening of the cap is covered.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: November 27, 2007
    Assignee: Yazaki Corporation
    Inventors: Chieko Torii, Takayuki Yamamoto, Masato Ozawa
  • Patent number: 7296350
    Abstract: A method for fabricating a drop generator with a uniquely formed nonconductive mandrel, which when encapsulated with electroplated metal, shapes and defines the internal ink channel entails identifying a non-conductive dimensionally stable structure with a shape adapted to define a fluid cavity for the drop generator for an ink jet printer. The ends of the structure are covered with caps. A conductive base is mounted to each structure. Metal from the conductive base is electroformed onto the structure to a thickness at least equivalent to a desired outer dimension. The caps are removed and the structure is removed, thereby leaving a drop generator with a channel adapted to receive fluid and a slot adapted to communicate fluid from the channel to the orifice plate.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: November 20, 2007
    Assignee: Eastman Kodak Company
    Inventors: Richard W. Sexton, James E. Harrison, Jr.
  • Patent number: 7296345
    Abstract: A portable memory device includes a molded housing and a printed circuit board assembly (PCBA) encased with the molded housing such that a plug connector extends from one end. A lower housing portion is produced by injection molding using a first apparatus, and then the lower housing portion is transferred to a second molding apparatus. The PCBA is mounted onto the lower housing such that the plug connector is received in a protected region. The second molding apparatus is then closed, and an upper housing portion is injected molded over the PBCA and exposed peripheral edges of the lower housing portion such that the upper housing portion becomes fused to the lower housing portion. Multiple lower housing portions connected together by plastic tethers to form a plastic strip, which facilitates efficient transfer to the second molding apparatus as a unit. The tethers are subsequently removed (e.g., singulated) to form individual memory devices.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: November 20, 2007
    Assignee: Super Talent Electronics, Inc.
    Inventors: Kuang-Yu Wang, Jim Ni, Ren-Kang Chiou, Edward W. Lee
  • Patent number: 7281305
    Abstract: A method for attaching a capacitor to the feedthrough assembly of a medical device having a terminal pin comprises threading a first washer over the terminal pin, and placing a body of epoxy in contact with the first washer. The capacitor is positioned over the terminal pin such that the first washer and the body of epoxy are between the lower surface of the capacitor and a support surface. The body of epoxy is cured to couple the capacitor to the insulating structure. During curing, the body of epoxy is substantially confined between the upper surface and the lower surface by the ferrule, the insulating structure, the capacitor, and the first washer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 16, 2007
    Assignee: Medtronic, Inc.
    Inventors: Rajesh V. Iyer, Susan A. Tettemer, John P Tardiff, Shawn D. Knowles
  • Publication number: 20070231958
    Abstract: A method of manufacturing a composite electronic part includes: a part arrangement step of arranging a film circuit element and a chip-like electronic part on one substrate surface of a ceramic substrate; a protective layer disposition step of disposing a protective layer that protects the film circuit element and the chip-like electronic part on the one substrate surface of the ceramic substrate, and flattening an upper surface of the protective layer; and a conductive material arrangement step of, after both of the steps, arranging a plurality of conductive projections that become terminals of the film circuit element and the chip-like electronic part on the other surface of the ceramic substrate in a state where the upper surface of the protective layer abuts on a horizontal plane.
    Type: Application
    Filed: March 15, 2007
    Publication date: October 4, 2007
    Inventor: Isao Akahane
  • Publication number: 20070209449
    Abstract: A method for manufacturing a component of a fluid pressure measurement unit includes the step of providing a measurement element with a measurement chip arranged on a first side of the chip carrier and a plurality of socket-shaped terminal contacts for contacting contact terminals of the measurement chip, wherein the socket-shaped terminal contacts protrude from a second side of the chip carrier opposite from the first side of the chip carrier.
    Type: Application
    Filed: July 20, 2006
    Publication date: September 13, 2007
    Inventors: Joerg Weber, Bernd Beck
  • Patent number: 7263768
    Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7246421
    Abstract: A surface acoustic wave device which occupies a small mounting area and has a low profile, yet having an improved reliability, and can be made available at low cost. The surface acoustic wave device comprises a piezoelectric substrate, a function region formed of comb-like electrodes for exciting surface acoustic wave provided on a main surface of the piezoelectric substrate, a space formation member covering the function region, a plurality of bump electrodes provided on a main surface of the piezoelectric substrate and a terminal electrode provided opposed to the main surface of piezoelectric substrate. The bump electrode and the terminal electrode are having a direct electrical connection, and a space between piezoelectric substrate and terminal electrode is filled with resin.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiko Namba, Keiji Onishi, Yasuhiro Sugaya, Katsunori Moritoki
  • Patent number: 7231712
    Abstract: A module includes a ceramic substrate, first and second electrodes provided on the ceramic substrate, a component having third and fourth electrodes connected to the first and second electrodes, respectively, and a resin filled in a space between the component and the ceramic substrate. The ceramic substrate has a surface thereof having a recess formed therein. The first and second electrodes are provided on the surface of the ceramic substrate so that the recess is located between the first and second electrodes. The component is located over the recess and spaced from the ceramic substrate with a space including the recess. The space including the recess is filled with the resin. The module allows each component to be surface mounted at higher bonding strength, thus preventing short-circuit between the electrodes on the substrate and improving the operation reliability.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 19, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuichi Saito, Hiroshi Kagata, Masaaki Katsumata
  • Patent number: 7225534
    Abstract: The present disclosure relates to a telecommunications cable having a jacket including a feature for allowing post-extrusion insertion of an optical fiber or other signal-transmitting member. The present disclosure also relates to a method for making a telecommunications cable having a jacket including a feature for allowing post-extrusion insertion of an optical fiber or other signal-transmitting member.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: June 5, 2007
    Assignee: ADC Telecommunications, Inc.
    Inventor: Wayne M. Kachmar
  • Patent number: 7193161
    Abstract: A single-lid flash memory card and methods of manufacturing same are disclosed. The single-sided lid flash memory card may be formed from a semiconductor package having two or more tapered, stepped or otherwise shaped edges capable of securing a single-sided lid thereon. The taper, step or other shape may be fabricated by various methods, including during the molding step or during the singulation step. A semiconductor package having shaped edges may be enclosed within an external lid to form a finished flash memory card. The lid may be applied to a single side of the semiconductor package by various processes, including over-molding, or by pre-forming the lid with interior edges to match the exterior edges of the semiconductor package, and then sliding the lid over the package to form a tight fit therebetween. The shaped edge of the semiconductor package effectively holds the lid securely on the memory card without any adhesives and prevents the lid from dislodging from the semiconductor package.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: March 20, 2007
    Assignee: SanDisk Corporation
    Inventors: Hem Takiar, Warren Middlekauff, Robert C. Miller
  • Patent number: 7178235
    Abstract: A method for providing an encapsulated optoelectronic chip is provided. The optoelectronic chip is secured on a substrate. A translucent coating substance is then applied on said optoelectronic chip and the translucent coating substance is then polished away to enable an optical coupling.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: February 20, 2007
    Assignee: Reflex Photonics Inc.
    Inventors: David Robert Cameron Rolston, Tomasz Maj
  • Patent number: 7174627
    Abstract: A known good die is economically fabricated. A tested integrated circuit is provided which includes a die having a bonding location on an upper surface and a lead. An upper portion of the integrated circuit package is removed or ground away to expose the bonding location. The lead is removed leaving the die and exposed bonding location to provide a known good die. The backside portion of the integrated circuit package is removed or ground away to expose the backside of the die. A contact pad is disposed on the bonding location. The bonding wire and exterior lead are also removed or ground away. The upper portion of the bonding ball is removed to provide a flattened bonding location. Preferably, the tested integrated circuit package provided is a thin small outline integrated circuit package (TSOP), and advantageously may be a packaged flash memory integrated circuit.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: February 13, 2007
    Assignee: Irvine Sensors Corporation
    Inventor: Keith D. Gann
  • Patent number: 7171748
    Abstract: Disclosed is a manufacturing method of a liquid jet recording head which includes a forming step of forming a recess portion between a flexible film wiring board and a recording element board, a providing step of providing in the recess portion an electrical connecting portion for electrically connecting the flexible film wiring board and the recording element board, a membrane curing step of injecting first resin into the recess portion to cure the first resin in a membrane form, and a covering step of covering an upper portion of the electrical connecting portion and the first resin with second resin subsequent to the membrane curing step. The electrical connecting portion is protected against liquid droplets and the like, and its electrical reliability is improved.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 6, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Kigami, Manabu Tanimoto, Noaki Nakajo, Junichiro Iri
  • Patent number: 7168161
    Abstract: In a method of manufacturing a camera module having a CMOS image sensor, a semiconductor chip to serve as a light sensor is mounted on a optical-component-mounting face of a wiring substrate mother board and, after bonding wires are connected to the semiconductor chip, a lens barrel is joined to the wiring substrate mother board so as to cover the semiconductor chip. A position adjustment pin and a through hole are provided on the lens barrel and the wiring substrate mother board respectively outside a junction face between the lens barrel and the wiring substrate mother board to be used for adjusting the position of the lens barrel with respect to the wiring substrate mother board by inserting the position adjustment pin into the through hole.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: January 30, 2007
    Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor Inc.
    Inventors: Kenji Hanada, Akio Ishizu
  • Patent number: 7146720
    Abstract: A method for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate using the combination pin one indicator and alignment fiducial are also described.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: December 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7129590
    Abstract: A stencil and method for depositing a coupon of underfill material onto a substrate that is to receive an integrated circuit die.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventor: Jeffrey R. Watson
  • Patent number: 7122905
    Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ford B. Grigg
  • Patent number: 7117591
    Abstract: A siding block comprising an electrical junction box and a cover for mounting a light fixture to the exterior of a building. The electrical junction box includes a back wall, a front peripheral wall, and a recessed area within the back wall having one or more removable wall sections within the recessed area. One or more of the removable wall sections can be removed and an electrical cable connector inserted therein to provide strain relief attachment of an electrical cable therein. The electrical junction box includes two or more posts integral with and extending from the front peripheral wall and including fastener-accepting portions. The cover includes a central opening and a rear peripheral wall surrounding the central opening.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: October 10, 2006
    Assignee: Arlington Industries, Inc.
    Inventor: Thomas J. Gretz
  • Patent number: 7101737
    Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Chad A. Cobbley
  • Patent number: 7089661
    Abstract: A method is disclosed for packaging a small size memory card, including xD Picture card, Memory Stickâ„¢, Secure Digitalâ„¢ (SD) card, SmartMediaâ„¢ (SM) card, Multimedia card (MMC), CompactFlashâ„¢ (CF) card and PC card, by moulding over to encapsulate a populated printed circuit board (PCB) (10) to form the standard external dimensions and features of the memory card. The method comprises holding the populated PCB (10) in place in a cavity (44) of at least one mould piece; and moulding over both sides of the populated printed circuit board (10) to encapsulate said board. Various embodiments are disclosed, including means for holding the populated PCB (10) in the moulding cavity (44) for the encapsulation process, which includes transfer moulding and injection moulding processes, one or more moulding steps, and moulding over one part of one side of said board before the other side, and/or simultaneously moulding over both sides of said board.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: August 15, 2006
    Inventors: Piau Fong, Chee Kiang Yew, Colin Chun Sing Lum, Matthew Keng Siew Chua
  • Patent number: 7086147
    Abstract: Solder balls such as, low melt C4 solder balls, undergo volume expansion during reflow, such as may occur during attachment of chip modules to a PCB. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodated this volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Patent number: 7082678
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a first end to a second end such that a portion of each lead exhibits a generally arcuate shape. The first end may be coupled with a printed circuit board and the second end may be coupled with a semiconductor die. The generally arcuately shaped portion of the leads may include a portion which exhibits a constant radius. The generally arcuately shaped portion may also be formed from a plurality of conductor segments including, for example, at least one generally arcuately shaped segment. The semiconductor die and at least a portion of the leads may be encapsulated with an insulating material.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: August 1, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ronnie M. Harrison, David J. Corisis
  • Patent number: 7059042
    Abstract: A sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board. Accordingly, there are provided a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection reliability, a method of manufacturing the same, and a power module allowing its size to be reduced and its density to be increased.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
  • Patent number: 7047637
    Abstract: Method of manufacture of a composite wiring structure for use with at least one semiconductor device, the structure having a first conductive member upon which the semiconductor device can be mounted for electrical connection thereto. A dielectric member, made of ceramic or organo-ceramic composite material, is bonded to the first conductive member and contains embedded therein a conductive network and a thermal distribution network. A second conductive member may be incorporated with the composite wiring structure, with a capacitor electrically connected between the conductive network and the second conductive member. Bonding between the dielectric member and the conductive members may be in the form of a direct covalent bond formed at a temperature insufficient to adversely effect the structural integrity of the conductive network and the thermal distribution network.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: May 23, 2006
    Inventors: L. Pierre deRochemont, Peter H. Farmer
  • Patent number: 7047629
    Abstract: A circuit board manufacturing method including the steps of forming a through hole on an insulator layer and then filling the through hole with a conductive paste; dispersing and forming a protective agent on an adhesion surface of a conductor foil so as to include adhesion surface regions where the protective agent does not exist; sticking the conductor foil to the insulator layer; and abutting a plurality of conductive powders constituting the conductive paste and the conductor foil to each other through the adhesion surface regions by means of heating and pressurizing the insulator layer and conductor foil.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 7036223
    Abstract: A cabling method especially for installing thick electric cables (1) for connection to electric devices (8), in which method the cables (1) are brought to a cabling space (3), fitted and supported in place, cut and stripped at necessary locations, and the desired cables are equipped with cable shoes (6) or connectors for installing to the electric device (8), in which case the cabling steps are, before connection to the electric device (8), performed mainly outside the electric device (8) to be connected by using a separately arranged cabling part (3) comprising said cabling space (3). The invention also relates to this cabling part.
    Type: Grant
    Filed: October 14, 2002
    Date of Patent: May 2, 2006
    Assignee: ABB OY
    Inventors: Matti Kauranen, Mikko Himmanen
  • Patent number: 7031170
    Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Frank Daeche, Franz Petter
  • Patent number: 7024765
    Abstract: A method of manufacturing a surface-emitting backlight is provided with the steps of forming a lead frame and resin-made molded case by insert molding, attaching light sources, which are red, blue and green LED dies, to contacts of the lead frame provided in a hollow space of the molded case, forming a light guide section by filling the hollow space with a transparent or semitransparent resin, and thereafter attaching a reflector sheet, and lens sheets (or diffuser sheets) in accordance with the applications of the backlight.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 11, 2006
    Assignee: Ryoden Trading Company, Limited
    Inventor: Yasufumi Sakakibara
  • Patent number: 6986197
    Abstract: A method is provided for processing leadframe items of two or more types to form integrated circuit packages. The leadframe items are delivered along respective input paths and are received into holders, which are moved alternately between a processing region and a respective leadframe item reception position on a respective input path such that each of the holders moves to the processing region at a time when the other of the holders moves to its respective reception position. The leadframe items are delivered from the respective reception position to the processing region, and are then sent for encapsulation.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: January 17, 2006
    Assignee: ASM Technology Singapore PTE Ltd.
    Inventors: Jian Wu, Yan Zhou, Shu Chuen Ho, Teng Hock Kuah
  • Patent number: 6968613
    Abstract: A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 29, 2005
    Assignee: UltraTera Corporation
    Inventors: Chung-Che Tsai, Jin-Chuan Bai