By Molding Of Insulating Material Patents (Class 29/856)
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Patent number: 7258819Abstract: The present invention provides an improved voltage variable material (“VVM”). More specifically, the present invention provides an improved printed circuit board substrate, an improved device having circuit protection an improved data communications cable having circuit protection and a method for mass producing devices employing the VVM substrate of the present invention. The VVM substrate eliminates the need for an intermediate daughter or carrier board by impregnating conductive particles and possibly semiconductive and/or insulative particles associated with known volatage variable materials into the varnish or epoxy resin associated with known printed circuit board substrates.Type: GrantFiled: October 11, 2001Date of Patent: August 21, 2007Assignee: Littelfuse, Inc.Inventor: Edwin James Harris, IV
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Patent number: 7251877Abstract: A sensor assembly for a magnetic flowmeter is provided that is cost-effective to manufacture, while incorporating an effective seal against leakage and enabling precise positioning of electrodes. The sensor assembly includes an electrode assembly and a plastic housing molded about the electrode assembly. The electrode assembly includes an electrode and a plastic base disposed about the lower end of electrode. The housing includes a wall in direct contact with the plastic base such that the tip of the electrode projects from the wall, facilitating a secure seal about the electrode. The sensor assembly further includes a magnetic assembly configured to provide a magnetic field extending beyond the wall of the housing.Type: GrantFiled: May 24, 2006Date of Patent: August 7, 2007Assignee: George Fischer Signet, Inc.Inventors: Anthony Thai, Gert Burkhardt
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Patent number: 7234229Abstract: The present invention provides a process and an apparatus for the preparation of a motor coil by which a longitudinally wound motor coil, so called, can be easily prepared. First, a molded product 10 comprising a column part 11, and a fin part 12 projected in the form of flat plate from an outer peripheral surface 11A, 11B, 11C, 11D of the column part to an outer side in a radial direction of the column part and helically continuing in an axis direction of the column part at predetermined intervals along the outer peripheral surface of column part is prepared. The column part 11 of the first molded product is punched out in an axis direction of the column part with retaining the fin part 12 to remove the column part, and the fin part 12 having helical shape left after the removal is coated with an insulating film.Type: GrantFiled: April 2, 2004Date of Patent: June 26, 2007Assignee: Fuji Jukogyo Kabushiki KaishaInventors: Jiro Maruyama, Motoyuki Fujiwara, Nobuyuki Mabuchi, Koji Etoh
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Patent number: 7234237Abstract: In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.Type: GrantFiled: April 9, 2004Date of Patent: June 26, 2007Assignee: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Klaus-Günter Oppermann
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Patent number: 7230214Abstract: A metal sheathed heater utilizes splice connections that connects ends of a heater cable with ends of a lead wire. Each splice connection has a connector that connects core wires of the lead wires and heater cable together. Heat shrinkable tubing surrounds the connector and ends of the heater cable and lead wires. An adhesive is interposed between the heat shrinkable tubing and heater cable and lead wire ends to bond with the heat shrinkable tubing and complete the splice connection. The metal sheath of the heater can be formed with an enlarged diameter portion to account for the heat shrinkable tubing surrounding the lead wire and heater cable ends.Type: GrantFiled: February 25, 2005Date of Patent: June 12, 2007Assignee: Tutco, Inc.Inventor: Robert Kirby
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Patent number: 7219416Abstract: The present invention provides a composite magnetic body containing metallic magnetic powder and thermosetting resin and having a packing ratio of the metallic magnetic powder of 65 vol % to 90 vol % and an electrical resistivity of at least 104 ?·cm. When a coil is embedded in this composite magnetic body, a miniature magnetic element can be obtained that has a high inductance value and is excellent in DC bias characteristics.Type: GrantFiled: May 11, 2004Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Osamu Inoue, Junichi Kato, Nobuya Matsutani, Hiroshi Fujii, Takeshi Takahashi
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Patent number: 7216420Abstract: A print head manufacturing method in which satisfactory precision can be obtained by simple processes are provided. Projecting objects having a predetermined shape are formed on a substrate, and a setting resin is applied on the substrate and is set. Then, the projecting objects are removed so that ink cells and nozzles are formed. The thickness of the setting resin is determined such that tip portions of the projecting objects project above the setting resin and ink cells can be formed.Type: GrantFiled: March 20, 2003Date of Patent: May 15, 2007Assignee: Sony CorporationInventors: Manabu Tomita, Koichi Igarashi
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Patent number: 7207109Abstract: A method for producing an ink jet head including, on a substrate, a piezoelectric element for discharging an ink from a discharge port, and an ink flow path communicating with the discharge port so as to correspond to the piezoelectric element, the method comprising in this order a step of providing, on the substrate, a mold material corresponding to the ink flow path, a step of providing a wall material of the ink flow path so as to cover the mold material, a step of eliminating a portion of the substrate corresponding to the piezoelectric element thereby forming a space in the substrate, and a step of eliminating the mold material thereby forming the ink flow path.Type: GrantFiled: February 5, 2004Date of Patent: April 24, 2007Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Osamu Kanome, Takehito Nishida
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Patent number: 7204017Abstract: A manufacturing method of a modularized leadframe, using a first mold set to contact and hold the upper surface of rows of multiple block leads, using a second mold set to contact and hold at least one selected surface of the lower surface of leads, the second mold set has a protruding part between each row of leads so that the upper surface of the protruding part be in close contact with the inner surface of the first mold set. The hollow space between the mold sets is then injected with packaging materials such that a leadframe structure having packaged and fixed leads therein and surfaces for wire-bonding and soldering is obtained. A packaging material filling space is formed in the leadframe after removing the first and the second mold sets.Type: GrantFiled: October 7, 2004Date of Patent: April 17, 2007Assignee: Optimum Care International Tech. Inc.Inventors: Jeffrey Lien, Shihlin Chang
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Patent number: 7191515Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).Type: GrantFiled: July 28, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Robert C. Sundahl, Kenneth Wong
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Patent number: 7193161Abstract: A single-lid flash memory card and methods of manufacturing same are disclosed. The single-sided lid flash memory card may be formed from a semiconductor package having two or more tapered, stepped or otherwise shaped edges capable of securing a single-sided lid thereon. The taper, step or other shape may be fabricated by various methods, including during the molding step or during the singulation step. A semiconductor package having shaped edges may be enclosed within an external lid to form a finished flash memory card. The lid may be applied to a single side of the semiconductor package by various processes, including over-molding, or by pre-forming the lid with interior edges to match the exterior edges of the semiconductor package, and then sliding the lid over the package to form a tight fit therebetween. The shaped edge of the semiconductor package effectively holds the lid securely on the memory card without any adhesives and prevents the lid from dislodging from the semiconductor package.Type: GrantFiled: February 15, 2006Date of Patent: March 20, 2007Assignee: SanDisk CorporationInventors: Hem Takiar, Warren Middlekauff, Robert C. Miller
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Patent number: 7178235Abstract: A method for providing an encapsulated optoelectronic chip is provided. The optoelectronic chip is secured on a substrate. A translucent coating substance is then applied on said optoelectronic chip and the translucent coating substance is then polished away to enable an optical coupling.Type: GrantFiled: December 3, 2003Date of Patent: February 20, 2007Assignee: Reflex Photonics Inc.Inventors: David Robert Cameron Rolston, Tomasz Maj
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Patent number: 7112252Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.Type: GrantFiled: August 26, 2003Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
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Patent number: 7094619Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.Type: GrantFiled: September 23, 2004Date of Patent: August 22, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
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Patent number: 7059028Abstract: Methods of making certain piezoelectric films are disclosed. For example, a certain method of making piezoelectric films consistent with certain embodiments of the invention can include the steps of obtaining a piezoelectric material, reducing said piezoelectric material to particles, contacting said particles with a flexible matrix material, and applying said matrix material to one or more surfaces of a member.Type: GrantFiled: October 6, 2003Date of Patent: June 13, 2006Assignee: Head Sport AGInventor: Herfried J. Lammer
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Patent number: 7059042Abstract: A sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board. Accordingly, there are provided a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection reliability, a method of manufacturing the same, and a power module allowing its size to be reduced and its density to be increased.Type: GrantFiled: November 24, 2004Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
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Patent number: 7036223Abstract: A cabling method especially for installing thick electric cables (1) for connection to electric devices (8), in which method the cables (1) are brought to a cabling space (3), fitted and supported in place, cut and stripped at necessary locations, and the desired cables are equipped with cable shoes (6) or connectors for installing to the electric device (8), in which case the cabling steps are, before connection to the electric device (8), performed mainly outside the electric device (8) to be connected by using a separately arranged cabling part (3) comprising said cabling space (3). The invention also relates to this cabling part.Type: GrantFiled: October 14, 2002Date of Patent: May 2, 2006Assignee: ABB OYInventors: Matti Kauranen, Mikko Himmanen
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Patent number: 7031170Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.Type: GrantFiled: September 30, 2002Date of Patent: April 18, 2006Assignee: Infineon Technologies AGInventors: Frank Daeche, Franz Petter
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Patent number: 7024765Abstract: A method of manufacturing a surface-emitting backlight is provided with the steps of forming a lead frame and resin-made molded case by insert molding, attaching light sources, which are red, blue and green LED dies, to contacts of the lead frame provided in a hollow space of the molded case, forming a light guide section by filling the hollow space with a transparent or semitransparent resin, and thereafter attaching a reflector sheet, and lens sheets (or diffuser sheets) in accordance with the applications of the backlight.Type: GrantFiled: September 13, 2001Date of Patent: April 11, 2006Assignee: Ryoden Trading Company, LimitedInventor: Yasufumi Sakakibara
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Patent number: 7013559Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.Type: GrantFiled: October 31, 2002Date of Patent: March 21, 2006Assignee: Micron Technology, Inc.Inventors: Brad D. Rumsey, Matt E. Schwab
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Patent number: 6993812Abstract: Inner individual electrodes are formed at intervals on a piezoelectric ceramic layer so as to correspond in a one-to-one relationship with ink channels, and an inner common electrode are formed on another piezoelectric ceramic layer. The required number of piezoelectric ceramic layers with inner individual electrodes and with an inner common electrode are laminated alternately. An outer common electrode is connected to the inner common electrodes, and outer individual electrodes are connected to the respective inner individual electrodes. The capacitance between the outer common electrode and each of the outer individual electrodes is measured. A polarization electric field adjusted based on the measured value is applied between the common electrode and each of the outer individual electrodes to perform polarization.Type: GrantFiled: January 27, 2003Date of Patent: February 7, 2006Assignee: Brother Kogyo Kabushiki KaishaInventor: Yoshikazu Takahashi
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Patent number: 6973720Abstract: Method for manufacturing an elastic connector, integrated with an electrode of at least either a chip-type LED or a printed circuit board on which a LED element is directly mounted and to which the LED is electrically connected. The LED-integrated connector can subsequently be mounted on another circuit board by being sandwiched and compressed between a lower surface of the chip-type LED or lower surface of the LED-mounted printed circuit board and the other circuit board to which the LED-integrated connector is being mounted, so as to provide an electric connection. The method providing a LED-integrated connector which is thin and cost-effective while able to provide a simple and secure conductivity between electrodes of the chip-type LED and other circuit board, to which the LED-integrated connector is subsequently mounted.Type: GrantFiled: June 24, 2004Date of Patent: December 13, 2005Assignee: Citizen Electronics Co., Ltd.Inventors: Masakazu Koizumi, Shingo Mizuguchi, Tatsuji Hirano, Koichi Fukasawa, Hirohiko Ishii, Junji Miyashita
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Patent number: 6971171Abstract: The present invention provides a method for manufacturing an ink jet recording head utilizing ink bubbling by heating of an exothermic resistor to thereby eject ink and a method manufacturing the same, including the steps of: preparing a substrate provided with the exothermic resistor; applying such first resin on the substrate as to provide a first mold shape for forming the nozzle channel and the movable member; forming the first mold shape using the first resin; applying, on the substrate, second resin over the first mold shape for forming the nozzle channel and the movable member; and removing the first mold shape. By this method, the movable member is formed in the nozzle channel between the ink inlet and the exothermic resistor to thereby provide a high-density, high-accuracy ink jet recording head which can improve a frequency response while maintaining proper discharge performance.Type: GrantFiled: August 22, 2003Date of Patent: December 6, 2005Assignee: Canon Kabushiki KaishaInventors: Hirokazu Komuro, Masashi Miyagawa, Yoshinori Misumi, Masahiko Kubota, Hiroyuki Sugiyama, Ryoji Inoue
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Patent number: 6954983Abstract: A method for continuously producing flat cables with electric conductors embedded in an isolating material which are arranged at a certain distance from each other, parallel to each other. According to this invention, the band shaped conductors are guided separately in a plane forming two sides of a surface. The surface sides have insulating layers based on thermoplastic synthetic materials. According to this invention, at least one of the insulating layers which covers the surface sides is produced by extrusion coating of a thermoplastic melt.Type: GrantFiled: November 14, 2001Date of Patent: October 18, 2005Assignee: Reifenhäuser GmbH & Co MaschinenfabrikInventors: Karl Fröschl, Frank Bennerscheidt, Hartmut Halter
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Patent number: 6948239Abstract: A method for fabricating a semiconductor apparatus using a board frame. A wiring board region of the frame includes an island on which a semiconductor device is mounted. A marginal region of the frame surrounds the wiring board region. A frame region is located around the marginal region. A support region extends between the wiring board region and the frame region to connect the wiring board region and frame region together through the support region. The marginal region is removed from the board frame and then put back to its original position, while maintaining the wiring board region connected to the frame region through the support region. Then, the device is mounted onto the island. Next, transfer-molding is performed on the device using a die set that includes a gate through which a thermosetting resin is guided into a cavity. Then, the marginal region is removed completely from the board frame.Type: GrantFiled: December 12, 2002Date of Patent: September 27, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Takahiro Oka
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Patent number: 6941640Abstract: The present invention is directed to a miniature hard disc drive having a metal base plate, an actuator assembly wherein the actuator assembly comprises a plurality of bearings, a shaft, and a housing; a spindle motor assembly comprising a stator with conductors, a shaft, a plurality of bearings, and a rotor; and a monolithic body of phase change material unitizing said actuator assembly housing and stator to the base plate. Methods of developing and constructing the hard disc drive are also disclosed.Type: GrantFiled: October 25, 2001Date of Patent: September 13, 2005Assignee: Encap Motor CorporationInventors: Griffith D. Neal, Dennis K. Lieu
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Patent number: 6939746Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.Type: GrantFiled: April 26, 2002Date of Patent: September 6, 2005Assignee: Micron Technology, Inc.Inventor: Todd O. Bolken
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Patent number: 6935020Abstract: A method of producing a battery-connecting plate by providing busbars which connect batteries together, attaching terminals to one end of wires to produce terminal-attached wires for detecting voltage of desired ones of the batteries, placing the terminal-attached wires in a predetermined layout in a wire protector, setting the busbars and wire protector in a mold with the burbars positioned corresponding to an arrangement of the batteries, injecting resin into the mold to produce a molded piece with the burbars and the terminal-attached wires therein, and cutting an element mount portion of each of the terminals and connecting a respective circuit protector element to the element mount portion in a bridging manner across the cut.Type: GrantFiled: December 13, 2001Date of Patent: August 30, 2005Assignee: Yazaki CorporationInventor: Tomohiro Ikeda
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Patent number: 6922890Abstract: A method is provided for planarization of structures which minimizes step heights, reduces process steps, improves cleanliness, and provides increased ease of debond. Structures are placed with working surfaces facing down onto an adhesive layer such that structures remain fixed during heating. A bi-layer encapsulating film is used to achieve planarization. A carrier is bi-laminated with a thermoplastic film layer followed by a chemically inert protective polymer film layer that can withstand etch and cleaning processes. The thermoplastic layer is laminated on top of the carrier; the polymer layer is laminated on top of the joined thermoplastic layer and carrier. The carrier with bi-layer film is then placed onto the backside of the structures to resist chemical attack from the front side during photostrip and enable planarization. When heat is applied, the bi-layer encapsulating film melts and pushes the polymer layer into the gaps between structures thereby achieving complete planarization.Type: GrantFiled: November 15, 2002Date of Patent: August 2, 2005Assignee: International Business Machines CorporationInventors: Qing Dai, Jennifer Qing Lu, Dennis Richard McKean, Eun Row, Li Zheng
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Patent number: 6924967Abstract: An interposer connector for connecting an interdigitated capacitor to a substrate having a first track to be electrically connected to first capacitor terminals and an opposed second track to be electrically connected to second capacitor terminals. The interposer connector supports the interdigitated capacitor and has a first electrical conductor electrically connectable to the first track and the first capacitor terminals and a second electrical conductor electrically connectable to the second track substrate and the second capacitor terminals.Type: GrantFiled: April 30, 2004Date of Patent: August 2, 2005Inventor: Alan Devoe
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Patent number: 6889429Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.Type: GrantFiled: March 26, 2001Date of Patent: May 10, 2005Assignee: Semiconductor Components Industries, L.L.C.Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
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Patent number: 6868602Abstract: A structural frame (12) for dissipating heat from an electronic device (10) is provided. The structural frame (12), to which an electronic circuit board (14) containing a heat generating electronic component (16) is mounted, is injection molded from a thermally conductive, net-shape moldable polymer composition. The electronic component (16) that is within the device (10) is in thermal communication with the structural frame (12), so that the heat generated within the device (10) is transferred to the frame (14) and dissipated from the heat-generating device (10). An outer case (22) may be mounted to the frame (12) to finish the device (10) or the frame (12) may serve as all or a part of the outer device case (22) as well. In addition, the structural frame (12) has characteristics that may be engineered and used to shield the device (10) from electromagnetic interference.Type: GrantFiled: January 16, 2002Date of Patent: March 22, 2005Assignee: Cool Options, Inc.Inventor: Kevin A. McCullough
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Patent number: 6860004Abstract: In a method of manufacturing a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection, a sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board.Type: GrantFiled: December 3, 2002Date of Patent: March 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
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Patent number: 6823587Abstract: A method of making a data cable includes coupling an electrical conductor of an end of a cable to an electrical contact that is positioned within a portion of a connector housing. A protective clamp is positioned over a section of the cable rearwardly of the electrical contact. Another portion of the connector housing is formed over the cable section and the clamp, to thereby secure the cable with the connector housing. The protective clamp is positioned between the formed portion of the connector housing and the cable section and provides mechanical protection for the cable section to reduce damage thereto.Type: GrantFiled: August 5, 2002Date of Patent: November 30, 2004Assignee: Tensolite CompanyInventor: Bruce Reed
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Patent number: 6823585Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.Type: GrantFiled: March 28, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
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Patent number: 6813830Abstract: In a cable connector (1) in which a core wire (81a, 81c) of a cable (81) is pressed against a base contact (3) in a predetermined direction (a) intersecting the core wire, a support contact (5) is cooperated with the base contact to clamp the core wire therebetween in the predetermined direction. The base contact is coupled to a base insulator (2). The support contact is coupled to a cover insulator (4) movable against the base insulator in the predetermined direction. A partition wall (42) is formed integral with the cover insulator and positions the core wire to make the core wire face the base contact. When the cover insulator is moved towards the base insulator, the core wire becomes in press contact with the base contact.Type: GrantFiled: February 22, 2001Date of Patent: November 9, 2004Assignees: Japan Aviation Electronics Industry, Ltd., NEC CorporationInventors: Kazuki Saito, Osamu Hashiguchi, Hisashi Ishida, Shin Kamiyamane
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Patent number: 6779251Abstract: An assembly method for a vehicle anti-theft key having an embedded resistor pellet is provided. The resistor pellet includes a flange at one end which abuts one side of the key blade when the opposed end of the pellet is inserted into a through opening formed in the shank portion of the key blade. With the resistor pellet loosely positioned within the through opening, a second flange is attached to the end of the pellet that was inserted through the through opening, thereby capturing the pellet within the through opening by the two opposed flanges. In one embodiment, the second flange is formed in place by employing a polymeric molding process, such as a thermoforming injection molding process. A handle for the key is efficiently formed substantially simultaneously with the second flange using the same polymeric molding process.Type: GrantFiled: October 29, 2001Date of Patent: August 24, 2004Assignee: Hurd CorporationInventors: David C. Banks, Charles C. Edwards
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Patent number: 6779264Abstract: A method for manufacturing an electronic device by placing within a die a first lead with an element placement pad, a second lead, and an electronic element placed on the element placement pad. The electronic element, the element placement pad, a part of the first lead, and a part of the second lead are sealed in a package by injecting a sealing resin in the die from a position on a longer side of the package, with the position being offset toward one shorter side thereof. The first lead is bent in an S shape, with a bending depth being at least as large as the thickness of the first lead. A thickness of the resin on a non-device side of the element placement pad is smaller than the bending depth.Type: GrantFiled: October 8, 1999Date of Patent: August 24, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kobayashi, Hideki Fukazawa, Satoshi Utsunomiya
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Patent number: 6767767Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.Type: GrantFiled: July 16, 2002Date of Patent: July 27, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tetsuya Hayashida, Norihiko Kasai
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Patent number: 6745464Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.Type: GrantFiled: March 31, 2003Date of Patent: June 8, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
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Patent number: 6740543Abstract: The present invention is a method and apparatus for encapsulating semiconductor dies and other devices using stencil printing techniques. The apparatus includes a pressurized vessel for containing encapsulation material, the apparatus having a head including a slot through which the encapsulating material escapes into the apertures of the stencil. The head is angularly adjustable relative to the stencil and thus relative to the streets between the semiconductor dies that are in the apertures of the stencil so that the head can be adjusted to the optimal angle for filling both the vertical and horizontal streets between the dies and minimizing the creation of voids in the encapsulant. The method involves encapsulating semiconductor dies using a pressurized stencil printing machine having a slot through which the encapsulating material is forced into the apertures in the stencil and wherein the slot is at a large angle relative to both the vertical and horizontal streets.Type: GrantFiled: March 7, 2002Date of Patent: May 25, 2004Assignee: Kulicke & Soffa Industries, Inc.Inventor: Claire Rutiser
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Patent number: 6715200Abstract: Methods for forming data storage media and the media formed thereby are disclosed herein. In one embodiment, the method for forming a data storage media, comprises: injection molding a substrate comprising surface features, wherein said surface features have greater than about 90% of a surface feature replication of an original master; and disposing a data layer over at least one surface of said substrate; wherein said data storage media has an axial displacement peak of less than about 500&mgr; under shock or vibration excitation.Type: GrantFiled: May 1, 2001Date of Patent: April 6, 2004Assignee: General Electric CompanyInventors: Thomas P. Feist, Wit C. Bushko, Herbert S. Cole, John E. Davis, Thomas B. Gorczyca, Joseph T. Woods
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Patent number: 6706557Abstract: A stacked semiconductor package including a plurality of stacked semiconductor devices on a substrate, and a method of forming the same. The semiconductor devices are stacked in an active surface-to-backside configuration. The top semiconductor die is flipped over to face the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on the top semiconductor die to a bond pad on a substrate.Type: GrantFiled: April 24, 2003Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventor: Michel Koopmans
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Patent number: 6706547Abstract: After conductive patterns are formed on the conductive foil every block by employing isolation trenches, conductive plating layers are arranged selectively on the conductive patterns. Therefore, it is possible to accomplish the circuit device manufacturing method by which the die bonding of the circuit elements can be applied stably and the wire bonding can also be applied stably and which can fit to the mass-production while saving the resource.Type: GrantFiled: December 6, 2001Date of Patent: March 16, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Publication number: 20040017668Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Applicant: STMicroelectronics, Inc.Inventors: Harry M. Siegel, Anthony M. Chiu
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Patent number: 6675474Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.Type: GrantFiled: December 3, 2002Date of Patent: January 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Mitani, Hiroaki Takezawa, Yukihiro Ishimaru, Takashi Kitae, Yasuhiro Suzuki
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Patent number: 6677669Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.Type: GrantFiled: January 18, 2002Date of Patent: January 13, 2004Assignee: International Rectifier CorporationInventor: Martin Standing
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Patent number: 6668450Abstract: The invention relates to a method for the production of an MID device. Proceeding from a conductor track sheet, which comprises a support sheet as well as conductor tracks arranged thereon, a plastic body is injection-molded onto this conductor track sheet. The conductor tracks have a surface having numerous microscopically small projections and depressions and are designed so as to thereby produce a positively locking connection between the conductor tracks and the plastic body.Type: GrantFiled: June 28, 1999Date of Patent: December 30, 2003Assignee: Thomson Licensing S.A.Inventors: Hans-Otto Haller, Volker Strubel, Gunter Beitinger
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Patent number: 6658734Abstract: There is disclosed a resin-sealed semiconductor device in which plural circuit portions integrally having inner and outer terminals are arranged two-dimensionally substantially in a plane and electrically independent of one another, and have leads for integrally interconnecting the inner and outer terminals, surfaces of the circuit portions are semiconductor element mounted faces with the inner and outer terminals and the leads forming one plane, the inner terminals and the leads are thinner than the outer terminals, back surfaces of the circuit portions are provided with terminal faces of the inner and outer terminals, a terminal mounted face of the semiconductor element is mounted via an insulating layer onto the semiconductor element mounted faces of the circuit portions, and the semiconductor element terminals are electrically connected with wires to the terminal faces of the inner terminal, and the whole is sealed with a resin in such a manner that the outer terminals are partially exposed to the outsideType: GrantFiled: November 16, 2001Date of Patent: December 9, 2003Assignee: Dai Nippon Insatsu Kabushiki KaishaInventors: Syuichi Yamada, Makoto Nakamura, Takayuki Takeshita, Hiroshi Yagi
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Patent number: 6643919Abstract: A semiconductor device package fabrication method is proposed, which is used for the fabrication of a semiconductor device package of the type having a core-hollowed portion that is typically used to house an optically-sensitive semiconductor device such as an image sensor or an ultraviolet-sensitive EPROM (Electrically-Programmable Read-Only Memory) device. The proposed method is characterized in the use of a support pillar, which is positioned beneath the lead frame when the lead frame is clamped between a top inserted mold and a bottom cavity mold, to help prevent resin flash on the lead frame during the molding of the core-hollowed portion.Type: GrantFiled: May 19, 2000Date of Patent: November 11, 2003Assignee: Siliconware Precision Industries Co., Ltd.Inventor: Chien-Ping Huang