Including Parallel Paths (e.g., Current Mirror) Patents (Class 323/315)
  • Patent number: 10969815
    Abstract: The constant current circuit includes a constant current generation circuit, a start-up detection circuit configured to detect start-up of the constant current generation circuit, and a clamp circuit configured to output a start-up voltage to the constant current generation circuit. The start-up voltage output from the clamp circuit is a voltage close to gate voltages that are higher than gate voltages of transistors that form a current mirror circuit of the constant current generation circuit, in a state where the constant current generation circuit is operating.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: ABLIC INC.
    Inventor: Minoru Sano
  • Patent number: 10951208
    Abstract: A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 16, 2021
    Assignee: RACYICS GMBH
    Inventors: Stephan Henker, Monika Dietrich
  • Patent number: 10921840
    Abstract: A voltage generator includes a bias voltage generation circuit and a compensation circuit. The bias voltage generation circuit generates a first bias voltage based on a reference current and generates a second bias voltage based on the first bias voltage. The compensation circuit changes a voltage level of the first bias voltage based on the second bias voltage.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Tae Jin Hwang
  • Patent number: 10921352
    Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 16, 2021
    Assignee: Chrontel Inc.
    Inventors: David Chee-Fai Soo, Mohammad Yunus, Yiwei Wang
  • Patent number: 10885843
    Abstract: A pixel circuit for a display device operable in an initialization phase, a compensation phase, a data programming phase, and an emission phase, whereby the one horizontal time is minimized while maintaining accurate compensation of the threshold voltages of the drive transistors, and further accounting for any variations in the voltage supplies. The pixel circuit includes a first drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon voltages applied to a gate and a first terminal of the first drive transistor; and a second drive transistor that is configured as a source follower, wherein a first terminal of the second drive transistor is connected to a first power supply line and a second terminal of the second drive transistor is connected to a first terminal of the first drive transistor. The first drive transistor is one of a p-type or n-type transistor and the second drive transistor is the other of a p-type or n-type transistor.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 5, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tong Lu, Michael James Brownlow, Tim Michael Smeeton
  • Patent number: 10845839
    Abstract: A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (IIN) and generate a mirrored current (IM), where IM=K*IIN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1?m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 24, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Devrim Aksin, Omid Foroudi
  • Patent number: 10826472
    Abstract: A digital input circuit adopts a first state when an input signal is below a lower threshold value and adopts a second state when the input signal is above an upper threshold value. The digital input circuit comprises first and second subcircuits that exhibit a non-ideal current output behavior at least in the second state, and each comprises a current stabilizing element with a driving circuit and a voltage stabilizing element. The first and second subcircuits are configured such that, at least in a portion of the second state, an electric current flowing through the first subcircuit's voltage stabilizing element consists substantially of a stabilized current of the second subcircuit, and an electric current that flows through the second subcircuit's voltage stabilizing element consists substantially of a stabilized current of the first subcircuit, such that the non-ideal current output behavior of the first and second subcircuits compensate for each other.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Pilz GmbH & Co. KG
    Inventor: Bernd Harrer
  • Patent number: 10825487
    Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Tanaka, Yasunori Orito
  • Patent number: 10826473
    Abstract: A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 3, 2020
    Assignee: INTEGRATED SILICON SOLUTION, INC. BEIJING
    Inventors: Weikang Liu, Chia Yu Lin
  • Patent number: 10819237
    Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: October 27, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Gaetano Maria Walter Petrina, Joerg Kirchner
  • Patent number: 10784917
    Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sri Navaneethakrishnan Easwaran, Ted F. Lekan, Michael J. Zroka, Darren J. Rollman
  • Patent number: 10784794
    Abstract: A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventor: Michael A. de Rooij
  • Patent number: 10763850
    Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 1, 2020
    Assignee: FLEXTRONICS AP, LLC
    Inventor: Antony E. Brinlee
  • Patent number: 10732210
    Abstract: A sensor for sensing a parameter includes a control circuit that outputs a clock signal, a converter that receives the clock signal, generates a parameter-dependent voltage, and outputs an output voltage based on a comparison of the parameter-dependent voltage to a reference voltage. The sensor also includes a filter that receives the output voltage and counts a number of pulses of the clock signal based on a level of the output voltage.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chia Liang Tai
  • Patent number: 10720121
    Abstract: A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 21, 2020
    Assignee: DB HiTek Co., Ltd.
    Inventor: Ik Hyun Kim
  • Patent number: 10712760
    Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 14, 2020
    Assignee: IMEC VZW
    Inventors: Gaspard Hiblot, Bertrand Parvais
  • Patent number: 10691155
    Abstract: In accordance with an embodiment, a proportional to absolute temperature (PTAT) circuit includes a first bipolar transistor having a collector coupled to a common node; a second bipolar transistor having a collector coupled to the common node; a MOSFET having a load path coupled between a base of the first bipolar transistor and a base of the second bipolar transistor; and an amplifier having a first input coupled to an emitter of the first bipolar transistor, a second input coupled to an emitter of the second bipolar transistor and an output coupled to a gate of the MOSFET.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 23, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Stefan Marinca
  • Patent number: 10678289
    Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 9, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Mario Chiricosta
  • Patent number: 10672326
    Abstract: A pixel driving circuit includes a first transistor receiving a data signalsame. A first end of a second transistor is connected to the first end of the first transistor, and a gate of the same is connected to a second end of the second transistor. A second end of a third transistor is connected to the second end of the second transistor. A first end of a fourth transistor is connected to the gate of the first transistor. A second end of a fifth transistor is connected to the first end of the first transistor. A first end of the sixth transistor is connected to a second end of the first transistor. An anode of a light emitting diode is connected to a second end of the sixth transistor. A capacitor is connected between the first end and the gate of the first transistor.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 2, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Mao-Hsun Cheng
  • Patent number: 10664000
    Abstract: According to an embodiment, a power source circuit has first, second, and third one-conductivity-type transistors with commonly connected emitters, wherein the first transistor has an emitter area that is N times those of the second and third transistors. The power source circuit outputs a reference voltage that is set by a voltage drop that is caused at a resistance between bases of the first and second transistors and a forward voltage of a PN-junction diode, and outputs a BG_OK signal in response to a potential at a collector of the third transistor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: May 26, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuji Yamanaka
  • Patent number: 10635126
    Abstract: In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yoshiki Makiuchi
  • Patent number: 10620655
    Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Benoit Labbe, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Patent number: 10620656
    Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Cheng Lin, Kai-Yin Liu, Hui-Min Huang
  • Patent number: 10614861
    Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Tanaka, Yasunori Orito
  • Patent number: 10613572
    Abstract: Systems and devices are provided for generating a process, voltage, temperature (PVT)-independent reference current for a relatively low voltage domain. An apparatus may include a bandgap circuit that outputs a bandgap voltage and a first proportion-to-absolute temperature (PTAT) current. The apparatus may also include trimming circuitry that outputs a reference a voltage based at least in part on the bandgap voltage. Further, the apparatus may include reference current generation circuitry. In particular, the reference current generation circuitry may include a complementary-to-absolute-temperature (CTAT) current generation portion that generates a CTAT current based on the reference voltage as well as a PTAT current tuning portion that tunes a received first PTAT current to generate a second PTAT current.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Wei Lu Chu
  • Patent number: 10596987
    Abstract: An apparatus for controlling electric current includes a power supply for supplying a voltage, a driving circuit for receiving the voltage from the power supply to supply a first current to a load electrically connected thereto, and a control circuit electrically connected to the load and the driving circuit and for receiving the voltage from the power supply to supply a second current to the load.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 24, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: ChoongSeob Park, TaeSun Roh
  • Patent number: 10601414
    Abstract: A bias generator and a method for generating a bias voltage are presented. The bias generator is for use with an electronic circuit comprising a first switch coupled in series with a second switch. The bias generator is adapted to generate a reference voltage, a first bias voltage, and a second bias voltage. The second bias voltage is based on the reference voltage. After applying the first voltage to the first switch and the second voltage to the second switch, the bias generator controls a voltage across the first switch. The bias generator may be adapted to set a value of the reference voltage to control the voltage across the first switch. For instance, the reference voltage may be set to a fix value so that the voltage across the first switch is maintained at a constant value.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Zhi Mou, Mohammad Hanif, Mahbub Reja, Shobak Kythakyapuzha
  • Patent number: 10587227
    Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: March 10, 2020
    Assignee: Sony Corporation
    Inventors: Hideyuki Takano, Fumitaka Kondo, Norio Shoji
  • Patent number: 10588186
    Abstract: A driver port that provides selectable output currents based on connections thereto, and a driver including the same, is provided. A plurality of shunt resistors are connected in series between a negative output of a driver and a ground. A driver port having a plurality of connection points is provided, each respective connection point connected to a different connection between two of the plurality of shunt resistors. A load including one or more solid state light sources is capable of being connected between one of the connection points of the driver port and a positive output of the driver.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: March 10, 2020
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Nitin Kumar, Markus Ziegler, Naveen Tumula, Thomas Schalton
  • Patent number: 10534386
    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-An Chang, Chia-Fu Lee, Yu-Der Chih, Yi-Chun Shih
  • Patent number: 10503196
    Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sameer Wadhwa, Yi Wang, Lennart Mathe
  • Patent number: 10498242
    Abstract: A power stage output node stabilizer may be used to reduce ringing of a power stage output node of a switching DC-DC power converter. The power stage output node stabilizer may be a network of resistors and switches coupling the power stage output node to a higher voltage level and a lower voltage level.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: December 3, 2019
    Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
    Inventors: Bertrand Diotte, Mykhaylo Teplechuk
  • Patent number: 10488876
    Abstract: A circuit and a method using a pass device that is coupled between a supply voltage level and a load-connectable node of the circuit for providing a load current. A sense device forms a current mirror with the pass device. The sense device has transistor devices that can be switched to an active state, to adjust a mirror ratio of the current mirror. A first feedback loop regulates a voltage drop across the pass device to a predetermined value. A second feedback loop regulates a voltage drop across the sense device to the voltage drop across the pass device. Measurement circuitry sets a mirror ratio of the current mirror based on an indication of a current flowing through the sense device and generates an indication of current flowing through the pass device based on the set mirror ratio and the indication of the current flowing through the sense device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 26, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Thomas Jackum, Walter Meusburger
  • Patent number: 10469066
    Abstract: A system includes a trickle charge control circuit coupled to a charge pump and a motor driver circuit. The trickle charge control circuit is configured to sense a voltage at a bootstrap capacitor voltage node (VBST) of the motor driver circuit; as a result of the voltage at VBST being greater than a voltage at an input voltage node (VIN), couple a charge pump voltage node (VCP) to VBST of the motor driver circuit, where a voltage at VCP is greater than the voltage at VIN; and as a result of the voltage at VBST being less than the voltage at VIN, decouple VCP from the charge pump from VBST of the motor driver circuit.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 5, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Krishnamurthy Ganapathi Shankar
  • Patent number: 10461730
    Abstract: A gate driver circuit for driving a power switch includes a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver providing a primary gate current and an auxiliary gate current, and a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a power supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to a second input of the gate driver.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrea Luigi Francesco Mariconti, Wolfgang Frank, Christian Locatelli, Diego Raffo, Davide Respigo
  • Patent number: 10457237
    Abstract: A device for providing an activation voltage for a safety unit for a vehicle. The device includes a supply terminal for applying a first supply voltage potential, an activation terminal for outputting the activation voltage, and a control terminal for reading in a control signal. In addition, the device includes a pass-through switch that is connected between the supply terminal and the activation terminal, a first control switch, a second control switch, and a third control switch that includes a control input that is connected to the control terminal.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 29, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Hartmut Schumacher, Thomas Henig
  • Patent number: 10444776
    Abstract: According to one embodiment, a voltage-current conversion circuit includes an amplifier first, second and third inputs, a transistor including a first and second terminals, and a control terminal electrically connected to an output of the amplifier, and a serial connection including resistors connected in series between the first terminal and an ac ground, wherein a predetermined connecting point, among a first connecting point between the first terminal and the serial connection, a second connecting point between the ac ground and the serial connection, and one or more third connecting points between the resistors, is connected to the second input, and one of the connecting points other than the predetermined connecting point is connected to the third input.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 15, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Itakura, Yohei Hatakeyama
  • Patent number: 10437275
    Abstract: A current reference circuit and a semiconductor IC including the current reference circuit, the current reference circuit including a proportional to absolute temperature (PTAT) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the PTAT current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Young Shin
  • Patent number: 10401887
    Abstract: A circuit includes a startup circuit to provide a charging signal to initiate startup of a reference circuit. The startup circuit includes a detector circuit having a detector current path control, a level shifter having a level shifter current path control, and a charger circuit having a charger current path control. Each of the detector current path control, the level shifter current path control, and the charger circuit current path control enable current flow in the startup circuit when the charger turn-on signal is in the on-state and disable the current flow in the startup circuit when the charger turn-on signal is in the off state.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Devlopment LP
    Inventors: Tsung-Ching Huang, Chin-Hui Chen, Cheng Li
  • Patent number: 10393597
    Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*ln(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*ln(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventor: John M. Pigott
  • Patent number: 10381960
    Abstract: A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS EUROPE GMBH
    Inventor: Hans-Juergen Braun
  • Patent number: 10379566
    Abstract: An apparatus and method for a voltage reference circuit with flexible and adjustable voltage settings. A voltage reference circuit, comprising a PTAT Current Generator configured to provide current through a first resistor, a CTAT Current Generator configured to provide a CTAT current through a second resistor, a PTAT-CTAT Adder circuit configured to sum the PTAT current, and the CTAT current, wherein said sum of the PTAT and CTAT current through a third resistor is configured to provide an output voltage greater than a silicon bandgap voltage.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: August 13, 2019
    Assignee: Apple Inc.
    Inventors: Turev Acar, Selcuk Talay, Burak Dundar
  • Patent number: 10361732
    Abstract: An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Patent number: 10355673
    Abstract: An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Roh Yamamoto
  • Patent number: 10297317
    Abstract: A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit includes a transistor having a current path between the first node and a second node, and an amplifier circuit having a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the transistor. The amplifier circuit is configured to output a differentially amplified signal from the output port. A memory cell is connected between a bit line and a word line and includes a variable resistance element. The bit line can be connected to the second node. A sense amplifier is connected to the first node to detect data stored in the memory cell.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: May 21, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshinori Suzuki, Takayuki Miyazaki
  • Patent number: 10284095
    Abstract: A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells. The converter includes a plurality of current sense circuits for sensing current in a respective converter cell, each of the current sense circuits configured to generate a respective current sense signal, an averaging circuit for receiving each of the respective current sense signals and generating an average signal, a plurality of imbalance detector circuits for comparing a respective current sense signal with the average signal and generating a respective current imbalance signal, and a plurality of ON time generators for activating a converter cell for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 7, 2019
    Inventors: Alexander Mednik, Ioan Stoichita, Surya Talari
  • Patent number: 10250199
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 2, 2019
    Assignee: pSemi Corporation
    Inventors: Jonathan Klaren, Poojan Wagh, David Kovac, Eric S. Shapiro, Neil Calanca, Dan William Nobbe, Christopher Murphy, Robert Mark Englekirk, Emre Ayranci, Keith Bargroff, Tero Tapio Ranta
  • Patent number: 10205378
    Abstract: A circuit for providing a current flowing from a supply voltage into an electric load is presented. The circuit comprises a first circuit branch connected between the supply voltage and an output node connected to the electric load, wherein the first circuit branch comprises a first transistor device, a second circuit branch connected between the supply voltage and a predetermined voltage level, wherein the second circuit branch comprises a series connection of a second transistor device that is a scaled replica of the first transistor device and a current source. The control terminals of the first and second transistor devices are connected to each other. A control circuit is configured to control the voltage at the control terminal of the first transistor device depending on a current flowing through the first transistor device. The application further relates to a method of operating such circuit.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 12, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Danilo Gerna, Enrico Pardi
  • Patent number: 10168363
    Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: January 1, 2019
    Assignee: STMicroelectronics Design & Application S.R.O.
    Inventor: Sandor Petenyi
  • Patent number: 10170994
    Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 1, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Thomas J. Gibney, Larry D. Hewitt, Daniel L. Bouvier