Including Parallel Paths (e.g., Current Mirror) Patents (Class 323/315)
  • Patent number: 11314269
    Abstract: An electronic circuit for voltage regulation is disclosed, the circuit generally includes a low-dropout (LDO) voltage regulator function block, including a primary feedback loop, and an output voltage stabilizer block connected to the LDO voltage regulator function block outside the primary feedback loop, wherein the output voltage stabilizer block includes a plurality of peak voltage suppression circuits and a plurality of dip voltage suppression circuits. In some embodiments, the output voltage stabilizer block is set at low bias current to minimize current consumption at normal condition. Other useful features and advantages of an electronic circuit for voltage regulation are disclosed.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: April 26, 2022
    Assignee: Morse Micro PTY. LTD.
    Inventor: Hiroyuki Kimura
  • Patent number: 11296599
    Abstract: A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: April 5, 2022
    Assignee: Apple Inc.
    Inventors: Soheil Golara, Ali Mesgarani, Seyedeh Sedigheh Hashemi, Mansour Keramat
  • Patent number: 11244944
    Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
  • Patent number: 11237586
    Abstract: Disclosed is a reference voltage generating circuit including a bandgap reference voltage generating circuit, a voltage controlled current source circuit, a current mirror circuit, an input voltage generating circuit, and a voltage controlled voltage source circuit. The bandgap reference voltage generating circuit generates a bandgap reference voltage. The voltage controlled current source circuit generates a reference current according to the bandgap reference voltage. The current mirror circuit generates a mirrored current according to the reference current. The input voltage generating circuit determines an input voltage according to the mirrored current. The voltage controlled voltage source circuit generates a reference voltage according to the input voltage.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 1, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Leaf Chen
  • Patent number: 11223343
    Abstract: A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 11, 2022
    Assignee: NXP USA, Inc.
    Inventor: Robert Matthew Mertens
  • Patent number: 11199591
    Abstract: A current detection circuit includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 14, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yasuhiro Kakitsuka, Kazuyasu Minami, Takaya Yasuda
  • Patent number: 11150280
    Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 19, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Junhua Shen
  • Patent number: 11138496
    Abstract: Systems and/or devices for efficient and intuitive methods for implementing artificial neural networks specifically designed for parallel AI processing are provided herein. In various implementations, the disclosed systems, devices, and methods complement or replace conventional systems, devices, and methods for parallel neural processing that (a) greatly reduce neural processing time necessary to process more complex problem sets; (b) implement neuroplasticity necessary for self-learning; and (c) introduce the concept and application of implicit memory, in addition to explicit memory, necessary to imbue an element of intuition. With these properties, implementations of the disclosed invention make it possible to emulate human consciousness or awareness.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 5, 2021
    Inventor: Rohit Seth
  • Patent number: 11125787
    Abstract: A semiconductor device is provided and includes: a voltage sensing circuit configured to output first and second sensing voltages based on a target voltage applied thereto; and a comparing circuit configured to generate a monitoring output signal based on levels of the first and second sensing voltages, wherein the voltage sensing circuit includes: a first transistor including a gate to receive a reference bias voltage, a source connected to an input node, and a drain connected to one end of a first resistive element; a second transistor provided in a current mirror structure with the first transistor, and including a drain connected to a third resistive element; and a second resistive element connected to another end of the first resistive element, the first sensing voltage being provided to both ends of the second resistive element, and the second sensing voltage being provided to both ends of the third resistive element.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Do Hyung Kim, Min Young Kang
  • Patent number: 11119524
    Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 14, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher M. Dougherty, Anindya Bhattacharya, Vaibhav Pandey, Ying Ou
  • Patent number: 11101794
    Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deep Banerjee, Lokesh Kumar Gupta, Somshubhra Paul
  • Patent number: 11099595
    Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: August 24, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Germano Nicollini
  • Patent number: 11099590
    Abstract: A linear regulator with indirect leakage compensation is presented. The regulator has a pass device coupled between an input voltage and an output node, a feedback loop for controlling the pass device based on a reference voltage and a feedback voltage that depends on an output voltage, an off-state device that is kept in the off-state, and a leakage compensation circuit for sinking a leakage compensation current from the output node, in dependence on a leakage current of the off-state device. The off-state device is coupled between the leakage compensation circuit and an intermediate voltage level of the linear regulator. The intermediate voltage level is a voltage level between the input voltage level and ground, with a magnitude of the intermediate voltage level being smaller than a magnitude of the input voltage level. A corresponding method of operating a linear regulator with leakage compensation is presented.
    Type: Grant
    Filed: March 21, 2020
    Date of Patent: August 24, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Carlos Azevedo, Ambreesh Bhattad
  • Patent number: 11092991
    Abstract: A voltage generator circuitry includes first to third bipolar transistors having commonly-connected base electrodes, first and second current mirror circuitries, first and second differential amplifiers; a first resistor; and a current-voltage conversion circuitry. The first current mirror circuitry supplies currents to the first to third bipolar transistors and to the current-voltage conversion circuitry. The second current mirror circuitry supplies currents to the first to third bipolar transistors, and s to the current-voltage conversion circuitry. The first and second differential amplifiers control the first and second current mirror. The current-voltage conversion circuitry converts a sum current of the first and second currents into an output voltage.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 17, 2021
    Assignee: Synaptics Japan GK
    Inventor: Yasuhiko Sone
  • Patent number: 11086349
    Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.
    Type: Grant
    Filed: September 1, 2019
    Date of Patent: August 10, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Jen-Yu Peng, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11042177
    Abstract: A voltage-current conversion circuit includes a voltage-current conversion resistor connected to an input terminal, and a current mirror circuit which mirrors a current supplied from the voltage-current conversion resistor, wherein the current mirror circuit is constructed to include a depletion-type transistor whose source voltage is biased to be higher than the substrate voltage.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 22, 2021
    Assignee: ABLIC INC.
    Inventors: Yusuke Kanazawa, Yoichi Suto
  • Patent number: 11043919
    Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Toshihiko Yoshimasu, Tadamasa Murakami, Tsuyoshi Sugiura
  • Patent number: 11038503
    Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Efficient Power Conversion Corporation
    Inventors: Edward Lee, Ravi Ananth, Michael Chapman, Michael A. de Rooij
  • Patent number: 11036251
    Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 15, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Mario Chiricosta
  • Patent number: 11031771
    Abstract: A power supply control apparatus controls power supply via a semiconductor switch, by a driving circuit turning ON or OFF the semiconductor switch. A current circuit pulls in a current from the drain of the semiconductor switch via a resistance. The current value Ic of the current that is pulled in by the current circuit fluctuates in the same direction as a fluctuation direction of the ON resistance value of the semiconductor switch, depending on the ambient temperature of the semiconductor switch. If the source voltage of the semiconductor switch is lower than a voltage at the other end of the resistance, the driving circuit turns OFF the semiconductor switch.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 8, 2021
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kota Oda, Katsuma Tsukamoto, Keisuke Wakazono
  • Patent number: 11016524
    Abstract: The analog switch includes: a clock generation circuit configured to generate a first clock and a second clock; a transfer circuit including an NMOS transistor having a source and a back gate connected to each other, and a PMOS transistor having a source and a back gate connected to each other, one of which has a drain connected to the source of the other, and a source connected to a signal input terminal, and the other of which has a drain connected to a signal output terminal; a first control signal generation circuit configured to generate a control signal for switching the PMOS transistor based on a voltage at the signal input terminal and the first clock; and a second control signal generation circuit configured to generate a control signal for switching the NMOS transistor based on the voltage at the signal input terminal and the second clock.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 25, 2021
    Assignee: ABLIC INC.
    Inventor: Eiki Imaizumi
  • Patent number: 11019696
    Abstract: A method and apparatus for operating a semiconductor light source is presented. In particular there is a current regulator for regulating a current flowing through a light emitting diode device. The current regulator includes a first switch for receiving a first current flowing through the semiconductor light source and a control circuit coupled to the first switch and adapted to provide a second current proportional to the first current. The current regulator is adapted to regulate the first current using the second current.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 25, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Junyue Sun, Yufeng Zou, Huibin Cao, Lijie Chen
  • Patent number: 11018577
    Abstract: A charge pump circuit generates a charge pump voltage that powers a bias circuit. The bias circuit generates a reference current and generates switch currents from the reference current. Gate-source voltages are generated from the switch currents and applied to switching components of switch circuits to connect two nodes. The gate-source voltages can be generated in the bias circuit and provided to the switch circuits. The gate-source voltages can also be generated in the switch circuits.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 25, 2021
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Lei Huang
  • Patent number: 10969815
    Abstract: The constant current circuit includes a constant current generation circuit, a start-up detection circuit configured to detect start-up of the constant current generation circuit, and a clamp circuit configured to output a start-up voltage to the constant current generation circuit. The start-up voltage output from the clamp circuit is a voltage close to gate voltages that are higher than gate voltages of transistors that form a current mirror circuit of the constant current generation circuit, in a state where the constant current generation circuit is operating.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: ABLIC INC.
    Inventor: Minoru Sano
  • Patent number: 10951208
    Abstract: A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 16, 2021
    Assignee: RACYICS GMBH
    Inventors: Stephan Henker, Monika Dietrich
  • Patent number: 10921840
    Abstract: A voltage generator includes a bias voltage generation circuit and a compensation circuit. The bias voltage generation circuit generates a first bias voltage based on a reference current and generates a second bias voltage based on the first bias voltage. The compensation circuit changes a voltage level of the first bias voltage based on the second bias voltage.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Tae Jin Hwang
  • Patent number: 10921352
    Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 16, 2021
    Assignee: Chrontel Inc.
    Inventors: David Chee-Fai Soo, Mohammad Yunus, Yiwei Wang
  • Patent number: 10885843
    Abstract: A pixel circuit for a display device operable in an initialization phase, a compensation phase, a data programming phase, and an emission phase, whereby the one horizontal time is minimized while maintaining accurate compensation of the threshold voltages of the drive transistors, and further accounting for any variations in the voltage supplies. The pixel circuit includes a first drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon voltages applied to a gate and a first terminal of the first drive transistor; and a second drive transistor that is configured as a source follower, wherein a first terminal of the second drive transistor is connected to a first power supply line and a second terminal of the second drive transistor is connected to a first terminal of the first drive transistor. The first drive transistor is one of a p-type or n-type transistor and the second drive transistor is the other of a p-type or n-type transistor.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 5, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tong Lu, Michael James Brownlow, Tim Michael Smeeton
  • Patent number: 10845839
    Abstract: A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (IIN) and generate a mirrored current (IM), where IM=K*IIN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1?m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 24, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Devrim Aksin, Omid Foroudi
  • Patent number: 10825487
    Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Tanaka, Yasunori Orito
  • Patent number: 10826472
    Abstract: A digital input circuit adopts a first state when an input signal is below a lower threshold value and adopts a second state when the input signal is above an upper threshold value. The digital input circuit comprises first and second subcircuits that exhibit a non-ideal current output behavior at least in the second state, and each comprises a current stabilizing element with a driving circuit and a voltage stabilizing element. The first and second subcircuits are configured such that, at least in a portion of the second state, an electric current flowing through the first subcircuit's voltage stabilizing element consists substantially of a stabilized current of the second subcircuit, and an electric current that flows through the second subcircuit's voltage stabilizing element consists substantially of a stabilized current of the first subcircuit, such that the non-ideal current output behavior of the first and second subcircuits compensate for each other.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 3, 2020
    Assignee: Pilz GmbH & Co. KG
    Inventor: Bernd Harrer
  • Patent number: 10826473
    Abstract: A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 3, 2020
    Assignee: INTEGRATED SILICON SOLUTION, INC. BEIJING
    Inventors: Weikang Liu, Chia Yu Lin
  • Patent number: 10819237
    Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: October 27, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Gaetano Maria Walter Petrina, Joerg Kirchner
  • Patent number: 10784917
    Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sri Navaneethakrishnan Easwaran, Ted F. Lekan, Michael J. Zroka, Darren J. Rollman
  • Patent number: 10784794
    Abstract: A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventor: Michael A. de Rooij
  • Patent number: 10763850
    Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 1, 2020
    Assignee: FLEXTRONICS AP, LLC
    Inventor: Antony E. Brinlee
  • Patent number: 10732210
    Abstract: A sensor for sensing a parameter includes a control circuit that outputs a clock signal, a converter that receives the clock signal, generates a parameter-dependent voltage, and outputs an output voltage based on a comparison of the parameter-dependent voltage to a reference voltage. The sensor also includes a filter that receives the output voltage and counts a number of pulses of the clock signal based on a level of the output voltage.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chia Liang Tai
  • Patent number: 10720121
    Abstract: A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 21, 2020
    Assignee: DB HiTek Co., Ltd.
    Inventor: Ik Hyun Kim
  • Patent number: 10712760
    Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 14, 2020
    Assignee: IMEC VZW
    Inventors: Gaspard Hiblot, Bertrand Parvais
  • Patent number: 10691155
    Abstract: In accordance with an embodiment, a proportional to absolute temperature (PTAT) circuit includes a first bipolar transistor having a collector coupled to a common node; a second bipolar transistor having a collector coupled to the common node; a MOSFET having a load path coupled between a base of the first bipolar transistor and a base of the second bipolar transistor; and an amplifier having a first input coupled to an emitter of the first bipolar transistor, a second input coupled to an emitter of the second bipolar transistor and an output coupled to a gate of the MOSFET.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 23, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Stefan Marinca
  • Patent number: 10678289
    Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 9, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Mario Chiricosta
  • Patent number: 10672326
    Abstract: A pixel driving circuit includes a first transistor receiving a data signalsame. A first end of a second transistor is connected to the first end of the first transistor, and a gate of the same is connected to a second end of the second transistor. A second end of a third transistor is connected to the second end of the second transistor. A first end of a fourth transistor is connected to the gate of the first transistor. A second end of a fifth transistor is connected to the first end of the first transistor. A first end of the sixth transistor is connected to a second end of the first transistor. An anode of a light emitting diode is connected to a second end of the sixth transistor. A capacitor is connected between the first end and the gate of the first transistor.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 2, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Mao-Hsun Cheng
  • Patent number: 10664000
    Abstract: According to an embodiment, a power source circuit has first, second, and third one-conductivity-type transistors with commonly connected emitters, wherein the first transistor has an emitter area that is N times those of the second and third transistors. The power source circuit outputs a reference voltage that is set by a voltage drop that is caused at a resistance between bases of the first and second transistors and a forward voltage of a PN-junction diode, and outputs a BG_OK signal in response to a potential at a collector of the third transistor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: May 26, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuji Yamanaka
  • Patent number: 10635126
    Abstract: In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yoshiki Makiuchi
  • Patent number: 10620655
    Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Benoit Labbe, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Patent number: 10620656
    Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Cheng Lin, Kai-Yin Liu, Hui-Min Huang
  • Patent number: 10614861
    Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hitoshi Tanaka, Yasunori Orito
  • Patent number: 10613572
    Abstract: Systems and devices are provided for generating a process, voltage, temperature (PVT)-independent reference current for a relatively low voltage domain. An apparatus may include a bandgap circuit that outputs a bandgap voltage and a first proportion-to-absolute temperature (PTAT) current. The apparatus may also include trimming circuitry that outputs a reference a voltage based at least in part on the bandgap voltage. Further, the apparatus may include reference current generation circuitry. In particular, the reference current generation circuitry may include a complementary-to-absolute-temperature (CTAT) current generation portion that generates a CTAT current based on the reference voltage as well as a PTAT current tuning portion that tunes a received first PTAT current to generate a second PTAT current.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Wei Lu Chu
  • Patent number: 10596987
    Abstract: An apparatus for controlling electric current includes a power supply for supplying a voltage, a driving circuit for receiving the voltage from the power supply to supply a first current to a load electrically connected thereto, and a control circuit electrically connected to the load and the driving circuit and for receiving the voltage from the power supply to supply a second current to the load.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 24, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: ChoongSeob Park, TaeSun Roh
  • Patent number: 10601414
    Abstract: A bias generator and a method for generating a bias voltage are presented. The bias generator is for use with an electronic circuit comprising a first switch coupled in series with a second switch. The bias generator is adapted to generate a reference voltage, a first bias voltage, and a second bias voltage. The second bias voltage is based on the reference voltage. After applying the first voltage to the first switch and the second voltage to the second switch, the bias generator controls a voltage across the first switch. The bias generator may be adapted to set a value of the reference voltage to control the voltage across the first switch. For instance, the reference voltage may be set to a fix value so that the voltage across the first switch is maintained at a constant value.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Zhi Mou, Mohammad Hanif, Mahbub Reja, Shobak Kythakyapuzha