With Amplifier Connected To Or Between Current Paths Patents (Class 323/316)
  • Patent number: 11355164
    Abstract: A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ming-ta Hsieh, Taylor Loftsgaarden
  • Patent number: 11320846
    Abstract: The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 3, 2022
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan Wang, Gangyi Hu, Tao Liu, Jian'an Wang, Daiguo Xu, Guangbing Chen, Dongbing Fu
  • Patent number: 11316528
    Abstract: A pulse width modulation (PWM) digital-to-analog conversion circuit includes switches 102, 104, 114, 116 controlled by a first PWM signal, and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter, and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104, and an output of a third op-amp is coupled to the output of the first op-amp via switches 114 and 116. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108, and an output of the third op-amp is coupled to the input of the filter via switches 110 and 112.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 26, 2022
    Assignee: Fluke Corporation
    Inventor: Denny E. Henson
  • Patent number: 11287839
    Abstract: A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 29, 2022
    Assignee: Apple Inc.
    Inventors: Sujan K. Manohar, Jay B. Fletcher, Nathan F. Hanagami
  • Patent number: 11251701
    Abstract: A high voltage tolerant output circuit includes a boost circuit, a first bias circuit, and a buffer circuit. The boost circuit includes a first transistor and an output node. A first terminal of the first transistor is coupled with the output node. The first bias circuit is coupled with the output node and a control terminal of the first transistor, and for dividing the output voltage of the output node. The first bias circuit is further configured to transmit the divided output voltage to the control terminal of the first transistor. The buffer circuit is coupled with a second terminal of the first transistor, and for setting a first voltage of the second terminal of the first transistor. The output voltage is positive correlated to the first voltage, and a maximum value of the output voltage is higher than or equal to a maximum value of the first voltage.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-I Kuo, Yi-Jang Wu, Chun-Ta Ho, Cheng-Yu Liu
  • Patent number: 11239806
    Abstract: An ultra-low power sub-threshold gm stage is disclosed where transconductance is very stable with process, temperature, and voltage variations. This technique can be implemented in a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain can achieve a small temperature coefficient of 48.6 ppm/° C. and exhibits small sigma of 75 mdB with process. The second order biquad can achieve temperature stability of 69 ppm/° C. and a voltage coefficient of only 49 ppm/mV.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 1, 2022
    Assignee: Northeastern University
    Inventor: Aatmesh Shrivastava
  • Patent number: 11159193
    Abstract: A line driver circuit has first and second differential input terminals and first and second differential output terminals, and is configured to interface with first and second termination impedances coupled between the first and second differential output terminals, respectively, and first and second transmit chain output terminals, respectively. The line driver circuit includes an amplifier circuit having first and second input terminals coupled to the first and second differential input terminals of the line driver circuit, respectively, and first and second output terminals coupled to the first and second differential output terminals of the line driver circuit, respectively, and an impedance switching circuit coupled between the first and second output terminals of the amplifier circuit.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: October 26, 2021
    Assignee: MaxLinear, Inc.
    Inventors: Christian Fleischhacker, Rainer Strobel
  • Patent number: 11150682
    Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Kuno Lenz
  • Patent number: 11095222
    Abstract: A high efficiency converter is provided. The converter can be used in applications requiring fast transient response under a first loading condition, and high efficiency under a second loading condition. The converter converts one or more input voltages via two or more conversion paths. Each of the two or more conversion paths corresponds to a different loading condition which indicates a magnitude of a load driven by the converter (e.g., heavy or light), and a target transient response of the load (e.g., fast or slow). A conversion path for a heavy or fast loading condition converts an input voltage directly to a target output voltage. A conversion path for a light or slow loading condition includes a two-stage architecture.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 17, 2021
    Assignee: MediaTek Inc.
    Inventors: Chih-Chen Li, Yen-Hsun Hsu, Tzu-Chi Huang
  • Patent number: 10979555
    Abstract: The present subject matter relates to one or more devices, systems and/or methods for generating sealing current at a customer's premises or residence and injecting the sealing current into a DSL service provider's telephone cables to prevent the oxidation or corrosion of wire splices or connections on the telephone cables transporting DSL services. A cable pair stabilizer unit is connected at the customer's premises or residence, between the service provider's telephone cables and the customer's residential gateway/modem. The cable pair stabilizer unit comprises circuitry for generating the sealing current and for injecting the sealing current into the service provider's telephone cables transporting DSL services. The cable pair stabilizer unit may be combined with an AC/DC power supply adapter as a single, integrated device. The cable pair stabilizer unit may alternatively be combined with or inside of the Residential Gateway as a single, integrated device.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 13, 2021
    Assignee: Enginuity Communications Corp.
    Inventors: Sean Iwasaki, Stephen M. Todd
  • Patent number: 10935639
    Abstract: Systems and circuits directed to a time-of-flight measurement system are provided. More specifically, an illustrative optical sensor is disclosed to include a plurality of avalanche photodiodes, at least one of the plurality of avalanche photodiodes being in communication with amplifier common node through an impedance converter that is responsive to a control signal and selectively connects or disconnects the at least one avalanche photodiode from the common node based on the control signal. In an example, the impedance converter is also configured to preserve current generated from the at least one avalanche photodiode.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 2, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Milos Davidovic, Reinhard Enne, Gunther Leopold Steinle
  • Patent number: 10873257
    Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Regents of the University of Minnesota
    Inventors: Ramesh Harjani, Saurabh Chaubey
  • Patent number: 10868527
    Abstract: Aspects of the present disclosure address a slew rate controlled driver. The slew rate controlled driver includes an amplifier with a capacitive feedback loop and a current generator capable of producing a current that is proportional to on-chip capacitance. The current generator is implemented using a switched capacitor and supplies the driver with a current that is proportional to the capacitance of the switched capacitor. By supplying the driver with current that is proportional to the capacitance of the switched capacitor, the slope of the output signal of the driver is proportional to the ratio of the switched capacitance and a capacitance of the driver's capacitive feedback loop.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Humberto Andrade de Fonseca
  • Patent number: 10859630
    Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 8, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Hung-Sen Kuo, Te-Wei Chen, Hung-Sheng Chang, Ming-Wan Kuan
  • Patent number: 10826385
    Abstract: Provided is a power factor correction circuit including an inductor having one end to which an input voltage is applied; a power switch connected between another end of the inductor and the ground, and configured to control an output of the power factor correction circuit; and a power factor correction controller configured to calculate a duty of the power switch on the basis of an output detection voltage corresponding to the output and an inductor current flowing through the inductor, calculate conduction-period information regarding a conduction period in which the inductor current flows in one switching cycle of the power switch, and compensate the calculated duty on the basis of the conduction-period information.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jintae Kim, Hangseok Choi, SangCheol Moon
  • Patent number: 10803912
    Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yadhu Vamshi Vancha, Ali Al-Shamma, Yingchang Chen, Jeffrey Lee, Tz-Yi Liu
  • Patent number: 10727827
    Abstract: A switching circuit includes back-to-back NMOS transistors coupled between first and second pins. A first PMOS transistor is coupled between an upper supply voltage and a first node and has a gate coupled to receive a first enable signal. First and second current mirrors are coupled in series to the first node and a resistor is coupled in parallel with the first current mirror. A first leg of the first and second current mirrors is coupled to a lower supply voltage through a second PMOS transistor and a second leg is coupled to the gates of the back-to-back NMOS transistors. The gate of the second PMOS transistor is coupled to a node that lies between the back-to-back NMOS transistors. Additional NMOS transistors couple the lower supply voltage to the gates and sources of the back-to-back NMOS transistors and also to the gate of the first current mirror.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 28, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Carsten Ingo Stoerk
  • Patent number: 10715128
    Abstract: Provided is a power supply voltage detection circuit that prevents offsetting from occurring due to different voltages being applied for an extended period of time to gates of two transistors that constitute a differential pair in a comparator circuit that compares a comparison voltage that is generated based on a power supply voltage to a reference voltage. This power supply voltage detection circuit has a reference voltage generation circuit, a comparison voltage generation circuit, and a comparator circuit that includes a first transistor and a second transistor that constitute a differential pair and each have a gate to which a same bias voltage is applied, and a third transistor and a fourth transistor that are respectively connected in series to the first and second transistors and have sources to which the reference voltage and the comparison voltage are respectively applied.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Nobuyuki Oikawa, Toshikazu Kuwano
  • Patent number: 10663994
    Abstract: A voltage reference generator which can be automatically calibrated has a first mode and a second mode. The voltage reference generator provides a bandgap reference voltage with a voltage reference node having a capacitance. Calibration logic, which can be on the same integrated circuit device as the voltage reference generator, executes a calibration sequence including enabling the voltage reference generator in the first mode to produce a voltage on the voltage reference node, holding the voltage by the capacitance, and then enabling the voltage reference generator in the second mode and calibrating the voltage reference generator in the second mode relative to the voltage held on the voltage reference node, to provide the bandgap reference voltage.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 26, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiao-Ming Lin
  • Patent number: 10634705
    Abstract: A first resistor and a second resistor are coupled in series between a voltage source and an active load. When the current drawn by the active load exceeds a current threshold corresponding to a maximum admissible voltage drop across the first resistor, a stabilization current is delivered to the node common to the series coupled first and second resistors in such a way as to stabilize the voltage on the terminals of the active load at a threshold value. In the presence of such a current in excess of the current threshold, the current consumed by the active load is measured from the voltage drop across the second resistor. Conversely, if the current is less than the current threshold, the current consumed by the active load is measured from the voltage drop across the first resistor.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 28, 2020
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Patrick Almosnino
  • Patent number: 10605676
    Abstract: A method includes: calculating a first calibration temperature based on a first ratio of a known external voltage to a delta voltage that is a difference between first and second base-emitter voltages of first and second sensing transistors, calculating a first sensed temperature based on a second ratio of the first base-emitter voltage to the delta voltage, adjusting one or more temperature fitting parameters based on a comparison of the first sensed temperature with the first calibration temperature; activating the on-chip heater; calculating a second calibration temperature based, at least in part, on a third ratio of the known external voltage to the delta voltage, calculating a second sensed temperature based on a fourth ratio of the first base-emitter voltage to the delta voltage, adjusting at least one of the one or more temperature fitting parameters based on a comparison of the second sensed temperature with the second calibration temperature.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 31, 2020
    Assignee: NXP B.V.
    Inventors: Bahman Yousefzadeh, Kamran Souri, Kofi A. A. Makinwa
  • Patent number: 10591938
    Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Soheil Golara
  • Patent number: 10547193
    Abstract: A battery charging circuit adjusts a voltage proportional relationship between a turned-on voltage of a charging transistor and a turned-on voltage of a first transistor according to a first voltage corresponding to a charging current and a second voltage corresponding to the charging current, so that a ratio between the charging current and a first current sensing the charging current is a constant value or close to a constant value.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 28, 2020
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Chih-Ning Chen
  • Patent number: 10491118
    Abstract: A voltage comparator for detecting a voltage difference in a high-voltage domain, wherein said comparator receives an input voltage and compares it with a reference voltage also received in input, in which the output voltage from the comparator assumes the logic value 1 if the input voltage is greater than the reference voltage and assumes the logic value 0 if the input voltage is less than or equal to the reference voltage, wherein said comparator comprises low-voltage components and a single high-voltage component. In particular, the low-voltage components are MOS transistors and the high-voltage component is a high-voltage PMOS.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 26, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Iorio, Jeanpierre Vicquery, Emilio Volpi
  • Patent number: 10429878
    Abstract: A test device is provided. An output terminal of an operational amplifier is coupled to a device under test. A current replication circuit copies a current flowing through a charging circuit and a discharge circuit according to voltages of control terminals of the charging circuit and the discharge circuit in the operational amplifier and outputs a test result signal.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 1, 2019
    Assignee: eMemory Technology Inc.
    Inventor: Yu Wu
  • Patent number: 10416702
    Abstract: A first current proportional to absolute temperature flows in a first current line through a first p-n junction and a second p-n junction arranged in series. A cascaded arrangement of p-n junctions is coupled to the second p-n junction and includes a further p-n junction with a current flowing therethrough that has a third order proportionality on absolute temperature. A differential circuit has a first input coupled to the further p-n junction and a second input coupled to a current mirror from the first p-n junction, with the differential circuit configured to generate a bandgap voltage with a low temperature drift from a sum of first voltage (that is PTAT) derived from the first current and a second voltage (that is PTAT3) derived from the third current.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronic S.r.l.
    Inventors: Germano Nicollini, Stefano Polesel
  • Patent number: 10401888
    Abstract: A low-dropout voltage regulator (LDO) apparatus is disclosed. In an embodiment, the LDO apparatus includes a voltage input connectable to a power supply, an error amplifier coupled to the voltage input and configured to receive a reference signal and a feedback signal and to generate an output control signal dependent on the reference signal and the feedback signal, and a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current dependent on the output control signal. The LDO apparatus further includes a detection circuit coupled to the voltage input and configured to provide an output signal on its output and a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: September 3, 2019
    Assignee: TDK Corporation
    Inventors: Lei Zou, Gino Rocca
  • Patent number: 10381051
    Abstract: A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP USA, INC.
    Inventors: Birama Goumballa, Cristian Pavao Moreira, Pierre Pascal Savary
  • Patent number: 10359801
    Abstract: The present disclosure relates to a voltage reference generator without temperature dependency. The disclosed voltage reference generator includes a precursor voltage generator and a voltage extractor. The precursor voltage generator is configured to provide a base-emitter voltage, a proportional-to-absolute-temperature (PTAT) voltage, and a nonlinear (NL) voltage. The voltage extractor is configured to scale and sum the base-emitter voltage, the NL voltage, and the PTAT voltage and provide an output voltage, such that linear temperature dependent components and nonlinear temperature dependent components within the base-emitter voltage, the NL voltage, and the PTAT voltage are not included in the output voltage, which is temperature independent.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 23, 2019
    Assignee: Iowa State University Research Foundation, Inc.
    Inventors: Degang James Chen, Zhiqiang Liu
  • Patent number: 10353414
    Abstract: In some examples, a bandgap reference circuit comprises a first bandgap pair having multiple first diodes and a first resistor positioned between the multiple first diodes. The circuit also comprises a second bandgap pair having multiple second diodes and a second resistor positioned between the multiple second diodes, the second bandgap pair being an inverted form of the first bandgap pair. The circuit further comprises a scaling resistor coupled to the first and second bandgap pairs. The circuit still further comprises an operational amplifier coupled to the first and second bandgap pairs.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sandeep Shylaja Krishnan
  • Patent number: 10345833
    Abstract: A current to be supplied to a load driven by the current is linearly controlled in accordance with a voltage. A voltage-current converter according to the present invention includes a differential amplifier, a first current mirror, and a voltage setting unit. The differential amplifier receives an input voltage from an input terminal and outputs a voltage in accordance with a difference between the input voltage and a threshold voltage. The first current mirror receives the voltage from the differential amplifier and outputs an output current to an output terminal. The voltage setting unit sets the threshold voltage.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yo Habu, Mitsutaka Hano
  • Patent number: 10317925
    Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Rajavelu Thinakaran, Sumit Dubey
  • Patent number: 10310526
    Abstract: An low dropout regulator and method that has reduced quiescent current consumption is presented. The voltage regulator circuit comprises an output terminal, a first circuit branch connected between an input voltage level and the output terminal, a second circuit branch connected between the input voltage level and a predetermined voltage level, a first current mirror for mirroring a current flowing in the second circuit branch to the first circuit branch, a first feedback circuit to regulate the output voltage, and a second feedback circuit for controlling the second switching element. The second feedback circuit comprises a current sensing means for sensing a current that depends on a current flowing in the first circuit branch and to control the second switching element such that the current flowing through the second circuit branch is limited to a current that depends on the current sensed by the current sensing means.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 4, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Slawomir Malinowski, Robert Goslawski
  • Patent number: 10298748
    Abstract: The present subject matter relates to one or more devices, systems and/or methods for generating sealing current at a customer's premises or residence and injecting the sealing current into a DSL service provider's telephone cables to prevent the oxidation or corrosion of wire splices or connections on the telephone cables transporting DSL services. A cable pair stabilizer unit is connected at the customer's premises or residence, between the service provider's telephone cables and the customer's residential gateway/modem. The cable pair stabilizer unit comprises circuitry for generating the sealing current and for injecting the sealing current into the service provider's telephone cables transporting DSL services. The cable pair stabilizer unit may be combined with an AC/DC power supply adapter as a single, integrated device. The cable pair stabilizer unit may alternatively be combined with or inside of the Residential Gateway as a single, integrated device.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 21, 2019
    Assignee: Enginuity Communications Corp.
    Inventors: Sean Iwasaki, Stephen M. Todd
  • Patent number: 10289145
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Patent number: 10234487
    Abstract: A current sense circuit for a pass transistor is described. The circuit comprises a sense transistor having input and control ports that are coupled to input and control ports respectively of the pass transistor. The circuit comprises a differential amplifier comprising a differential input and output. An output port of the pass transistor is coupled to a first port of the differential input and an output port of the sense transistor is coupled to a second port of the differential input. The differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel and which are operated in an auto-zero phase and in an amplification phase in an alternating manner, and which are operated in the auto-zero phase in a mutually exclusive manner. The output of the differential amplifier is used to control voltage drops across the sense transistor and the pass transistor.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 19, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Nicolo Nizza, Danilo Gerna
  • Patent number: 10191105
    Abstract: A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 29, 2019
    Assignee: ATOMERA INCORPORATED
    Inventor: Richard Stephen Roy
  • Patent number: 10152078
    Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
  • Patent number: 10146240
    Abstract: A voltage regulator having a pre-regulator circuit is disclosed. A low dropout (LDO) voltage regulator includes an amplifier circuit, a current buffer circuit, and a pre-regulator circuit. The current buffer circuit includes a transistor having a gate terminal coupled to the amplifier output. The current buffer provides a current based at least in part on the output signal generated by the amplifier. The pre-regulator circuit is coupled to provide a dynamic supply voltage to the current buffer. They dynamic supply voltage depends at least in part on a fixed supply voltage provided thereto, as well as the output voltage provided by the LDO voltage regulator.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 4, 2018
    Assignee: Apple Inc.
    Inventors: Ruopeng Wang, Dashun Xue, Jiandong Jiang, Jay B. Fletcher
  • Patent number: 10128821
    Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Patent number: 10128807
    Abstract: A system improve amplifier efficiency of operation relative to that of an amplifier with fixed biasing is operating channel dependent. A control circuit determines a bias current for an amplifying transistor of an amplifier circuit based at least in part on an operating channel. The amplifying transistor operates in a multi-channel system, where the bias current for the amplifying transistor operating at channels at an edge of a channel band is different from the bias current for the amplifying transistor operating at channels nearer a center of the channel band.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 13, 2018
    Assignee: SiGe Semiconductor, Inc.
    Inventors: Alan J. A. Trainor, Grant Darcy Poulin, Craig Joseph Christmas
  • Patent number: 10095252
    Abstract: A voltage-to-current converter includes an input stage having a first input and a second input. The first input is connectable to a reference voltage, wherein the voltage of the second input is substantially the same as the voltage at the first input. A feedback loop is coupled between the second input and a voltage feedback node. A current feedback node is connectable to a first node of a resistor; the second node of the resistor is connectable to a voltage input, wherein a bias voltage of the current feedback node is set by the voltage of the voltage feedback node. At least one current mirror mirrors the current input to the current feedback node, the output of the at least one current mirror is the output of the voltage-to-current converter.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dinesh Jain
  • Patent number: 10090826
    Abstract: Various technologies pertaining to a high-impedance current source are described herein. The current source outputs a substantially constant current by way of a first transistor that draws current from a supply. The current source is configured to feed back noise from the supply to a feedback resistor at an input of an operational amplifier (op-amp) by way of a second transistor. The feedback resistor and the op-amp are configured such that responsive to receiving the supply noise feedback, the op-amp drives a gate voltage of the first transistor to cause the first transistor to reject the supply noise and cause the output of the current source to remain substantially constant.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 2, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Kurt O. Wessendorf
  • Patent number: 10067522
    Abstract: As one example of the invention disclosed herein, a reference voltage generation circuit has: a first reference voltage source generating a first reference voltage; a second reference voltage source generating a second reference voltage having a temperature response different from that of the first reference voltage; a first comparator comparing the first and second reference voltages to generate a first comparison signal; and a selector selectively outputting one of the first and second reference voltages as a reference voltage according to the first comparison signal.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 4, 2018
    Assignee: Rohm Co., Ltd.
    Inventors: Yusuke Yoshii, Yuki Inoue
  • Patent number: 10061444
    Abstract: Self capacitance touch circuits to cancel the effects of parasitic capacitance in a touch sensitive device are disclosed. One circuit can generate a parasitic capacitance cancelation signal that can be injected into touch sensing circuitry to cancel the parasitic capacitance. Another circuit can adjust the phase and magnitude of the parasitic capacitance cancelation signal based on characteristics of channels in the touch sensing circuitry so as to fine tune the parasitic capacitance cancelations. Another circuit can drive a guard plate and touch panel electrodes so as to cancel the parasitic capacitances between the panel and the plate and between the electrodes.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 28, 2018
    Assignee: Apple Inc.
    Inventors: Shahrooz Shahparnia, Christoph H. Krah
  • Patent number: 10041983
    Abstract: A current sense circuit for a pass transistor is described. The current sense circuit comprises a sense transistor, a differential amplifier comprising a differential input and a differential output, and a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input and wherein the output port of the sense transistor is coupled to a second port of the main differential input. The output of the DD amplifier is used to control a voltage drop across the sense transistor and the pass transistor.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 7, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Danilo Gerna, Stefano Scaldaferri, Nicolo Nizza
  • Patent number: 10007282
    Abstract: Provided is a voltage regulator capable of stably generating a constant output voltage even in a high temperature environment. The voltage regulator includes: an output transistor; an output terminal connected to a drain of the output transistor and outputting an output voltage; an error amplifier circuit configured to supply a signal obtained by amplifying a difference between a divided voltage of the output voltage and a reference voltage to a gate of the output transistor; and an NMOS transistor connected between the output terminal and a reference potential and configured to turn on, when the voltage regulator reaches a predetermined temperature at which a leakage current flowing in the output transistor is absorbed, to lead the leakage current to the reference potential.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 26, 2018
    Assignee: ABLIC INC.
    Inventor: Michiyasu Deguchi
  • Patent number: 9989985
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 5, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Patent number: 9958895
    Abstract: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Chen, Mark Shane Peng
  • Patent number: 9954431
    Abstract: A starting circuit (10) of a power management chip, comprising: a starting capacitor (C3) which is used for connecting a power supply via an external resistor (R2) to perform charging; a switch circuit (100) which is connected between the external resistor (R2) and the starting capacitor (C3); a voltage detection circuit (200) which is used for detecting a voltage on the starting capacitor (C3) and is connected to the switch circuit (100) so as to control the on/off switching of the switch circuit (100); and a voltage maintaining circuit (300) which is connected between the starting capacitor (C3) and an operating circuit of the power management chip and is used for acquiring a voltage that maintains the starting capacitor (C3) from the operating circuit of the power management chip, wherein when the voltage detection circuit (200) detects that the starting capacitor (C3) reaches the starting voltage of the power management chip, the broken circuit of the switch circuit (100) is controlled.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 24, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Nan Zhang