Abstract: The present invention is directed towards systems and methods for predicting one or more desired properties of external nodes or properties of their relations with internal nodes, based on a selected group of nodes about which it is known whether the nodes have the desired properties, or it is known whether they have a desired relation property with an internal node. The method comprises storing in one or more data structures a first data set regarding external nodes and a second data set regarding nodes with known properties in a selected group, each data set having one or more data items representing one or more events relating to or attributes of each node in the data set, the second data set including one or more types of data items not included in the first data set.

Abstract: Embodiments of methods and apparatuses for characterizing an electrical power distribution system are disclosed. One method includes applying, by at least one test/response unit, at least one test signal to at least one test point of the system, measuring, by a plurality of test/response units, a plurality of response signals at a plurality of test points, wherein the plurality of response signals are generated in response to the at least one test signal, and characterizing the system based on the plurality of response signals.

Abstract: A test apparatus for testing for short circuits in electrical wiring comprises an emission apparatus and a detection apparatus. The emission apparatus provides a test signal into the electrical wiring, where the test signal is adjustable both for frequency and amplitude. An electromagnetic field is generated in and around the wiring under test. The detection apparatus amplifies strength of magnetic fields found, and detects electromagnetic fields caused by the test signal in a circuit loop. When a signal confirming detection drops suddenly in strength by more than a predetermined threshold, a point or portion of the wiring under the detector is established as a point of short circuit.

Abstract: A method for detecting and determining a position of faults using reflectometry in a wired electrical network including: injecting a test signal e(t) into a cable in the electrical network, a timing of successive injections being controlled by a synchronization module that generates an emission clock signal and a reception clock signal; retrieving a reflected signal on the cable; sampling the reflected signal at a frequency Fe=1/Te, where Te is a sampling period; counting a number of samples obtained for the reflected signal and comparing the number of samples obtained with a number n predefined as a function of a length of the cable or the electrical network to be diagnosed, where n is an integer; repeating the injecting, the sampling, and the counting steps N times, shifting the emission clock signal by a duration ?; reconstituting the reflected signal from n*N samples obtained; and analyzing the reconstituted reflected signal to detect a fault.

Abstract: An arc fault circuit interrupter test circuit is disclosed. The test circuit incorporates a controller along with at least one power transistor, a current sense circuit and a voltage sense circuit. When the power transistor is operated, the current flowing through the transistor is sensed, and if the current is not at least equal to a threshold value, the voltage at which the power transistor is operated is increased.

Abstract: A short circuit detection module for a touch panel includes first and second short circuit detection circuits. The first short circuit detection circuit is coupled to a first conductive line of the touch panel. The first short circuit detection circuit is configured to drive the first conductive line with a first signal having a first logic level. The second short circuit detection circuit is coupled to second, adjacent, conductive line of the touch panel. The second short circuit detection circuit is configured to drive the second conductive line with a second signal having a second logic level that is complementary to the first logic level.

Abstract: A method for determining damaged faulty and/or weak points in a structural seal. The seal is provided with an electrically conductive layer arranged inside or outside the structural seal and extends over substantially the entire surface of the structural seal and to which layer an electrical test voltage is applied. To establish the damaged, faulty and/or weak points, a further electrically conductive layer is used, which is electrically separated from the aforementioned electrically conductive layer by the structural seal and extends over substantially the entire surface of the structural seal. The level of the test voltage between the electrically conductive layers charged with voltage is selected such that when at least one electrically non-conductive damaged, faulty and/or weak point is present in the structural seal, the electrical disruptive strength is exceeded and an electric spark or arc is formed at the location of the damaged, faulty and/or weak point.

Abstract: Provided is a jitter injection apparatus that injects jitter into a signal, comprising: a plurality of jitter injecting sections that are provided in series in a transmission path that propagates the signal; an output section that selects the signal that is passed from a jitter injecting section at a first stage through a designated jitter injecting section, and outputs the selected signal; and a plurality of branch-path jitter injecting sections that (i) are provided in a plurality of branch paths that propagate the signal output by each jitter injecting section from the transmission path to the output section and (ii) are relays having frequency characteristics of attenuating a high-frequency band more than a low-frequency band.

Abstract: Apparatus for detecting faults in the delivery of electrical power to electrical loads, includes a plurality of load electrical connections arranged to deliver electrical power from an electrical power source to each of a plurality of electrical loads, a plurality of electrical switches, each connected to an associated one of the load connections, and a diagnostic device operable to detect a short circuit fault in the apparatus, wherein the diagnostic device is operable to apply a diagnostic procedure to detect a short circuit connection between at least two of the load electrical connections and includes a control logic unit operable to apply to each of the electrical switches in turn a test control signal causing operation of the switch to apply a test electrical signal to each of the load electrical connections in turn; and detector means connected to the load electrical connections and operable, while the test electrical signal is applied in turn to each load electrical connection, to detect whether a cor

Abstract: AC shield continuity for shielded twisted pair structured datacomm cable is determined by testing the cable, driven in a common mode, over a range of frequencies, to determine presence and location of shield breaks. DC ground path generated false results are thereby avoided.

Abstract: The integrated circuit (10) has an internal power supply domain with a power supply voltage adaptation circuit (14) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit (16) in the integrating circuit (10). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.

Abstract: A system for detecting a location of fault in a cable includes a cable transmitting a fault current a current transforming unit connected to the cable and receiving the fault current and detecting an original signal of fault current, a detecting unit detecting a first detail signal and a second detail signal from the original signal of fault current where both signals being detail components in a high frequency band, a comparing unit comparing the first detail signal with a preset reference value and determining a fault in the cable, and a signal filtering unit generating a first filtering signal and a second filtering signal by use of the first detail signal and the second detail signal and outputting a fault detection signal based on a result of comparing the both signals.

Abstract: The present invention is implemented by deploying an enhanced ground fault detection and location apparatus and by using the apparatus in conjunction with specific circuit analysis methods, using the information generated by the ground fault detection and location apparatus. The ground fault detection and location apparatus comprises the functionality of a voltmeter, an ammeter, a phase angle meter, a frequency generator, and a variable power supply, thereby providing for a variety of signals and analyses to be performed on a unintentionally grounded circuit in an ungrounded AC or DC power distribution system. The ground fault detection and location apparatus is capable of operating in six different modes, with each mode providing a different capability or opportunity for detecting, analyzing, and locating one or more unintentionally grounded circuits in an normally ungrounded AC or DC power distribution system.

Abstract: A short circuit detection device is provided to check a circuit layout. The circuit layout includes electronic components connected in parallel. Any of the electronic components includes two contacts on the circuit layout. The short circuit detection device includes a determination circuit configured to determine whether a short circuit has occurred in the circuit layout, and a detection circuit configured to determine the specific electronic component or components responsible for the short circuit. The determination circuit connects with one contact of any of the electronic components. The detection circuit connects with two contacts of any of the electronic components.

Abstract: Embodiments of methods and apparatuses for characterizing an electrical power distribution system are disclosed. One method includes applying, by at least one test/response unit, at least one test signal to at least one test point of the system, measuring, by a plurality of test/response units, a plurality of response signals at a plurality of test points, wherein the plurality of response signals are generated in response to the at least one test signal, and characterizing the system based on the plurality of response signals.

Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.

Abstract: A flat display panel and an active device array substrate and a light-on testing method thereof are provided. The active device array substrate comprises a plurality of first pixel units, a plurality of second pixel units, a first light-on testing circuit, a second light-on testing circuit and a plurality of sets of signal lines. The first light-on testing circuit and the second light-on testing circuit disposed in a peripheral circuit region of the active device array substrate are electrically connected with the first pixel units and the second pixel units disposed in a display region of the active device array substrate respectively. Each two adjacent sets of signal lines disposed in the peripheral circuit region of the active device array substrate are alternatively electrically connected to the first pixel units or the second pixel units respectively.

Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Abstract: A first semiconductor tier has a first tier-to-tier connector for detecting a tier-to-tier coupling in a stacked integrated circuit (IC) device. A second semiconductor tier has a second tier-to-tier connector configured to electrically couple to the first tier-to-tier connector. A tier-to-tier detection circuit electrically couples to the second tier-to-tier connector. The tier-to-tier detection circuit generates an output signal indicative of an electrical coupling between the first semiconductor tier and the second semiconductor tier.

Abstract: A circuit for detecting changes in resistance at a solder joint connecting a constant voltage source supplying a first voltage and a pin of an array package during operation of the array package includes: a test circuit for applying a second voltage different from the first voltage at a side of the solder joint opposite the constant voltage source; and a monitoring circuit for monitoring an output of the test circuit, wherein the test circuit is configured to output the first voltage when the resistance at the solder joint is below a threshold value, and to output a voltage other than the first voltage when the resistance at the solder joint is above the threshold value, and wherein the monitoring circuit is configured to indicate a failure of the solder joint connection when the voltage other than the first voltage is output by the test circuit.

Abstract: Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include basic, ASIC, AC, DC, and RF monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system.

Abstract: An overhead power transmission line system includes detector circuitry to detect a flashover event on a power line conductor in response to test over voltage excitations applied to the power line conductor applied. Processing circuitry establishes an operational voltage level for the power line conductor taking into account the lowest applied test over voltage excitation that causes a flashover event.

Abstract: In accordance with an embodiment, a method of testing a power supply controller includes detecting whether an external switch is coupled between a first supply pin and the second supply pin. If the external switch is detected, the method determines whether there is a short circuit between the second supply pin and the switching output pin. If the short circuit between the second supply pin and the switching output pin is not detected, however, the method determines whether there is a short circuit between a switch control pin and the second supply pin. If the short circuit between the switch control pin and the second supply pin is not detected, the method determines whether there is a conductive path between the first supply pin and the second supply pin when the switch control pin activates the external switch.

Abstract: A test circuit includes a signal level modifying circuit. The signal level modifying circuit modifies at least one of signal levels of an inverting input signal and a noninverting input signal supplied to a differential input circuit in response to a test signal outputted from a signal output circuit to make a difference between signal levels of the inverting input signal and the noninverting input signal smaller than that in a normal operation. Here, the test signal indicates a test mode in which input/output characteristics of the differential input circuit is tested.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test includes a first terminal end and second terminal end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines whether the device under test has passed the test according to the first and second output signals.

Abstract: An electronic trip device is described that includes a test signal generator coupled to at least one of a line conductor and a neutral conductor and configured to create a test signal. The electronic trip device also includes a leakage current detection circuit configured to compare a current in the line conductor and a current in the neutral conductor, the leakage current detection circuit configured to output an error signal if the test signal is not detected.

Abstract: An in situ health monitoring apparatus may include an exciter circuit that applies a pulse to a piezoelectric transducer and a data processing system that determines the piezoelectric transducer's dynamic response to the first pulse. The dynamic response can be used to evaluate the operating range, health, and as-mounted resonance frequency of the transducer, as well as the strength of a coupling between the transducer and a structure and the health of the structure.

Abstract: A method is provided for visual inspection of an array of interferometric modulators in various driven states. This method may include driving multiple columns or rows of interferometric modulators via a single test pad or test lead, such as test pad, and then observing the array for discrepancies between the expected optical output and the actual optical output of the array. This method may particularly include, for example, driving a set of non-adjacent rows or columns to a state different from the intervening rows or columns and then observing the optical output of the array.

Abstract: A signal generator is disclosed that generates a test signal to be applied to a first and second wire of a subscriber line. The signal generator is configured to generate the test signal at the first and second test signal outputs in a first time section such that a first potential at the first test signal output is changed from a first value to a second value and a second potential at the second test signal output is maintained constant at least during the change of the first potential. The signal generator is further configured to generate the test signal during a second time section such that the first potential at the first output and the second potential at the second output are oscillating with a predetermined frequency.

Abstract: A detecting circuit measures at least one response characteristic of an output channel in an electro-acoustic transducer system. A memory stores a plurality of equalizations, each equalization corresponding to a known electro-acoustic transducer system associated with at least one response characteristic stored in the memory. A processor in communication with the detecting circuit and the memory selects one of the stored response characteristics matching the response characteristic measured by the detecting circuit. In some cases, an appropriate equalization is loaded based on the selected response characteristic.

Abstract: A full duplex, high speed test interface comprises a tester side circuit and a device under test side circuit, each comprising balancing circuits. The balancing circuit of the test side circuit is configured to cancel its own transmitted data at the test side circuit such that the transmitted data does not influence any other signal generated at the test side circuit. Similarly, the balancing circuit of the device under test side circuit is configured to cancel its own transmitted data at the device under test side circuit such that the transmitted data does not influence any other signal generated at the device under test side circuit.

Abstract: A one sheet test device and a method of testing using the same that can prevent a change of current characteristics due to a failure panel by measuring a current of normal panels except for the failure panel, when testing a one sheet substrate that includes panels, first wires that are arranged in a first direction between and connected to the panels, second wires that are arranged in a second direction different from the first direction between and connected to the panels. The test device includes voltage application units that are connected to the first and second wires, respectively, to apply a selected one of the first voltage and the second voltage to the corresponding wires; and a test unit that controls the voltage application units to measure an on-current and off-current of each of the panels.

Abstract: Aspects of a method and system for matching an integrated system to an antenna utilizing on-chip measurement of reflected signals are provided. In a chip comprising at least a portion of a receiver and at least a portion of a transmitter, a best impedance match between an antenna and the chip may be determined based on on-chip measurement of one or more signals reflected from the antenna. The best impedance match between the antenna and the chip may be determined utilizing a correction algorithm. The correction algorithm may be determined utilizing data from an external test set that measures signals transmitted by the chip via the antenna. The reflected signals may be routed to a signal analyzer via on on-chip directional coupler. The best impedance match may be determined for each of a plurality of frequencies and/or each of a plurality of transmit signal strengths.

Abstract: A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.

Abstract: One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.

Abstract: A method for testing electronic devices involves receiving a stimulus signal for testing a device; changing an operating temperature of at least a component of an electrical filter while maintaining settings of the electrical filter, thereby altering the stimulus signal as the stimulus signal passes through the electrical filter, to create an altered stimulus signal; and outputting the altered stimulus signal.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.

Abstract: A test structure for testing electrical properties of a material comprises a first loop and a second loop, which are connected to form a closed test loop. A signal generator, for generating a test signal, is coupled to the first loop and the second loop. A signal propagation switching logic is coupled to the first loop and to the second loop for alternatingly flipping the test signal between the first and second loops, such that the test signal moves uninterrupted through the closed test loop. A probe logic detects any degradation of the test signal as the test signal travels along the closed test loop.

Abstract: The present invention relates to electromigration testing and evaluation methods and apparatus for a device under test with an interconnect structure. The method comprises forcing the occurrence of a step resistance-increase of the interconnect structure due to electromigration in the first layer and subsequently subjecting the interconnect structure to at least three respective predetermined stress conditions while concurrently measuring a test quantity indicative of an electrical resistance of the interconnect structure. The method allows performing an electromigration test in much shorter time than known electromigration testing methods, without loss of information or accuracy. It is therefore possible to accelerate the optimization of the interconnect manufacturing process so that the conductor electromigration kinetics remains compatible with a required product lifetime.

Abstract: An inspection method includes an array process of forming a TFT array on a substrate to fabricate an active matrix panel, an inspection process of carrying out a performance test on the fabricated active matrix panel, and a cell process of mounting an OLED on the active matrix panel after the inspection process. In the inspection process, variation in parasitic capacitance through a pixel electrode is measured when driving TFTs constituting the active matrix fabricated in the array process are turned on and when the driving TFTs are turned off, and open/short defects in the driving TFTs are thereby inspected.

Abstract: In some embodiments, a method includes characterizing a plurality of channels, each of the plurality of channels being a channel between a location and a respective one of the plurality of communication interfaces; for each of the plurality of communication interfaces, supplying signals to the communication interface and detecting interference that occurs at the location as a result of emissions radiated from the plurality of communication interface while the signals are supplied thereto; for each of the plurality of communication interfaces, determining an estimate of interference that would occur at the location as a result of emissions radiated from the communication interface while the signals are supplied thereto, based at least in part on the characterization of the channel between the location and the communication interface; and for each of the plurality of communication interfaces, comparing the estimate of interference that would occur at the location to the detected interference that occurs at the

Abstract: A data driver of a display device includes: a DAC (Digital Analog Converter) outputting a drive signal for driving a signal line of a displaying unit; an amplifier amplifying the drive signal outputted by the DAC and outputting the drive signal to the signal line; a repair amplifier having an input and an output, wherein the signal line is separated by a breakage point into a connected data line connected to the amplifier and a disconnected data line not connected to the amplifier, and the input of the repair amplifier is connected to the connected data line and the output of the repair amplifier is connected to the disconnected data line; and a switch supplying the drive signal to the input of the repair amplifier for testing the repair amplifier. An output delay test for the repair amplifier can be performed under a condition similar to that of the amplifier.

Abstract: A circuit testing apparatus for testing capacitance of a capacitor of a device under test is provided. The circuit testing apparatus includes a measuring module, a first converting module, a processing module and a second converting module. The measuring module provides a testing signal, and determines the capacitance of the capacitor according to a signal measuring result of the testing signal. The first converting module is coupled to the measuring module for converting the testing signal to generate a testing input signal. The processing module is coupled to the first converting module and the device under test for transmitting the testing input signal to the capacitor, and amplifies an output signal generated by the capacitor to generate an amplified signal. The second converting module is coupled to the processing module and the measuring module for converting the amplified signal to generate the signal measuring result.

Abstract: An acoustic sensor apparatus includes a housing, a fastener structured to fasten together the housing and an electrical power conductor, an acoustic sensor structured to detect acoustic noise from the electrical power conductor and output a signal, and a circuit structured to detect an electrical conductivity fault from the signal.

Abstract: A method for adapting the signal transmission between two electronic devices (1, 2) that are connected to each other via a physical interface and that each have a transmitter (8a, 8b) and a receiver (7a, 7b), wherein analog signals are transmitted from the transmitter (8a, 8b) of one device (1, 2) along a transmission path (9a, 9b) to the receiver (7a, 7b) of the other device (1, 2). Known scattering parameters (10a, 10b, 10c, 11d) for describing the electromagnetic wave propagation in the transmission path (9a, 9b) between the receiver (7a, 7b) of the first device (1, 2) and the transmitter (8a, 8b) of the second device (1, 2) are retrieved by the first device (1, 2), transmitted to the second device (1, 2), and parameters of the transmitter (8a, 8b) in the second device (1, 2) are adapted with reference to a high-frequency description of the transmission path (9a, 9b) as a function of all of the scattering parameters (10a to 10d, 11a to 11d) known to the two devices.

Abstract: Detecting ingress of a transmitted signal into a cable communication system due to a radio frequency signal transmitted from a moving vehicle and interrogation of transmitter location over a separate wireless link provides monitoring of shielding integrity or flaws there in a cable communication system. The location of a shielding flaw may then be precisely located in a closed loop fashion without risking overload of the cable communication system or interference with upstream signaling therein by detecting ingress signal strength and controlling transmitted signal strength while providing a user-perceptible indication of ingress signal strength which is compensated for the control of transmitted signal strength and thus indicates proximity of a hand-held instrument or transmitter to said shielding flaw.

Abstract: An OLED display and a driving method of an inspection circuit are provided. The OLED display may include a data driver, a scan driver, a driving transistor, a switching transistor, an organic light emitting diode, and an inspection circuit. The data driver and scan driver may apply a data signal and a scan signal. The driving transistor may generate a current corresponding to a voltage supplied to a first electrode and a control electrode. The switching transistor may apply the data signal to the driving transistor. The organic light emitting diode may be electrically connected to the driving transistor. The inspection circuit may include a three-phase inverter circuit having an input and an output terminal. The input terminal may supply a first power voltage to the output terminal when the output terminal decides an output signal regardless of a signal input to the input terminal.

Abstract: A fault determination apparatus includes a housing. The housing includes a circuit board disposed there within. The housing is shaped and dimensioned for non-intrusive placement within an existing electrical system. The circuit board is configured to provide one of a transmitter or a receiver within a fault determination system. A first set of connectors is disposed at a first side of the housing and a second set of connectors disposed at the second end of the housing. The first set of connectors and the second set of connectors are directly connected through the wires provided inside the apparatus while at least one wires under fault monitoring are tapped to the circuit board and configured so as to be electrically coupled to the existing electrical system.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.