Abstract: A voltage source device, including a first voltage source configured to output a first voltage, source pathways to connect the first voltage source to a device under test, sensing pathways electrically coupled to the device under test; and circuitry configured to sample a second voltage at the device under test, determine a voltage difference between the first voltage and the second voltage, and adjust the first voltage based on the difference between the first voltage and the second voltage.

Abstract: A solar power generating system includes a solar power generating device (10), a microbubble cleaning device (20) mounted on the solar power generating device, a temperature adjustment device (30) mounted on the solar power generating device, and a controller (40) electrically connected with the solar power generating device, the microbubble cleaning device, and the temperature adjustment device. The microbubble cleaning device produces a liquid containing microbubbles and is controlled by the controller to inject the liquid outward to clean a surface of the solar power generating device. The temperature adjustment device is used to regulate an ambient temperature of the solar power generating device. The controller receives data of power generation from the solar power generating device, and controls on/off operation of the microbubble cleaning device and the temperature adjustment device.

Abstract: A diagnostic disc includes a disc-shaped body having raised walls that encircle the interior of the disc-shaped body and at least one protrusion extending outwardly from the disc-shaped body. The raised walls of the disc-shaped body define a cavity of the disc-shaped body. A non-contact sensor is attached to each of the at least one protrusion. A a printed circuit board (PCB) is positioned within the cavity formed on the disc-shaped body. A vacuum and high temperature tolerant power source is disposed on the PCB along with a wireless charger and circuitry that is coupled to each non-contact sensor and includes at least a wireless communication circuit and a memory. A cover is positioned over the cavity of the disc-shaped body and shields at least a portion of the PCB, circuitry, power source, and wireless charger within the cavity from an external environment.

Abstract: A connecting device for inspection includes a probe head configured to hold electric contacts and optical contacts such that tip ends of the respective contacts are exposed on a lower surface of the probe head, and a transformer including connecting wires arranged therein and optical wires penetrating therethrough. The respective proximal ends of the electric contacts and the optical contacts are exposed on an upper surface of the probe head, and tip ends on one side of the connecting wires electrically connected to the proximal ends of the electric contacts and connecting ends of the optical wires optically connected to the proximal ends of the optical contacts are arranged in a lower surface of the transformer.

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

Abstract: A probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe. The tester is configured to move around the wafer along a circumferential direction. The probe apparatus also includes a processing unit in communication with the tester and configured to control a movement of the tester.

Abstract: A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.

Abstract: An electronic component handling apparatus handles a DUT and includes: an acquiring device that acquires current three-dimensional shape data of a DUT container having a plurality of accommodating portions each capable of accommodating the DUT; and a computer device that: calculates a first correction amount from the current three-dimensional shape data and corrects the current three-dimensional shape data based on the first correction amount; extracts, from the corrected three-dimensional shape data, at least one of a height and a slope of each of predetermined regions of the DUT container; and determines an accommodation state of the DUT based on an extraction result. The first correction amount represents at least one of a movement amount and a rotation amount in a planar direction of the current three-dimensional shape data with respect to an initial state of the DUT container set in advance.

Abstract: A chip test device and a chip test method are provided. The chip test device may include a chip socket and an interface card comprising a signal synthesizer, a plurality of first interfaces and a second interface. The signal synthesizer may be configured to synthesize a plurality of low-frequency first signals output from a plurality of testers into a high-frequency second signal and transmit the second signal to the chip socket. The plurality of first interfaces may be arranged in a plurality of inputs of the signal synthesizer for connecting the testers, and the second interface may be arranged in an output of the signal synthesizer for connecting the chip socket. By synthesizing the low-frequency first signals into the high-frequency second signal, a high-frequency test may be conducted using a plurality of low-frequency testers.

Abstract: The present disclosure provides an antenna packaging structure and a method for forming the same. The structure includes: a supporting substrate, a rewiring layer on the supporting substrate, a first antenna layer disposed on the rewiring layer, first metal feedline pillars disposed on the first antenna layer, a first packaging layer covering the first metal feedline pillars except exposing the top surfaces of the first metal feedline pillars; a second antenna layer on the first packaging layer, second metal feedline pillars, a second packaging layer covering the second metal feedline pillars except exposing the top surfaces of the second metal feedline pillars; a third antenna layer disposed on the second packaging layer, semiconductor chips connected to the rewiring layer, a metal bump disposed inside an opening in the rewiring layer, and a third packaging layer encapsulating the semiconductor chips and the metal bump.

Abstract: Probe systems and methods of characterizing optical coupling between an optical probe of a probe system and a calibration structure. The probe systems include a probe assembly that includes an optical probe, a support surface configured to support a substrate, and a signal generation and analysis assembly configured to generate an optical signal and to provide the optical signal to the optical device via the optical probe. The probe systems also include an electrically actuated positioning assembly, a calibration structure configured to receive the optical signal, and an optical detector configured to detect a signal intensity of the optical signal. The probe systems further include a controller programmed to control the probe system to generate a representation of signal intensity as a function of the relative orientation between the optical probe and the calibration structure. The methods include methods of operating the probe systems.

Abstract: One embodiment provides an electronic control unit (ECU) for a vehicle. The ECU includes transceiver circuitry, voltage measurement circuitry and feature set circuitry. The transceiver circuitry is to at least one of send and/or receive a message. The voltage measurement circuitry is to determine at least one of a high bus line voltage (VCANH) value and/or a low bus line voltage (VCANL) value, for each zero bit of at least one zero bit of a received message. The received the message includes a plurality of bits. The feature set circuitry is to determine a value of at least one feature of a feature set based, at least in part, on at least one of a high acknowledge (ACK) threshold voltage (VthH) and/or a low ACK threshold voltage (VthL). The feature set includes at least one of an operating most frequently measured VCANH value (VfreqH2) of a number of VCANH values and/or an operating most frequently measured VCANL value (VfreqL2) of a number of VCANL values.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: A spectrum analyzer for measuring an electrical response of a device under test (DUT) includes a test port for receiving radio frequency (RF) signals from the DUT in response to a test signal transmitted to the DUT, a local oscillator (LO) for generating a LO signal, a sampler connected with the LO to receive the LO signal and a receiver connected with the sampler. The sampler includes a non-linear transmission line that generates a sampler signal having a frequency that is a multiple of a frequency of the LO signal, and an input for receiving a RF signal from the test port. When a RF signal from an RF input source is received the sampler outputs an intermediate frequency (IF) signal. The receiver receives the IF signal output of the sampler.

Abstract: A case module of a radiofrequency testing apparatus has a cable hole and a front entrance, and includes two electromagnetic shielding units respectively covering the cable hole and the front entrance. Each electromagnetic shielding unit includes a stepped structure, a cover detachably fastened to the stepped structure, a shielding structure sandwiched between the stepped structure and the cover. The stepped structures of the two electromagnetic shielding units are respectively arranged around the cable hole and the front entrance. Each of the stepped structure and the cover includes a plurality of treads and a plurality of risers staggeredly arranged with the treads, and the treads and the risers of the stepped structure respectively face those of the cover. Any two faced treads are configured to sandwich a part of the shielding structure, and any two faced risers are configured to sandwich the other part of the shielding structure.

Abstract: A measuring system for over the air measurements on a device under test comprises an antenna module with at least one measuring antenna, a positioner, adapted to change a relative position of the device under test and the antenna module, resulting in a relative path of movement of the antenna module with regard to the device under test. Each measuring antenna comprises an integrated power detector diode. Each measuring antenna is adapted to determine at least two power values during the movement along the path of movement.

Abstract: A method of determining a minimum permissible tip diameter of probing needles of a probe card for wafer probing is described. The method includes performing a plurality of contact procedures of at least one probing needle to a plurality of bonding pads on a wafer. The plurality of contact procedures is performed at different stress applied by the at least one probing needle to the bonding pads. A chart of indentation depths of the plurality of bonding pads caused by the contact procedures at different stress is determined. A set of calibration coefficients based on the chart is determined, wherein the set of calibration coefficients allows to compute a predicted indentation depth as a function of stress. The minimum permissible probing needle tip diameter is determined based on an evaluation of the function.

Abstract: When determining whether an insertion component provided with a positioning-use protruding section and a surface-mounting-use electrode section can be mounted onto a circuit board provided with a positioning hole into which the positioning-use protruding section is inserted and a land for connecting the surface-mounting-use electrode section, an image is captured of the positioning-use protruding sections and the surface-mounting-use electrode sections of the insertion component either separately or simultaneously by a component imaging camera, and the positions of the positioning-use protruding sections and the positions of the surface-mounting-use electrode sections are recognized by processing the captured image.

Abstract: A die-die inspection image can be aligned using a method or system configured to receive a reference image and a test image, determine a global offset and rotation angle from local sections on the reference image and test image, and perform a rough alignment de-skew of the test image prior to performing a fine alignment.

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Abstract: According to one embodiment, a testing device includes a signal generator that generates a first signal output to a device under test, a channel selector provided after the signal generator and configured to select one of a plurality of channels, a signal receiver that receives the second signal supplied from the device under test, a correction value calculator that calculates a correction value for calibrating loss of a respective one of the channels, wherein the correction value calculator calculates a correction value for calibrating loss of a respective one of the channels included in the channel selector, based on a signal level received by the signal receiver via a loopback channel, when a calibration-level output state indicating a state where a signal level of the first signal generated by the signal generator reaches a predetermined transmission reference level of calibration is assumed.

Abstract: A method for compensating probe misplacement and a probe apparatus are provided. The method is applicable to a probe module which includes a probe and a fixing base. The probe includes a probe body section and a probe tip section. The probe body section is fixed on the fixing base. The method includes: measuring a temperature of a probe body of the probe body section of the probe; calculating, according to the temperature of the probe body, thermal expansion amount of the probe along a length direction of the probe body section; calculating a compensation value according to the thermal expansion amount; moving the probe or a to-be-tested element according to the calculated compensation value, to align a probe tip of the probe tip section with the to-be-tested element or align the to-be-tested element with the probe tip of the probe tip section.

Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.

Abstract: A dual-band dual-port antenna structure is provided. The dual-band dual-port antenna structure includes a first antenna structure and a second antenna structure. The first antenna structure operates in a high-frequency band and includes a first feeding port, a first feeding path electrically connected to the first feeding port, and a first radiating element. The second antenna structure operates in a low-frequency band and includes a second feeding port, a second feeding path electrically connected to the second feeding port, and a second radiating element. The first feeding path includes a first capacitor and a first feeding line. The second radiating element of the second antenna structure at least partially surrounds the first radiating element of the first antenna structure.

Abstract: A packing foam positioning jig for assembling a piece of packing foam to a workpiece includes a suction tube. The suction tube includes a rod body and a positioning seat. The rod body is coupled to the positioning seat. The rod body defines a suction channel. The positioning seat defines at least one suction hole. The at least one suction hole communicates with the suction channel. The positioning seat includes at least one positioning post protruded from an outer surface of the positioning seat. The piece of packing foam is sleeved on the at least one positioning post. The at least one suction hole suctions the piece of packing foam. The at least one positioning post and the at least one suction hole cooperate to assemble the piece of packing foam to the workpiece.

Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.

Abstract: A data receiver includes a vibration sensor to sample data from vibrations in an incoming signal at a predetermined sampling rate, and a microcontroller, coupled to the vibration sensor, to control the sampling rate through an inter-integrated circuit (I2C) protocol or the like. A memory card, coupled to the microcontroller, stores the data with a serial peripheral interface (SPI) protocol or the like.

Abstract: A three-dimensional object printer generates image data of an object being formed in the printer with an optical sensor and identifies the heights of object features above a substrate on which the object is being formed. A controller operates one or more actuators to move the optical sensor at a plurality of distances above the object to generate image data of the object at a plurality of heights above the object. The controller identifies the distances of the features of the object with reference to the image data generated by the optical sensor and the focal length of the optical sensor.

Abstract: A method of probe testing dies, the method includes loading a wafer having a first die and a second die into a prober and bringing probes of the prober into contact with first contact pads of the first die according to first probe parameters. A first probe contact test of first values of the contact between the probes and the first contact pads is performed, and a die test of the first die is performed after performing the probe contact test. Results of the die test and results of the probe contact test are saved and second probe parameters are automatically generated based on at least the results of the first probe contact test.

Abstract: A calibration apparatus, for calibration of a measurement device, is provided. The calibration apparatus includes a calibration device configured to calibrate the measurement device. The calibration device also includes a verificationH device configured to verify the calibration of the measurement device. The calibration device also includes a switch configured to switch between a connection of the measurement device to the calibration device and a connection of the measurement device to the verification device.

Abstract: A calibration module with a substrate provides at least one high-frequency terminal integrated on the substrate which can be connected in each case with an allocated switching element integrated on the substrate to one of several allocated calibration standards or to an allocated power detector. The calibration standards and the power detector are integrated on the substrate.

Abstract: In accordance with one embodiment, a method for testing a plurality of electronic components is provided, including subdividing the plurality of electronic components into a plurality of first groups and subdividing the plurality of electronic components into a plurality of second groups. The method may further include measuring, for each first group, an electrical parameter of an interconnection of the components of the first group; measuring, for each second group, an electrical parameter of an interconnection of the components of the second group, and determining which electronic components of the plurality of electronic components have a predefined property, on the basis of the result of the measurement of the electrical parameter for the first groups and on the basis of the result of the measurement of the electrical parameter for the second groups.

Abstract: Aspects of the disclosure are directed to interference cancellation. A method for performing interference cancellation in a wireless communications device having a transmitter, a receiver, a coefficient controller, an analog interference cancellation (AIC) circuit and a receive local oscillator (LO) includes utilizing a receive local oscillator (LO) to generate a transmit pilot; injecting the transmit pilot into a transmit chain for transmission; utilizing a receiver to receive a signal, wherein the signal includes the transmit pilot and an interference signal; and determining a set of coefficients for the interference cancellation based on an output signal from the receiver.

Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Abstract: A test system for a semiconductor apparatus that includes a calibration board having first skew information therein and outputting a plurality of test signals, and a main board configured to perform first skew correction for correcting skews of the test signals based on the first skew information and perform secondary skew correction for correcting an I/O skew thereof using the plurality of test signals.

Abstract: A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.

Abstract: A system and method for performing radiation source analysis on a device under test (DUT) uses discrete Fourier transform on measured field components values at different sampling locations away from the DUT to derive field component values at locations on the DUT. The results of the discrete Fourier transform are multiplied by a complex phase adjustment term as a function of distance from the sampling locations to the DUT to translate the measured field component values back to the locations on the surface of the DUT.

Abstract: A method (100) for decreasing an excess carrier induced degradation in a silicon substrate, includes providing (120, 130) a charged insulation layer capable of retaining charge on the silicon substrate for generating a potential difference between the charged insulation layer and the silicon substrate, and heat treating (140) the silicon substrate for enabling an impurity causing the excess carrier induced degradation and being in the silicon substrate to diffuse due to the potential difference into a boundary of the silicon substrate and the insulation layer.

Abstract: A method that acquires data on a processing module of a substrate processing apparatus using a sensor substrate efficiently and highly precisely is provided. The method includes: holding a sensor substrate by a first holding member, the sensor substrate having a sensor section for acquiring data on the processing modules and a first power supply section with a rechargeable electricity storage section for supplying electric power to the sensor section; advancing the first holding member to transfer the sensor substrate to a processing module; acquiring data on the processing module by the sensor section of the sensor substrate; and causing the first holding member to receive the sensor substrate, whose electric charge is consumed, from the processing module and retract, and with that state, charging the first power supply section of the sensor substrate in a non-contact manner by a second power supply section that moves together with the base.

Abstract: Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.

Abstract: Manufacturing management information relating to a module battery and single battery mounted therein which are obtained in a battery manufacturing process (1) is collected by a manufacturing quality information collection processing unit (4) and stored in a database (6). In a battery diagnosis system (3), when the module battery (2) under a usage environment is charged, an operation result processing unit (5) collects operation result information relating to the module (2) and stores the operation result information in a database (7). An operation result monitoring processing unit (8) determines whether the operation result information is abnormal, and supplies the result of the determination to a manufacturing/usage environment factor classification processing unit (9).

Abstract: A calibration module for a tester, for testing a device under test, includes a pair of RF-channel terminals, a calibration device, a pair of measurement terminals and a mode selector. The pair of RF-channel terminals is configured to send or receive measurement signals to or from an RF-channel of the tester. The calibration device is configured to perform a calibration of the RF-channel based on the measurement signals sent to, or received from, the RF-channel. The pair of measurement terminals is configured to send or receive measurement signals to or from the device under test. The mode selector is configured to connect, in a calibration phase, the pair or RF-channel terminals to the calibration device for calibrating the RF-channel and to connect, in a measurement phase, the pair of RF-channel terminals to the pair of measurement terminals for routing measurement signals from the RF-channel to the device under test or vice versa.

Abstract: A radiator module system for automatic test equipment, wherein the automatic test equipment comprises at least one test arm, with the front end of the test arm being configured with a test head, and a closed-loop circulating cooling device is installed on the test arm. The closed-loop circulating cooling device includes a conduit which is in contact with the cooling device, internally contains an working fluid and is connected to the test head, a cooling device, a set of fans and a driving source for driving the working fluid. The closed-loop circulating cooling device can operate to circulate and exchange heat energy generated by a device under test (DUT) tightly stressed by downward pressure applied with the test arm, and brings up airflows by means of the fans to perform heat exchange on the cooling device thereby dissipating the generated heat energy.

Abstract: A refresh circuit includes a period signal generation circuit configured to drive a control node according to a level of the control node, discharge first and second currents from the control node in response to the first temperature signal, and generate a period signal, a division signal generator configured to divide the period signal to generate a first division signal and a second division signal, and a selector configured to select one of the first and second division signals in response to a second temperature signal and for outputting the selected division signal as a refresh signal.

Abstract: Implementations are presented herein that include a plurality of on-chip monitor circuits and a controller. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The controller is coupled to the plurality of on-chip monitor circuits. The controller is configured to receive a measurement result from at least one of the plurality of on-chip monitor circuits and to control a calibration of another one of the plurality of on-chip monitor circuits in accordance with the measurement result.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Abstract: In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

Abstract: Disclosed herein is an electronic switch that comprises a pressure sensitive bridge array adapted to monitor pressure and activate an indicator when the monitored pressure exceeds a predetermined value indicative of a dangerous condition. The electronic switch further comprises a monitoring circuit adapted to test the overall operability of the pressure sensitive bridge array and its accompanying electronics control circuitry.

Abstract: Systems, apparatus, and methods detect a current sensor error in an FOC electric machine system. A voltage command is monitored to detect the presence of an ac component can indicate that an error has occurred at a current sensor. By way of example, a sensor fault detection module can be configured to determine the deviation between an actual voltage command and an ideal voltage command to provide a complex deviation vector. By transforming the deviation vector to a reference frame rotating at the fundamental frequency of the command voltage, a dc component of the positive and negative sequences can be filtered, and their amplitudes determined. Error detection can be based on the total amplitude of the fundamental component, determined by positive and negative component amplitudes. The invention enables an FOC system to operate with two current sensors, rather than three, and provides a dedicated fault diagnostic for a current sensor.