Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

Abstract: In an electronic device and a method of correcting time-domain reflectometers, two channels of a time-domain reflectometer are connected to a corrector using cables, and the two channels are enabled to transmit pulses. Parameters Step Deskew and Channel Deskew of the two channels are zeroed. Resistance values of the two channels are measured simultaneously, and the value of the parameter Step Deskew of one of the two channels is adjusted according to the Resistance values of the two channels. Times of achieving the same resistance value of the two channels are measured after the cables and the connector have been disconnected, and the value of the parameter Channel Deskew of one of the two channels is adjusted according to the times of achieving the same resistance value. The adjusted values of the parameters Step Deskew and Channel Deskew are displayed through a display unit.

Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Abstract: A method for the error correction of a vectorial network analyzer, where a primary system calibration is initially implemented using a calibration kit. Following this, a first, secondary error correction is implemented on at least two one-port networks of the vectorial network analyzer. After this first, secondary error correction of the one-port networks of the vectorial network analyzer, a second, secondary error correction is implemented, where either two one-port networks are through-connected in an ideal manner or a measurement is implemented on a reciprocal two-port network. The corrected system-error values from the first, secondary error correction are used even in this further measurement, and overall, a high-precision, calibrated multi-port network analyzer is obtained.

Abstract: A test station for wireless devices and methods for calibration thereof. The test station includes a signal generator, a calibrator, a scanner having receiving and transmitting antennas, a signal analyzer, and a computer. Under the direction of the computer, the signal generator generates a calibration signal in accordance with a programmable calibration signal script. The calibrator may be used to emulate either a wireless device in transmit mode by transmitting the calibration signal to the scanner for analysis by the signal analyzer, or a wireless device in receive mode by receiving the calibration signal from the scanner for analysis by the signal analyzer. The behavior of the test station is calibrated by correlating signal parameters of the calibration signal as specified by the calibration signal script and as measured at the signal analyzer.

Abstract: A failure detecting method for a solar power generation system having plural solar cell strings in each of which plural solar cell modules are connected to each other in series. Specifically, by comparing the current value of each of the solar cell modules or strings with the average current value per one module or string, calculated from the total current value of the entire solar cell modules or strings, one or more failure candidates can be detected with high precision.

Abstract: A current calibration method and the associated control circuit are provided. The method includes: providing a predetermined voltage to the differential output for obtaining an accurate current passing through the panel resistor during a calibration procedure and, providing a driving current to the differential output according to the accurate current during a normal operation procedure.

Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a shunt pole-zero pair coupled to the input circuitry providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

Abstract: A wafer probing method includes calibrating a wafer probing system, checking continuity between probe pins of the wafer probing system and respective conductors of a wafer under test, and identifying at least an interconnect structure in the wafer under test to determine whether a fault exists.

Abstract: Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner.

Abstract: Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

Abstract: The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters.

Abstract: A first output pin of a microcontroller is connected to a control pin of a high speed switch chip. A second output pin of the microcontroller is connected to two control pins of first and second switch chips. Two output pins of the high speed switch chip are connected to two input pins of the first switch chip. Two input pins of a third switch chip are connected to two output pins of the second switch chip. Two control pins of the third switch chip are connected to a third output pin of the microcontroller. Three input pins of a bus switch chip are connected to fourth to sixth output pins of the microcontroller. A load board is connected to six output pins of the bus switch chip and four switch pins of the first and second switch chips.

Abstract: A system and method for measuring near field information of a device under test (DUT) uses a reference probe and a measurement probe that are configured to sense a field. A probe calibration factor is used to determine corresponding field values for signals from the measurement probe at sampling locations about the DUT. The probe calibration factor is derived from measured signals about a conductive trace using a probe and simulated field information for the conductive trace when subjected to a simulated reference signal.

Abstract: A testing system for a PSU includes a test chamber and a control device. The test chamber includes a first partition with the PSU accommodated therein and a second partition with an electric load accommodated therein. The PSU is electrically connected to the electric load. The control device includes a microcontroller unit (MCU). The MCU is connected to a setting circuit and a temperature sensing circuit. The setting circuit is configured to set one of predetermined parameters. The temperature sensing circuit is capable of sensing temperature in the test chamber. The MCU is capable of automatically controlling a predetermined temperature in the test chamber and presetting a test time for testing the PSU.

Abstract: The invention relates to a device for checking the operability of a sensor element (100) for determining the concentration of gas components in a gas mixture, particularly of the concentration of gas components in the exhaust gas of internal combustion engine, having an external pump electrode (APE) and an internal pump and Nernst electrode (IPE), a measurement resistor (Rm) and a balancing resistor (Rtrim) connected parallel thereto being provided upstream of the external pump electrode (APE), and a pump current (Ip) being impressible into the external pump electrode by means of a pump current source, and a measuring voltage (Um) incident across the measuring resistor (Rm) via a measuring and analysis device (200) being detectable, characterized in that an activatable switch means (S) is disposed in series to the measuring resistor (Rm), which can be switched at a high impedance for a predetermined amount of time, during which the voltage across the measuring resistor is detected and analyzed in the measurin

Abstract: Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point.

Abstract: An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.

Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a compensation digital filter providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

Abstract: A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.

Abstract: Embodiments of the present invention relate to methods and systems of transmitting data signals from at least one transmitting terminal with a spatial diversity capability to at least two receiving user terminals, each provided with spatial diversity receiving device. The methods and systems are useful, for example, in communication between terminals, e.g., wireless communication. In certain embodiments, transmission can be between a base station and two or more user terminals, wherein the base station and user terminals are each equipped with more than one antenna.

Abstract: Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.

Abstract: By examining scrub mark properties (such as position and size) directly, the performance of a wafer probing process may be evaluated. Scrub mark images are captured, image data measured, and detailed information about the process is extracted through analysis. The information may then be used to troubleshoot, improve, and monitor the probing process.

Abstract: A probe apparatus includes a movable mounting table for supporting an object to be tested; a probe card disposed above the mounting table and having a plurality of probes to come into contact with electrodes of the object; a support body for supporting the probe card; and a control unit for controlling the mounting table. Electrical characteristics of the object are tested based on a signal from a tester by bringing the object and the probes into electrical contact with each other by overdriving the mounting table in a state where a test head is electrically connected with the probe card by a predetermined load. Further, one or more distance measuring devices for measuring a current overdriving amount of the mounting table are provided at one or more locations of the test head or the probe card.

Abstract: An evaluation method and apparatus is provided for evaluating a displacement between patterns of a pattern image by using design data representative of a plurality of patterns superimposed ideally. A first distance is measured for an upper layer pattern between a line segment of the design data and an edge of the charged particle radiation image, a second distance is measured for a lower layer pattern between a line segment of the design data and an edge of the charged particle radiation image; and an superimposition displacement is detected between the upper layer pattern and lower layer pattern in accordance with the first distance and second distance.

Abstract: A system and method are provided for correction of parameters used in determination of stator turn faults of an induction motor. An embodiment may include determining a residual impedance and/or a residual voltage of the motor, and correcting a normalized cross-coupled impedance based on the residual impedance and residual voltage. Additional embodiments may include measuring an operating temperature of the motor and determining a negative sequence impedance of the motor based on the temperature. Another embodiment may include measuring voltages and currents of the motor and determining phasors for the voltages and currents using compensation for variations from a nominal frequency of the motor.

Abstract: Implementations are presented herein that include a test circuit and a reference circuit.

Abstract: A test apparatus that tests a device under test, comprising first and second terminal groups including a plurality of drivers that output signals to the device under test; a first common setting section that sets a common delay amount for the signals output from one driver in the first terminal group and one driver in the second terminal group; and an inter-group adjusting section that causes reference phases of the signals output from the drivers in the first terminal group and reference phases of the signals output from the drivers in the second terminal group to draw near each other, based on a delay amount setting value set by the first common setting section when the reference phases in the first terminal group were adjusted and a delay amount setting value set by the first common setting section when the reference phases in the second terminal group were adjusted.

Abstract: Techniques for self-calibration of transceivers are described herein.

Abstract: A target position detection apparatus for a robot includes: a robot including an arm configured to be freely moved in at least two directions of X and Y axes, the arm having a wrist axis provided at a distal end of the arm and configured to be freely moved in a horizontal direction, and the wrist axis being provided with an end effector; and a control unit adapted for driving a memory to store a teaching point therein and controlling an operation of the robot such that the end effector will be moved toward the teaching point stored in the memory.

Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: A process monitor measures the absolute value of unit sample resistors and transistors on a common Integrated Circuit (IC) substrate. This information can be used to adjust the gain of an amplifier assembly to a desired value, or to determine the true, corrected gain of such the amplifier assembly. Also, process information about process variations corresponding to the common IC substrate can be collected from the process monitor. Gain correction factors are derived and applied to the amplifier assembly to compensate for the process variations using the gain value and the process information.

Abstract: An apparatus and method for preventing access to calibration controls includes a primary cover including a connection device, an access opening and a first through hole. The primary cover is configured to exclude access to an underlying area. The access opening is located on the primary cover to permit access to the underlying area when securing the primary cover. A shield is configured to fit over the primary cover and prevent access to the access opening. The shield includes a latch portion configured to latch on a first end portion of the primary cover and a second through hole located at a second end portion and corresponding to the first through hole of the primary cover. A security mechanism is configured to be received in the first and second through holes such that the security mechanism shows signs of tampering when unauthorized access to the underlying area is attempted.

Abstract: A chuck for supporting and retaining a test substrate includes a device for supporting and retaining a calibration substrate. The chuck comprises a first support surface for supporting a test substrate and a second support surface, which is laterally offset to the first support surface, for supporting a calibration substrate. The calibration substrate has planar calibration standards for calibration of a measuring unit of a prober, and dielectric material or air situated below the calibration substrate at least in the area of the calibration standard. In order to be able to take the actual thermal conditions on the test substrate and in particular also on known and unknown calibration standards and thus the thermal influence on the electrical behavior of the calibration standard used into consideration, the second support surface is equipped for temperature control of the calibration substrate.

Abstract: The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected.

Abstract: Methods and systems for calibrating a temperature control system in a vapor deposition chamber. A temperature sensor senses temperature within a semiconductor processing chamber and generates an output signal. A temperature control system controls a chamber temperature by controlling a heating apparatus based on the output signal. A method includes instructing the control system to target a setpoint temperature, and depositing a layer of material onto a surface in the chamber by a vapor deposition process. A variation of a property of the layer is measured while depositing the layer, the property known to vary cyclically as a thickness of the layer increases. The measured property is allowed to vary cyclically for one or more cycles. If there is a difference between a time period of one or more of the cycles and an expected time period associated with the setpoint temperature, the temperature control system is adjusted based on the difference.

Abstract: Determination of non-linearity of a positioning scanner of a measurement tool is disclosed. In one embodiment, a method may include providing a probe of a measurement tool coupled to a positioning scanner; scanning a surface of a first sample with the surface at a first angle relative to the probe to attain a first profile; scanning the surface of the first sample with the surface at a second angle relative to the probe that is different than the first angle to attain a second profile; repeating the scannings to attain a plurality of first profiles and a plurality of second profiles; and determining a non-linearity of the positioning scanner using the different scanning angles to cancel out measurements corresponding to imperfections due to the surface of the sample. The non-linearity may be used to calibrate the positioning scanner.

Abstract: An accelerometer with improved immunity to sensitivity drift is disclosed. In some embodiments, the accelerometer comprises an actuator that induces a known acceleration on a reference frame. A signal based on this known acceleration is used to calibrate the accelerometer to mitigate the effects due to at least one of sensitivity drift, D.C. bias drift, sense laser wavelength drift, and resonant frequency drift.

Abstract: A system includes at least one of a first generator, at least two of a second generator, and a load board. The at least one of a first generator one of receives and transmits analog signals. The at least two of a second generator one of receives and transmits digital signals. The load board is disposed between the first generator and the second generators and electrically coupled therebetween to calibrate parameters relating to communications. The load board includes a direct path for each of the analog signals between the at least one of the first generator and a corresponding number of devices under test and for each of the digital signals between the at least two of the second generator and a corresponding number of devices under test.

Abstract: An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.

Abstract: Methods and apparatus for calibrating a vector network analyzer (VNA) and characterizing a device under test. In one example, a device fixture including a pair of embedded device adapters provides an interface between a device under test (DUT) with non-coaxial connectors and the coaxial connectors of the VNA, and moves the calibration reference plane from the coaxial connectors of the VNA to a DUT reference plane at the leads/connectors of the DUT. A through fixture having a pair of similar through adapters is used to establish the DUT reference plane and to facilitate characterizing the device adapters such that they can be de-embedded from measurements of the device fixture.

Abstract: A chuck for supporting and retaining a test substrate includes a device for supporting and retaining a calibration substrate. The chuck comprises a first support surface for supporting a test substrate and a second support surface, which is laterally offset to the first support surface, for supporting a calibration substrate The calibration substrate has planar calibration standards for calibration of a measuring unit of a prober, and dielectric material or air situated below the calibration substrate at least in the area of the calibration standard. In order to be able to take the actual thermal conditions on the test substrate and in particular also on known and unknown calibration standards and thus the thermal influence on the electrical behavior of the calibration standard used into consideration, the second support surface is equipped for temperature control of the calibration substrate.

Abstract: A calibration substrate includes a plurality of input terminals, a detector coupled to the input terminals, and an output terminal. The calibration substrate can be used for calibrating and/or deskewing communications channels.

Abstract: A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern.

Abstract: A method is disclosed for calibrating a capacitance of an apparatus for measuring dielectric properties of a part. The apparatus includes an electrically grounded chamber, a lower electrode disposed within the chamber and connected to a radiofrequency (RF) transmission rod, an electrically grounded upper electrode disposed within the chamber above the lower electrode, and a variable capacitor connected to control transmission of RF power through the RF transmission rod to the lower electrode. A method is also disclosed for determining a capacitance of a part through use of the apparatus. A method is also disclosed for determining a dielectric constant of a part through use of the apparatus. A method is also disclosed for determining a loss tangent of a part through use of the apparatus.

Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Abstract: The present invention provides an apparatus for easily detecting an abnormal status of power generation of a solar cell panel in a solar cell power generation system having the power generation of 1 MW or higher. The present invention provides an abnormality detecting apparatus for a solar cell power generation system including a plurality of solar cell strings each having a plurality of solar cell modules connected to each other in series and a backflow preventing diode connected to a power output terminal of each of the solar cell strings, characterized in that the abnormality detecting apparatus further includes measuring means for measuring a current flowing in the backflow preventing diode; and that the measuring means is supplied with electric power from both terminals of the backflow preventing diode.

Abstract: An endurance testing system is configured to test endurance of a first detecting apparatus. The endurance testing system includes a second detecting apparatus, a movement module, a processor, and a storage module. The movement module includes a first inductive object and a second inductive object. The processor is connected to the first and second detecting apparatuses, and the movement module, for controlling the movement module and counting a first number of times the first detecting apparatus detects the first inductive object, and a second number of times the second detecting apparatus detects the second inductive object. The storage module is connected to the processor, for storing the first and second numbers of times from the processor. The first detecting apparatus fails the testing upon the condition that the first number of times is not equal to the second number of times.