Abstract: The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation.

Abstract: A first resistance element (R1) and a second resistance element (R2) are added to a pixel circuit (1) in which an organic EL element (E1) is lighted and driven by a control TFT (T1) and a drive TFT (T2). That is, an anode power supply wiring (a1) and a scanning wiring (s1) are connected through the first resistance element (R1), and a cathode power supply wiring (k1) and a data wiring (d1) are connected through the second resistance element (R2). A test anode voltage (VH1) and a test cathode voltage (VL1) are applied respectively to the anode power supply wiring and the cathode power supply wiring, whereby pixels are lighted and driven. Consequently, whether or not the pixel circuit (1) is normally operated can be verified.

Abstract: A regulated circuit having a number of metal-oxide-semiconductor field effect transistors (MOS FETs) and a method for using the same are provided to reduce Negative Bias Temperature Instability degradation of the MOS FETs on the circuit. In one embodiment, the method involves steps of: (i) detecting degradation in performance of at least one of the MOS FETs causing a shift in threshold voltage (VT) of the MOS FET; and (ii) if the shift in VT exceeds a predetermined value, forward biasing the MOS FETs, thereby reducing or reversing the shift in VT. Optionally, the method includes an initial step of determining if the circuit is in a non-dynamic operating mode before forward biasing the MOS FETs. Other embodiments are also disclosed.

Abstract: To provide a simple method for evaluating reliability of a transistor, a simple test which correlates with a bias-temperature stress test (BT test) is performed instead of the BT test. Specifically, a gate current value is measured in the state where a voltage lower than the threshold voltage of an n-channel transistor whose channel region includes an oxide semiconductor is applied between a gate and a source of the transistor and a potential applied to a drain is higher than a potential applied to the gate. The evaluation of the gate current value can be simply performed compared to the case where the BT test is performed; for example, it takes short time to measure the gate current value. That is, reliability of a semiconductor device including the transistor can be easily evaluated.

Abstract: An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: A fault diagnostic circuit (100) and associated method of operation are described for testing an FET device (114) for a gate-drain short failure (113) by floating the FET gate during a predetermined test period and then comparing (118) the FET output voltage (115) at the source to a predetermined threshold voltage (VTHRESHOLD) which may be selected as a percentage of the power supply voltage (VPOWER) for the FET device to determine if the FET output voltage is greater than the threshold voltage, in which case a device fault is signaled (119).

Abstract: A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.

Abstract: A switching and fault detection circuit comprises two controllable switches capable of coupling a power source to a load. A controller can control the switches and test them for faults, and a voltage sensor can read the output voltage going to the load. Dual-redundant switches and fault detection circuitry can provide correct operation if one should fail. Control and feedback logic can determine if each of the solid-state switches is operating correctly during the power-on and power-off cycles and can also check for a fail-open condition during normal operations. If it is determined that a solid switch has failed open or closed, a fault can be generated.

Abstract: There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.

Abstract: A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.

Abstract: A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

Abstract: Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.

Abstract: Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point.

Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.

Abstract: Provided is an active non-contact probe card including a carrier, a support base, a piezoelectric material layer, an active sensor array chip and a control circuit. The support base is disposed on the carrier. The piezoelectric material layer is connected with the support base. The position of the active sensor array chip with respect to the carrier is determined according to the thicknesses of the support base and the thicknesses of the piezoelectric material layer. A control circuit provides a control voltage to the piezoelectric material layer to control the thickness of the piezoelectric material layer, so as to adjust the position of the active sensor array chip with respect to the carrier.

Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).

Abstract: The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).

Abstract: A method and system is provided for retrieving information about operational data from a plurality of building systems and service and maintenance information for a plurality of building sites. A customer web portal is provided with a database for storing the operational data and the service information allowing users to more readily generate reports and obtain service related information for a plurality of sites without having to maintain separate database systems at remote locations.