Abstract: A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an antiphase signal using a two-wire line. A control circuit is connected to one of the driver paths and controls the turn-on resistance of the power transistor circuit in this driver path such that the power transistor circuits in the two driver paths have the same turn-on resistance.

Abstract: A crosstalk inhibition unit which can inhibit crosstalk without causing an enlargement of a signal processing apparatus. A crosstalk inhibition unit 10 in order to inhibit crosstalk is provided to a signal processing apparatus. The crosstalk inhibition unit 10 is comprised of a contact terminal detection means 8 for detecting whether a contact terminal 7b of a signal cable 7 is inserted to an external terminal 5b of the signal processing apparatus and a first switching element 2 which operates differently depending on whether the contact terminal detection means 8 detects the contact terminal 7b. When the contact terminal detection means 8 does not detect the contact terminal 8, the first switching element 2 becomes conductive, and a signal line 15b is grounded. Thus, the cable 7 is not connected, and a signal line 15b, which is not used for signal processing is grounded. Accordingly, without particularly providing a grounded line, crosstalk between signal lines 15a, 16 and 19 can be inhibited.

Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: A driver including first and second buffers connected in parallel between a power source and a return path. In one configuration, the buffer outputs are commonly connected to an external coil and optionally a capacitive load. In another configuration, the buffers' outputs independently drive first and second external transistors. The external transistors are in series between a supply voltage source and its return path.

Abstract: A MOS-gated circuit, including a plurality of gated switches; and a driver circuit electrically coupled to the gated switches, the driver circuit configured to automatically prevent a simultaneous conduction of the gated switches if at least one of the gated switches is not capable of sustaining a reapplied voltage without conducting.

Abstract: Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages.

Abstract: It is intended to provide a terminal control device and a universal serial bus system capable of achieving stable system operation wherein the termination control device controls termination considering propagation delay time required for bus voltage level to shift to termination voltage when a universal serial bus system is terminated and an erroneous detection due to propagation delay time of voltage level shifting is avoided, accordingly. A pull-up start signal PU is inputted to a mask counter 11, timing operation is conducted in a manner of count operation. As a result of count operation, mask count signals MC are outputted to a comparator 13. Masking-time setting signals SC are inputted to the comparator 13. The mask count signals MC and the masking-time setting signals SC are compared to calculate a predetermined length of masking time that begins with start of pull-up. During this masking time, detection of SE0 state or bus-reset state is masked.

Abstract: The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.

Abstract: A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array of selectable capacitors coupled between a line driver and a pre-driver wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (MOSFET in the described embodiment) to a mirror device that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.

Abstract: A method for operating an output buffer for reducing a power/ground bounce noise while maintaining high transmission rate is disclosed. The method includes steps of providing a plurality of driving current paths to an output end of the output buffer when an output end of the output buffer is switched from a low level to a high level, turning off a portion of the driving current paths when the output end of the output buffer is kept at the high level, providing a plurality of discharging current paths to the output end when the output end of the output buffer is switched from a high level to a low level, and turning off a portion of the discharging current paths when the output end of the output buffer is kept at the low level. In addition, an output buffer with both low power/ground bounce noise and high transmission rate is also disclosed.

Abstract: A circuit for controlling driver strengths of a data and a data strobe in a semiconductor device comprising: a control signal generating unit which generates a first control signal in response to a first address code, generates a second control signal in response to a second address code, and generates a third control signal in response to a third address code; a data driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data in response to the second control signal, and finely adjusts the driver strength of the input data in response to the third control signal; and a data strobe driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data strobe in response to the second control signal, and finely adjusts the driver strength of the input data strobe in response to the third control signal.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. In an embodiment, rising and/or falling edge slopes are monitored. For example, a dV/dt may be monitored. The dV/dt can be monitored by coupling a capacitance to the output signal, generating a current with the capacitance, and generating a voltage from the current. The voltage is generally proportional to the dV/dt. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: A capacitor-coupling acceleration apparatus is an accelerating circuit capable of being applied to interconnect lines in an integrated circuit in order to reduce delay owing to parasitic resistance and capacitance of the interconnect lines in the integrated circuit. The apparatus can be disposed between the interconnect lines. When a signal transmitted on the interconnect line has a change from a low-level voltage to a high-level voltage, the apparatus detects the voltage level change of the signal and provides a charging loop to charge the interconnect line, thereby accelerating the change from the low-level voltage to the high-level voltage. When a signal on the interconnect line has a change from the high-level voltage to the low-level voltage, the apparatus detects the voltage level change of the signal and provides a discharging loop to discharge the interconnect line, thereby accelerating the change from the high-level voltage to the low-level voltage.

Abstract: To provide a semiconductor instrument for improving power added efficiency when a low power is outputted. In the semiconductor instrument in which a radio-frequency input signal (SRF) is supplied to input circuits of a plurality of transistors (1, 2), output circuits of the plurality of transistors (1, 2) are connected in parallel, and a radio-frequency output signal amplified with power is retrieved an amplifying operation of one part transistor (2) of the plurality of the transistors (1, 2) is turned off during a low-output operation.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or pre-determined, rate of voltage change.

Abstract: This invention provide a new and improved output circuit of a semiconductor integrated circuit device that enables output of a slew-rate waveform with a desired gradient without generating unwanted delay and also enables reduction in switching noise. According to this invention, an output circuit of a semiconductor integrated circuit device for controlling the gradient of an output waveform of a CMOS output transistor using first and second variable resistance units (transfer gates) controlled by a signal of an input part has another CMOS output circuit for delaying rise of a gate by dividing an output part and connecting first and second resistance units (NMOS transistor and PMOS transistor) to the gates.

Abstract: Systems and methods for enhancing slew control of output signals. An output driver receives an input signal and controllably increases the gain of that signal to provide a high quality output signal for use by an electronic device coupled thereto. The output driver includes an operational amplifier that maintains stability of the output signal through a feedback of the output signal. A control circuit supplies a signal to the output driver such that the driver to improve the shape of the output signal as the input signal is applied. After the operational amplifier regains control, the control circuit disengages. One embodiment of the present invention may be particularly useful as a USB output driver.

Abstract: The present invention provides apparatus and methods to eliminate a required “dead cycle” or “living cycle” during transfer of control from a first source terminated driver to a second source terminated driver on a bidirectional signaling conductor. On a last bus cycle on which the first driver drives the signaling conductor, the first driver stops driving and goes into a high impedance state respondent to detection that the first driver current has become lower than a predetermined current or that a voltage at the output of the first driver has become within a predetermined voltage difference of a target voltage. The second driver, knowing that the first driver will be switched to a high impedance state, can assume control of the signaling wire and drive a signal on the signaling conductor shortly after receipt of the signal from the first driver.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

Abstract: Disclosed is a semiconductor integrated circuit realizing improved operating speed, reduced power consumption in an active mode, reduced power consumption in a standby mode, and reduced area of a chip. A first logic gate using a first pair of potentials VDDL, VSSL having a relatively small potential difference as an operation power source and a second logic gate using a second pair of potentials VDDH, VSSH having a relatively large potential difference as an operation power source commonly use substrate potentials VBP, VBN of MIS transistors. The second logic gate has a relatively high driving capability, and the first logic gate can operate on relatively low power. The MIS transistor has a threshold voltage which increases by a reverse substrate bias and decreases by a forward substrate bias. By commonly using the substrate potential, even in the case where different substrate bias states are generated at both of the logic gates, MOS transistors of the logic gates can be formed in the common well region.

Abstract: The open-drain type output buffer includes a first driver and at east one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and pulls the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the first state when a transition from a steady high voltage output data to a low voltage output data is determined.

Abstract: Circuits that have programmable parallel on-chip termination impedance are provided. On-chip transistors provide parallel termination impedance to an I/O pin. The impedance of the on-chip transistors can be programmed by an impedance matching circuit in response to the value of external resistors. The impedance matching circuit can regulate the impedance of termination transistors that are coupled to numerous I/O pins on an integrated circuit. This technique eliminates the need for external resistors that provide parallel termination impedance to I/O pins.

Abstract: Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrate circuit to meet a variety of different high speed single-ended and differential I/O standards.

Abstract: A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

Abstract: The present invention discloses a high voltage tolerant output buffer, which is compatible with a 5-volt input signal on its output node while operating with a 3.3-volt power supply. The high voltage tolerant output buffer includes a NAND gate, a NOR gate, a pair of pull-up transistors, a pair of pull-down transistors, a pair of enable transistors, an inhibit transistor, and a substrate bias circuit. The present invention overcomes the problems due to the degradation of gate-oxide integrity reliability and reduces the fabrication cost by minimizing the chip size.

Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

Abstract: A bus interface having a first circuit based on a first pair of transistors of opposite types having a control electrode and a common electrode for providing a first output potential. A second circuit has a second pair of transistors of opposite types and having a common electrode for providing a second potential switching in opposite direction from the former. This device has a first capacitive coupling means for feeding a portion of the signal existing at said first potential back into said control electrode of said second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at said second potential back into said control electrodes of said first transistor pair. Thus variations between the rise and decay times of the transistors of each pair can be compensated for.

Abstract: A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude.

Abstract: An improved, open-loop push-pull driver is described. Closed-loop feedback loop techniques for control of the push-pull driver are described. These techniques are particularly well adapted to control shoot-through current in a push-pull driver circuit.

Abstract: According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

Abstract: The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement (10) is provided with a device (20) for detecting the time history of an output voltage that is output and supplied to a load (12) by means of the driver/s (90). The measured time values are converted into an output voltage value in a device (36) for converting the measured time history of the output voltage. Moreover, a device (40) for generating a reference voltage value is provided. The device (40) is connected to a device (60) for predetermining a desired slope time for the driver/s (90), whereby the slope time is essentially independent of external conditions.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: A method of providing a constant current drive to a driver circuit (40) in a compensating bias circuit (10) includes the steps of providing a constant current source insensitive to process, supply voltage, and temperature variations and mirroring the constant current source to the driver circuit while adding no sensitivity to process, supply voltage, and temperature variations.

Abstract: A high-potential side power device driving circuit has a clock signal generation circuit generating the so-called internal clock signal by outputting a pulse in a constant cycle for driving NMOS transistors and an iterative pulse generation circuit monitoring the state of an external input signal in synchronization with an output signal of the clock signal generation circuit, receiving a pulsing input signal generated with reference to a ground potential and generating pulsing ON and OFF signals. Thus provided is a level shifting circuit capable of preventing a power device from a malfunction also when a dv/dt transient signal is supplied with time difference.

Abstract: A device having a processor and a memory element positioned outside the processor, as well as a device for linking a memory element to a processor, and a memory element, are described, the processor and the memory element being linked via address and/or data lines, the address and/or data lines each being implemented in a structure combining a differential structure, LVDS in particular, and a structure having transistors which switch to ground and voltage, SSTL in particular, which has corresponding transmitters and receivers.

Abstract: A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.

Abstract: A output buffer circuit comprises a pull-up transistor, a boost transistor and a boost-controlling circuit. The pull-up transistor has a drain connected to a voltage source, a source connected to an I/O node and a gate connected to a data out through a voltage-boosting node. The boost transistor has a drain connected to the voltage source, and a source connected to the voltage-boosting node. The boost-controlling circuit has an input connected to the I/O node and an output connected to a gate of the boost transistor. The input of the boost-controlling circuit senses an excessive voltage at the I/O node and the output thereof turns on the boost transistor. Therefore, a gate voltage of the pull-up transistor is sustained to a predetermined high level when the pull-up transistor is turned off, and a voltage difference between the gate voltage and a source voltage of the pull-up transistor is reduced.

Abstract: An integrated circuit (100, 200, 300) includes a voltage-mode driver circuit having an analog on-chip termination and also having a substantially constant output impedance across an operating range of an output voltage of the voltage-mode driver circuit. The voltage-mode driver circuit also maintains a substantially constant output impedance through voltage transitions to minimize voltage reflections while driving cabling.

Abstract: A transmission system and method for transmission of digital data with impedance matching at the terminal ends reduces reflected signals due to impedance mismatch at the terminating ends and due to impedance transition areas in the transmission line. The transmission system includes a transmission line having a driver end connected to a driving circuit and a receiving end connected to a receiving circuit, each said end having an adjustable termination means connected thereto On the driver end of the transmission line said adjustable termination means is incorporated in the driving circuit, while on the receiver end of the transmission line said adjustable termination means is connected in parallel with the receiving circuit. Thus, both the reflections produced on the ends of a transmission line and the reflections resulting from discontinuities within a transmission line will be terminated.

Abstract: The invention is related to methods and apparatus for driving transistors. One embodiment includes a driver circuit that can drive power transistors at relatively high switching speeds, which can advantageously decrease the size of associated electronics systems that use the driver circuit and power transistors. Embodiments of the invention can drive a switching device that needs a negative voltage bias in order to be shut off. For example, the switching device can correspond to a junction field effect transistor (JFET). Advantageously, one embodiment of the invention can drive such switching devices on and off from a single positive voltage supply.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. A first embodiment of this invention provides a current mode signaling technique over transmission lines formed having a lower characteristic impedance than conventional CMOS transmission lines. The low impedance transmission lines of the present invention are more amenable to signal current interconnections over longer interconnection lines. An interconnection on an integrated circuit is described in which a first end of a transmission line is coupled to a driver. The transmission line is terminated at a second end with a low input impedance CMOS technology. In one embodiment, the low input impedance CMOS technology is a current sense amplifier which is input impedance matched to the transmission line. This minimizes reflections and ringing, cross talk and noise as well as allows for a very fast interconnection signal response.

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs.