Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: A circuit comprises an output terminal, an output driver for providing an output signal at the output terminal, a switching device for producing one or more connections of the output terminal to a respective fixed or variable potential, and a control device for controlling the switching device, the control device being designed to produce the connection or the connections in the event of a transition in the output signal from a first logic level to a second logic level and to disconnect it at the latest when the output signal attains the second level.

Abstract: An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current. The calibration circuit may be configured to generate the reference current based on a reference resistor coupled thereto. In particular, the calibration circuit may be configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor to generate the voltage at the replica of the variable impedance circuit.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

Abstract: A data output driver and a semiconductor memory device having the same are disclosed.

Abstract: A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a voltage value approximately near a threshold voltage of the control circuit. The pre-charge bias amount is slightly less than the amount needed to place the control circuit in a high current conduction state. A coupling circuit is thereafter used and adapted to couple an input voltage applied to the buffer circuit to the input of the control circuit. This causes the control circuit to enter the high current conduction state. Depending on the input impedance of the coupling circuit, by pre-charging the coupling circuit input, less time is needed to cause the coupling circuit to enter and thereafter leave a high current conduction state.

Abstract: Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG<GND) in active mode. Another embodiment provides a HOT-A high-VTH thick oxide SOI PFET header scheme. A further embodiment provides a HOT-A body biased high-VTH thick oxide SOI PFET header scheme.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: Providing a transmission circuit, which can transfer data normally with high speed even toward a host controller and a device, which does not meet design requirements defined in the standard, a data-transfer control device and electronic equipment. A current source coupled between a first source VDD and a node ND10; a first transistor SW1 formed between the node ND10 and a DP terminal; a second transistor SW2 formed between the node ND10 and a DM terminal; a first buffers outputting a first control signal HS_DPout 2 to the gate of the first transistor SW1; and a second buffer outputting a second control signal HS_DMout 2 to the gate of the second transistor SW2; are included. When any of the first control signal HS_DPout2 and the second control signal HS_Dmout 2 is set active, other of the control signals is set non-active. Each of the buffers includes a first inverter INV1 and a second inverter INV receiving an output from the first inverter INV1.

Abstract: An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

Abstract: There is provided a data acceleration device comprising a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: The semiconductor device according to the present invention comprises an output MOS transistor M0, an MOS transistor M3 connected between a gate G1 of the output MOS transistor M0 and a ground voltage GND, a parasitic transistor Tr1 which is formed in parallel with the MOS transistor M3 with the substrate terminal of the MOS transistor M3 as a base, and a parasitic transistor control circuit for controlling the conducting status of the parasitic transistor Tr1 based on the power supply voltage Vcc.

Abstract: The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.

Abstract: A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.

Abstract: The present invention relates to an apparatus for adjusting a slew rate of a data signal outputted by a signal from an external circuit in a semiconductor memory device and a method therefor. The apparatus includes: a slew rate control signal generation block for outputting a plurality of slew rate control signals through combining control codes inputted from the external circuit in response to a command signal; and a data buffer for adjusting a slew rate of a data signal inputted by using the slew rate control signals.

Abstract: A bus communication system contains a pair of communication conductors and a driver. The driver contains a plurality of pairs of controlled current source circuit, each pair comprising current source circuits of a first and second, mutually opposite polarity, and a control circuit for matching currents drawn by the current sources in each pair. The current source circuit of the first polarity have outputs coupled to a first one of the communication conductors, the current source circuits of the second polarity have outputs coupled to a second one of the communication conductors. A delay line is provided, with taps coupled to control inputs of the current sources of the first and second polarity, so that the pairs are switched on successively with mutual delays between successive pairs, as determined by the delay line.

Abstract: The open-drain type output buffer includes a first driver and at least one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and does not pull the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the first state when it has been determined that at least two consecutive high voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated.

Abstract: A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A diode, a NMOS device, and a PMOS device are used as regenerative devices in three examples. These three examples exhibit improved electrostatic discharge (ESD) tolerance.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of the driver transistor and ground. A first inverter stage is coupled to a common gate of the first transistor stack. The first inverter stage is further coupled between a high voltage source and ground. A second inverter stage is coupled to a common gate of the first inverter stage. The second inverter stage is further coupled between the high voltage source and ground. The circuit further includes a first transistor coupled between the high voltage source and gate of the driver transistor. The gate of the transistor is coupled to the first inverter stage.

Abstract: A high performance adaptive load output buffer with fast switching of capacitive loads includes a first set of series connected complementary cascode structures having a first output node at the junction of the cascode connected p-channel device, a second output node at the junction of the two cascode structures, and a third output node at the junction of the cascode connected n-channel device. The buffer also may include at least one second set of series connected complementary cascode structures having the control terminal of the p-channel cascode structure of the second set connected to the inverted output from the first output node of first complementary cascode structure. The control terminal of the n-channel cascode structure of the second set may be connected to the inverted output from the third output node of first complementary cascode structure. The common terminal of the second cascode structure may be connected to the second output node of first complementary cascode structure and the output pad.

Abstract: Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter, a source follower, and a current compensation circuit. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal using a biasing current. The current compensation circuit, responsive to a difference between the voltage levels of the input and output signals, varies an amount of the biasing current.

Abstract: Circuits, methods, and apparatus that provide accurate on-chip termination impedances for high-speed data interface circuits. One embodiment of the present invention provides a series termination impedance for an output driver as well as shunt termination impedances for a receive circuit. These impedances are dynamically adjusted to match a ratio of an external precision resistor. Multiple coarse and fine-grain adjustments are automatically performed by the hardware. Adjustment may occur at power up or at programmable periodic intervals, and one or both of the impedances may be updated each time an interface begins to transmit or receive data. A specific embodiment utilizes a reference resistance that is made up of a parallel combination of resistors connected through MOS transistors. This resistance is adjusted by connecting or disconnecting the parallel resistors until it matches a ratio of an external resistor.

Abstract: A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

Abstract: A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Abstract: There is provided a semiconductor integrated circuit device with a filer circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein the filter circuit includes: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of the input logic signals to delay the falling edge; and an output driver controlled by outputs of the first and second delay circuits to output delayed logic signals to an output node in response to the input logic signals.

Abstract: Various embodiments for differential output circuits with reduced transistor sizes and reduced DC currents provide efficient and flexible differential driver circuits. AC current boosting enables the switching transistors that drive the output nodes to be smaller in size. The AC current boost circuitry is shared by both switching current paths in the differential output circuit to reduce size and parasitic effects. Similarly, DC current circuitry is also shared by both switching current paths. The AC boost circuit and the DC bias circuit are made programmable to enable the output circuit to support multiple I/O standards with different specifications.

Abstract: The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.

Abstract: An anti-cross conduction driver control circuit and method prevent the occurrence of race conditions and avoid cross-conduction between series-connected power devices, typically MOSFETs, controlled in accordance with the present invention. Individual state machines are connected across the inputs and outputs of each power device driver, and are arranged to accurately determine when the driver has completed a task requested of it. Each state machine produces a “lockout” signal based on driver status, which is used to inhibit the operation of the opposite driver under prescribed conditions, and to thereby prevent cross-conduction between the series-connected power devices.

Abstract: Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more process-dependent current sources may be utilized to compensate for process variations by supplementing the current drive of transistors used to precharge (PMOS) or discharge (NMOS) an output node of a secondary (e.g., inverter) stage of the buffer circuit.

Abstract: To output a digital signal in particular according to the LVDS (low voltage differential signalling) standard, a driver stage is supplied with a constant current and thus supplies the digital signal in the form of a current signal with defined current values. As a result of line capacitances of a transmission line, because of the current limited according to the standard the edge steepness and hence the maximum transmittable bit rate can deteriorate. According to the invention, therefore, at least essentially in synchronization with a triggering of the driver stage, at least one current increase signal is generated which via a capacitor causes an additional current increase in the output current of the driver stage. Preferably, the current increase signal via the respective capacitor is switched directly to an output of the driver stage. By using a capacitor, with very little expenditure a limited current pulse can be switched in a temporally targeted manner on the switching processes of the driver stage.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: A noise elimination circuit sets a certain time period for eliminating noise occurring immediately after a change in the logic level of an input signal by a delay time of a first delay buffer. It also adjusts the timing of switching by delay times of second and third delay buffers. The noise elimination circuit thereby blocks the input signal for a certain period of time immediately after the change in the logic level of the input signal to keep a switching signal by a latch circuit or transmit only the same logic level as the input signal to an output.

Abstract: A low-power, high-performance inverter circuit comprises first and second inverter circuit portions. The first portion comprises a first inverter, including a first pull-up element and a first pull-down element, for inverting an input signal, a first switching element connected between the first pull-down element and ground for switching the first inverter, and a first diode connected between the first pull-down element and ground in parallel with the first switching element. The second portion comprises a second inverter, including a second pull-up element and a second pull-down element, for inverting an input signal, a second switching element connected between the second pull-up element and a supply voltage terminal for switching the second inverter, and a second diode connected between the second pull-up element and the supply voltage terminal in parallel with the second switching element. An output of the first portion is connected to an input of the second portion.

Abstract: A very low voltage swing is used to achieve very high data rates (up to 4 Gbps double data rate) at very low power consumption. A differential signaling approach is used for noise rejection, and a constant current approach also is used to minimize switching noise.

Abstract: An exemplary embodiment matches the input impedance of the receiving device to characteristic impedance, even with the receiving device composed with the MOS transistor, with a receiving device for data transfer with the differential-current driven model including: a receiving node to receive a differential current signal; a current-voltage conversion device to convert current into a voltage corresponding to differential current signal from the receiving node; an impedance matching device to match the input impedance to characteristic impedance, including a low impedance circuit device that enables generation of a low impedance which is lower than the characteristic impedance of a sending-side transmission line that is connected to the receiving node as an input impedance of the receiving node; and a comparator into which a differential-voltage signal from the current-voltage conversion device is input as a comparison signal, and which outputs the comparison result thereof as an output data.

Abstract: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Abstract: A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the buffer operating efficiency. The technique is implemented to allow for a reduction of power associated with the output buffer pre-driver stage. The methodology employs a power efficiency control circuit that tri-states the output buffer before every transition.

Abstract: The present invention provides a semiconductor device that can shorten the initialization cycle of impedance matching of interface buffers and reduce as much as possible affects on other circuits at the time of fine control thereafter. The semiconductor device (1) includes interface buffers (18a to 18c) whose internal impedances are controlled by impedance control data and an impedance control circuit (35) that generates the impedance control data. The impedance control circuit includes a first impedance control mode that initially generates the impedance control data by a binary search and comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffers, and a second impedance control mode that updates the impedance control data set in the interface buffers by a sequential comparison operation resulting from the predetermined impedance control steps.

Abstract: Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the drivers. A first transistor of the driver couples a first signal line of the bus to the driver current source and a second transistor of the driver couples a second signal line of the bus to the driver current source. Each transistor receives control signals in accordance with the operating mode of the driver. These control signals continuously and selectively couple the current source to the bus lines in a manner which provides uniform current distribution across the bus during all driver operating modes. The uniform current distribution across the bus minimizes interruptions in driver current dissipation and any effects from self-induced supply noise during signal transfers.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: The invention relates to bus type connection systems, in particular those for wiring backplanes of electronic systems, when the bus comprises connectors distributed in an irregular manner. It consists in selecting segments (D1, D2) over which the intervals (d1, d2) between the connectors are substantially constant. The structure of all the segments except one is then modified to make the effective impedance of the modified segments coincide with that of the unmodified segment. It produces a bus that is fully matched from end to end and able to operate at a very high frequency with a slight reduction of its propagation constant.

Abstract: An on-die termination circuit, which is coupled to a pad and included in a semiconductor memory device, for reducing an interference caused by a signal reflection phenomenon, includes a pull-up block coupled between an output node and a supply voltage; a pull-down block coupled between the output node and a ground; and a control block for receiving an ODT control signal to simultaneously activate the pull-up block and the pull-down block.

Abstract: Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuit 10 can be eliminated.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

Abstract: An impedance matching circuit has comparator, counter, two current sources, semiconductor resistance device, and variable MOS impedance device. The current sources are respectively coupled to an internal impedance device and an external impedance device. The comparator has two input terminals and an output terminal. The input terminals of the comparator are coupled to the internal and external impedance devices. The output terminal of the comparator is coupled to the counter. The variable MOS impedance device is coupled between the counter and the semiconductor impedance, and is controlled by the counter. When the voltages of the internal impedance and the external impedance are not matched, the variable MOS impedance device can provide the compensating impedance by adjusting the counting value of the counter.