Output Switching Noise Reduction Patents (Class 326/26)
  • Patent number: 10884969
    Abstract: Some embodiments include an apparatus including a first node to receive an input data signal including a first edge, and a second edge occurring after the first edge; a second node to receive a strobe signal including an edge; a first circuit to generate a modified strobe signal based on the strobe signal, the modified strobe signal including an edge occurring after the edge of the strobe signal; a second circuit to generate a modified data signal based on the input data signal, the modified data signal including an edge occurring after the second edge of the input data signal; and a third circuit to respond to the modified strobe signal and generate an output data signal based on the modified data signal.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Sanjay Joshi, Charlie Changhong Lin
  • Patent number: 10846018
    Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: MEDIATEK INC.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Shang-Pin Chen
  • Patent number: 10735001
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Patent number: 10666145
    Abstract: A single die driver integrated circuit is coupled to an input portion having a single inductor receiving a low voltage source and configured to drive a capacitive load with an output voltage. The driver includes a bidirectional synchronous power converter stage configured to generate a switching voltage from the input portion at a switching node and to generate a high voltage waveform from the low-voltage source. An embedded controller is configured to control a switch of the power converter stage.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 26, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: Simon Chaput, Gu-Yeon Wei
  • Patent number: 10614870
    Abstract: An electronic device includes a first circuit grouping including a first set of drivers, the first circuit grouping configured to generate a first set of output signals corresponding to a first slew rate; and s second circuit grouping including a second set of drivers, the second circuit grouping configured to generate a second set of output signals corresponding to a second slew rate, wherein the first set of drivers correspond to one or more physical characteristics different than the second set of drivers for introducing different slew rates.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Scott E. Smith
  • Patent number: 10608634
    Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 31, 2020
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Bruce Millar
  • Patent number: 10545888
    Abstract: A data inversion circuit in accordance with an embodiment may include a data input circuit and an inversion latch circuit. The data input circuit may output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data. The inversion latch circuit may generate the flag data by latching inversion data.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Yun Gi Hong
  • Patent number: 10511218
    Abstract: A gate drive circuit including a drive-on element that applies an on-state voltage to a gate of a drive target semiconductor element and a drive-off element that applies an off-state voltage to the gate is such that a recovery switch, a reactor, and a capacitor are connected in series between output terminals of the gate drive circuit as a recovery circuit that can recover a charge accumulated in input capacitance of the drive target semiconductor element when turning on, and the drive-on element, the drive-off element, and the recovery switch are controlled by a control circuit, whereby power consumption of the gate drive circuit is reduced.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ryota Kondo
  • Patent number: 10498339
    Abstract: Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 3, 2019
    Assignee: MEDIATEK INC.
    Inventors: Chien-Pang Lu, Yu-Tung Chang, Yu-Ming Yang
  • Patent number: 10396840
    Abstract: Described is an apparatus which comprises: a plurality of transmitter circuits on a first die; a plurality of receiver circuits on a second die; a plurality of data transmission lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits; a termination circuit comprising a shared capacitor and a plurality of resistors, each corresponding to one of the plurality of conductive lines and each coupled to the shared capacitor; and a parallel coding block to code data transmitted by the plurality of transmitter circuits via the plurality of data transmission lines according to a direct current (DC) balanced code.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 27, 2019
    Assignee: INTEL CORPORATION
    Inventor: Zuoguo Wu
  • Patent number: 10389349
    Abstract: A semiconductor apparatus may include a logic circuit and a power gating circuit including a gating transistor configured to apply a first supply voltage to the logic circuit based on an operation mode of the semiconductor apparatus. The semiconductor apparatus may be configured to monitor a characteristic of the logic circuit and adjust aback bias voltage to the gating transistor based on the characteristic of the logic circuit.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10366041
    Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Kuehlwein, Gregory King, Michael Stay
  • Patent number: 10360167
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 23, 2019
    Assignee: Dell Products L.P.
    Inventors: Wade Andrew Butcher, Sandor Farkas
  • Patent number: 10341165
    Abstract: A controller area network (CAN) transmitter includes an output stage circuit, a replica circuit of the output stage circuit configured to produce a replica signal, and a control amplifier configured to control a CANL output signal of the CAN transmitter in order to maintain the replica signal at a desired level.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 2, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Burkhard Gehring
  • Patent number: 10318465
    Abstract: A user station for a bus system and a method for reducing line-related emissions in a bus system as described. The user station includes a transmitter unit for sending a message to another user station of the bus system via the bus system, an exclusive, collision-free access of a user station to a bus of the bus system being at least temporarily provided, and a switching unit for switching off a current limiting function of the transmitter unit when an HF signal component on the message sent by the transmitter unit is detected and a method for measuring the interference immunity in the area of electromagnetic compatibility is carried out for the transmitter unit.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 11, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventors: Steffen Walker, Axel Pannwitz
  • Patent number: 10304521
    Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 28, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Chien Huang, Chia-Lung Ma, Tzu-Chia Huang
  • Patent number: 10277213
    Abstract: A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: NXP USA, Inc.
    Inventor: Paul Kimelman
  • Patent number: 10256817
    Abstract: A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 10187046
    Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10135432
    Abstract: Described examples include a controller having a first current source. The first current source has an output terminal coupled to a control terminal of a switch. A second current source has an output terminal coupled to the control terminal of the switch. The second current source provides current to the control terminal when the voltage on the control terminal is below a threshold. In accordance with another example, the switch is a field effect transistor. In another example, the first current source is driven by a charge pump. Methods are disclosed.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 20, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: K Ganapathi Shankar
  • Patent number: 10128862
    Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) including: a comparing module and a calibration circuit. The comparing module is arranged to generate a first comparison result by comparing an input voltage value of the SAR ADC with a first voltage value and a second result by comparing the input voltage value with a second voltage value; the calibration circuit coupled to the comparing module is for generating a determination result determining whether the input voltage value is in a range according to the first comparison result and the second comparison result, and enters a calibration mode according to the determination result.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventor: Chun-Cheng Liu
  • Patent number: 10122553
    Abstract: A transmission device may include a main driver configured to drive an output node based on an input signal, and may generate an output signal with multiple levels. The transmission device may include a variable emphasis driver configured to drive the output node with various driving forces based on transition information of the input signal.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: November 6, 2018
    Assignee: SK hynix Inc.
    Inventor: Hae Kang Jung
  • Patent number: 10116428
    Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 30, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Qiming Wu, Kai Lei, Fei Song, Kai Zhou, Gijung Ahn, Zhi Wu, Min-Kyu Kim
  • Patent number: 10090836
    Abstract: A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 10056902
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 21, 2018
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 10032494
    Abstract: A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 24, 2018
    Assignee: SK hynix Inc.
    Inventors: Sung Eun Lee, Jung Hyun Kwon, Jae Sun Lee, Jingzhe Xu
  • Patent number: 10027311
    Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Wataru Shiroi
  • Patent number: 10020059
    Abstract: A memory device includes an electrical line operably coupled to a plurality of memory cells, and a switchable impedance driver operably coupled to the electrical line. An electronic circuit includes a first driver having a first output impedance, and a second driver having a second output impedance that is less than the first output impedance. The first driver and the second driver are operably coupled in parallel to an output of the electronic circuit. The electronic circuit includes logic circuitry to enable the second driver during switching of a digital output of the driver. A method includes driving an output with both the first driver and the second driver when an input switches between logic levels, and disabling the second driver when the output reaches a desired logic level following the switch between logic levels of the input.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: July 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Muralikrishna Balaga, Vinayak Ghatawade, Aditya Pradhan
  • Patent number: 10014860
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 3, 2018
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 9978460
    Abstract: A memory module includes a first memory device including a first one-die termination circuit for impedance matching of a signal path and a second memory device sharing the signal path with the first memory device and including a second on-die termination circuit for impedance matching of the signal path, wherein the signal path corresponds to a command or address signal path provided from a host, and the first and second on-die termination circuits are individually controlled according to control of the host.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sukyong Kang, Hangi Jung, Hun-Dae Choi
  • Patent number: 9935626
    Abstract: A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 3, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventor: Aldo Davide Gariboldi
  • Patent number: 9935632
    Abstract: A semiconductor device includes a power management integrated circuit that supplies a periodic supply voltage signal. The semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes associated with a period of the periodic supply voltage signal. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 9935606
    Abstract: A system on chip (SoC) and a correction method of termination impedance element thereof are provided. The SoC includes a pad, a first termination impedance element, and a correction circuit. The pad is coupled to an external dynamic random access memory (DRAM) chip, where the DRAM chip includes a corrected termination impedance element. The first termination impedance element is coupled to the pad. The correction circuit is coupled to a control terminal of the first termination impedance element, to control an impedance value of the first termination impedance element. During an initialization period, the correction circuit corrects the impedance value of the first termination impedance element by using the impedance value of the corrected termination impedance element.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 3, 2018
    Assignee: ALi Corporation
    Inventor: Yu-Hsiang Lin
  • Patent number: 9928194
    Abstract: Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to the controller. The transmit driver, in response to the generated data for transmission, generates logic transitions on the serial bus. The transmit driver generates low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period. The transmit driver generates high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 27, 2018
    Assignee: Allegro Microsystems, LLC
    Inventors: Thomas Ross, Aldo Togneri, James McIntosh, Gianluca Allegrini
  • Patent number: 9871520
    Abstract: The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: January 16, 2018
    Assignee: XILINX, INC.
    Inventors: Chi M. Nguyen, Robert I. Fu
  • Patent number: 9871518
    Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Patent number: 9793708
    Abstract: Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 17, 2017
    Assignee: Integrated Device Technology, Inc.
    Inventors: Alan Wolfram Glaser, Tak Kwong Wong, Al Fang, Roland Thomas Knaack, Jon Roderick Williamson
  • Patent number: 9716497
    Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 25, 2017
    Assignee: SK hynix Inc.
    Inventors: Oung Sic Cho, Jong Hoon Oh
  • Patent number: 9684321
    Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 20, 2017
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Michael D. Bucher, Lei Luo, Chaofeng Charlie Huang, Amir Amirkhany, Huy M. Nguyen, Hsuan-Jung (Bruce) Su, John Wilson
  • Patent number: 9641175
    Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 2, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Hiroki Fujisawa
  • Patent number: 9620497
    Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Nathan D. Jack, JunJun Li, Souvick Mitra
  • Patent number: 9614497
    Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yuhei Kaneko, Kohei Nakamura
  • Patent number: 9601163
    Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Hyung Song, Kyoungsun Kim, Yong-Jin Kim, Jaejun Lee, Sangseok Kang, Jungjoon Lee
  • Patent number: 9571098
    Abstract: A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Ha Kim, Hwaseok Oh
  • Patent number: 9548654
    Abstract: Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jun Yi, Xuechun Ou
  • Patent number: 9531291
    Abstract: Described embodiments provide a transmission-line resistance compression network that includes an input port, a first output port coupled to a first load and a second output port coupled to a second load. The first and second loads may have substantially similar input impedances under substantially similar operating conditions. The transmission-line resistance compression network includes a transmission-line network coupled to the input port, the first output port and the second output port, and includes at least two transmission lines of different lengths. For a first operating range, the resistances at input ports of the first and second loads vary over first and second ratios, respectively. The resistance of the input impedance at the input port of the transmission-line resistance compression network varies over a third ratio that is smaller than at least one of the first and second ratios.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: December 27, 2016
    Assignee: Eta Devices, Inc.
    Inventor: David J. Perreault
  • Patent number: 9485854
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
  • Patent number: 9432018
    Abstract: A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Park, Su-Jin Kim, Jung-Hee Cho
  • Patent number: 9407263
    Abstract: A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 2, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander B. Hoefler, Hector Sanchez
  • Patent number: 9385722
    Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Amit R. Trivedi, Jaydeep P. Kulkarni, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz