Abstract: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while the second connection scheme specifies a second set of connections between the second node and a set of nodes in the array. The two nodes cannot connect to any nodes on the boundary of the array with any connection that is specified in any connection scheme.

Abstract: In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Abstract: Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract: A semiconductor integrated circuit includes a memory for holding data of a logic circuit inputs or outputs. The memory is composed of logic cells, and is placed in a logic region. Thus, the semiconductor integrated circuit can prevent forming wasted space, in which no circuit component is built, and reduce its area and power consumption. It can reduce the design period of the memory as compared with the case where hard macro cells are used.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: Fast logic sharing is created using a feedback path from the output logic macrocell of one functional block to the product term inputs of another function block without going through an advanced interconnect matrix (AIM). The fast feedback path may be provided from the macrocell after the product terms XOR gate without registering, and/or after the register in the macrocell. The fast logic sharing avoids the slow AIM for feedback logic, and allows additional resources to be borrowed from other function blocks with a limited delay penalty. In particular, delay penalties resulting from dividing wide operations requiring multiple product terms between the product terms of multiple functional blocks are significantly reduced.

Abstract: Some embodiments of the invention provide a configurable logic circuit. The logic circuits has inputs for receiving input data. It also has a first connecting circuit for receiving configuration data and at least a portion of the input data. Based at least partially on the received portion of the input data, the first connecting circuit selects configuration data sub-sets. The logic circuit also includes a second core-logic circuit for receiving configuration data sub-sets from the first connecting circuit and for providing the output data. At least two configuration data sub-sets configure the configurable logic circuit to perform at least two different functions on the input data to produce output data.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.

Abstract: The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.

Abstract: A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.

Abstract: A method of port numbering in an interconnect device includes loading a port configuration value from a memory device. One or more ports and subports are enabled according to the configuration value. Contiguous logical port numbers are assigned to the one or more ports and subports included in the interconnect device. A mapping request is received; and a mapped response associated with the mapping request is provided to an entity.

Abstract: Methods of implementing a static memory cell compliant with the requirements of phase shift masks. A phase shift compliant memory cell is generated by implementing a single bit line, two word lines, first and second cross-coupled logic gates, and first and second pass gates. The logic gates and pass gates include transistors that use a fabrication layer (e.g., polysilicon) to implement the gate nodes of the transistors. All of these gate nodes extend substantially in a first direction. Throughout the static memory cell, the fabrication layer is implemented without T-shaped polygons in compliance with the requirements for a phase shift mask. In some embodiments, the static memory cell is a configuration memory cell for a PLD, and the method includes implementing an interconnection between at least one of the first and second storage nodes and programmable logic elements of the PLD.

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.

Abstract: A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.

Abstract: Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.

Abstract: A programmable logic device includes a block random access memory (“BRAM”) that is split into two first in, first out (“FIFO”) memory arrays. Two sets of FIFO control logic and FIFO ports are associated with a single BRAM so that the BRAM can be operated as memory buffers for two independent FIFO memory systems.

Abstract: A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.

Abstract: A simplified implementation of molecular field programmable gate arrays described in U.S. Pat. No. 6,215,327 and U.S. Pat. No. 6,331,788, reducing the complexity in a tiled array template to that of a 1-input lookup table.

Abstract: A reconfigurable electronic device (100), e.g., a field programmable gate array (FPGA) or another type of complex programmable logic device (CPLD), has a first data storage device (120) and a second storage device (220) that are interconnected in a dual port memory mode of the reconfigurable electronic device (100). In this mode, the first data storage device (120) is accessible by a first decoder (140) both in a read as well as in a write mode, and the second data storage device (120) is accessible by a second decoder (140) in a read mode, thus providing an efficient dual port memory implementation. In a preferred embodiment, the first data storage device (120) is coupled to the second data storage device (220) via a configurable data copy circuit (160) that is responsive to a configuration signal provided via a configuration signal input (170), thus allowing for a very area efficient implementation of a dual port memory for reconfigurable electronic device (100).

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.

Abstract: A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

Abstract: A configuration control circuit (400) allows a PLD to be quickly re-configured to implement different functions without requiring any configuration memory cells. The control circuit (400) includes a first input (IN1) connected to a first hardwired configuration bit (HCB1), a second input (IN2) connected to a second hardwired configuration bit (HCB2), an output (OUT) connected to one or more of the PLD's configurable elements (110), and a select circuit (402) to selectively connect either the first input (IN1) or the second input (IN2) to the output (OUT) in response to a select signal (SEL).

Abstract: Latch circuitry is provided for programmable logic regions on integrated circuits such as programmable logic device integrated circuits. A programmable logic device may have programmable logic regions based on programmable combinational logic circuits. Latch circuitry in a logic region may be provided between an output of a programmable combinational logic circuit in the logic region and an output of the logic region. When the latch circuitry is enabled, the latch circuitry performs the functions of a level-sensitive latch. When the latch circuitry is disabled, the latch circuitry acts as a passive data path. The passive data path may include only a single driver so that the latch circuitry adds essentially zero additional delay to the data produced by the combinational logic.

Abstract: The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.

Abstract: Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

Abstract: A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method reduces die size and power consumption while increasing the performance of the logic device.

Abstract: Data is transferred on a field programmable gate array (FPGA) by (1) retrieving a first set of data from a first block RAM column of a configuration memory of the FPGA, (2) storing the first set of data retrieved from the first block RAM column in a frame data output register, (3) transferring the first set of data from the frame data output register directly to a frame data input register through a configuration bus of the FPGA, and (4) transferring the first set of data from the frame data input register to a second block RAM column of the configuration memory. The configuration bus is wide (e.g., 32-bits), thereby resulting in a high data transfer bandwidth.

Abstract: A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder receives a first subset of the six input signals, and in response, provides a first set of write select signals to the 64 write control circuits. A second write address decoder receives a second subset of the six input signals and a write clock signal, and in response, provides a plurality of decoded write clock signals to the sixty-four write control circuits. A write data value, which is applied to each of the write control circuits, is written to one of the memory cells in a synchronous manner with respect to the write clock signal in response to the first set of write select signals and the decoded write clock signals.

Abstract: Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the memory, which improves bandwidth. In an implementation, the memory architecture having one port supports pipelining, so reading from and writing to the memory can be accomplished in a one clock cycle and both Read and Write operation can occupy the full clock cycle at the same time on the same port. The pipelining architecture has relatively minimal circuit changes compared to a standard memory architecture which not supporting simultaneous-clock-cycle reads and writes, without requiring two or more ports.

Abstract: A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple independently stored optimized logic applications instantly. The alterable ASIC comprises programmable logic blocks and user configurable circuits. Either random access memory (RAM) configuration circuits or mask configured read only memory (ROM) configuration circuits are stacked in separate module layers above a single logic module layer. Each RAM or ROM layer implements one design application and global control signals provide user selection. Alterable ASIC dissever the effective die cost, requires one smaller package, occupies one site on the PC board and needs less board level wires. An extremely low cost solution for system designs is realized with an alterable ASIC.

Abstract: A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform arbitrary sequences of events. The RAM is used as a state table and output states are fed back to determine the next memory location. The number of locations in the RAM is reduced in comparison with prior art devices, which minimises power consumed by a microprocessor implementing such an FSM. This reduction in the number of locations is possible because only relevant inputs to the RAM are selected. The circuit has both synchronous and asynchronous implementations.

Abstract: A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. A set of 64 transmission gates is configured to receive the 64 four data values. A first input signal is applied to the set of 64 transmission gates, thereby routing 32 of the 64 data values. A set of 32 transmission gates is coupled to receive the 32 data values routed by the set of 64 transmission gates. A second input signal is applied to the set of 32 transmission gates, thereby routing 16 of the 32 data values. A 16:1 multiplexer receives the sixteen data values routed by the set of 32 transmission gates. Third, fourth, fifth and sixth input signals are applied to the 16:1 multiplexer, thereby routing one of the 16 data values as the output of the LUT.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A configurable logic block (“CLB”) in a programmable logic device (“PLD”), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a timing signal, such as an external clock signal, through the CLB to provide a selected delay. The timing signal is routed through selected fast or slow pins of look-up tables (“LUTs”) in the CLB. CLBs are widely available in the PLD, allowing many timing signals to be delayed, and can be configured to account for board-specific or component-specific delays.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as a sum-of-product, three memory words: mask word, product word and function word. The words of all product terms are ranged in a table, which characterize the logical behavior of the circuit. The invention provides the hardware structure of several new types of VSLI circuits, having re-configurable logic behaviors. A first embodiment implements any type of multiple output combinational circuit, a second embodiment implements any synchronous sequential circuit with only clock input and, a third embodiment implements any synchronous sequential circuit s with data inputs and clock input.

Abstract: A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.

Abstract: Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract: Pre-configuration of a programmable device permits implementation and operation of the device using a first, dedicated operation usable upon power up of the programmable device without the need for programming the device using external configuration data. Configuration data can be provided in any suitable manner to re-configure the device to perform a second, programmable operation. The pre-configured design preferably uses programmable resources and leaves dedicated resources undisturbed during both first and second operations.

Abstract: Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

Abstract: A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory arranged between the functional elements and the higher-level unit; and a control unit configured to move at least one position pointer to a configuration memory location in response to at least one event reported by a functional element. At run time, a configuration word in the configuration memory pointed to by at least one of the position pointers is transferred to the functional element in order to perform reconfiguration without the configuration word being managed by a central logic.

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.