Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block.

Abstract: A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

Abstract: Circuits and methods of implementing flip-flops in dual-output lookup tables (LUTs). A flip-flop is implemented by programming a dual-output LUT to include a first function implementing a master latch and a second function implementing a slave latch. An output of the master latch is provided at a first output terminal of the LUT, and an output of the slave latch is provided at a second output terminal of the LUT. The output of the master latch (the first output of the LUT) is coupled to a first input terminal of the LUT, where it drives both the first and second functions. The output of the slave latch (the second output of the LUT) is coupled to a second input terminal of the LUT, where it drives the second function. A clock signal is provided to both first and second functions via a third input terminal of the LUT.

Abstract: Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

Abstract: Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks and corresponding input/output pins, and a plurality of configuration memory cells. The configuration memory cells are adapted to store configuration data for configuration of the logic blocks and the input/output blocks. A data port is adapted to provide a clock signal to and receive configuration data from an external memory. A plurality of circuits are adapted to hold the input/output pins in a known logic state during the configuration.

Abstract: Programmable integrated circuits (ICs) that compensate for process variations and/or mask revisions in a programmable integrated circuit (IC). An exemplary IC includes two programming ports, two programmable circuits (e.g., digital and analog), a non-volatile memory, and a configuration control circuit coupled to the programmable circuits and non-volatile memory. In some embodiments, one port can be used for storing data in the non-volatile memory, while the other port can be used for providing a configuration bitstream to the configuration control circuit. The non-volatile memory can be used to store a value that identifies a process corner and/or mask revision for the programmable IC. The configuration control circuit monitors data arriving in the configuration bitstream, and selectively either ignores the data or uses the data to configure the IC (e.g., the analog circuit), based on a comparison of a code key in the bitstream with the value stored in the non-volatile memory.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table. A load logic input line associated with a lookup table having limited input lines is used to augment the number of input lines that can be handled by a particular lookup table. Load logic and a lookup table having four input lines can be used to implement a 3:1 multiplexer having five input lines.

Abstract: A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tn-1 and the input variables of the switching device form a time point tn. Elements are provided in order to control the output variables in a clocked manner and to store the output variables of the switching device between the time points tn-1 and tn.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior depending on the construction.

Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A multiplexer can be implemented in a programmable logic device, using addition elements which are optimised for performing a one-bit addition function. A logic device receives a first data input value and a first select input. The logic device then routes the first data input to the addition element as a first input one-bit value, and routes either the first data input or its inverse to the addition element as a second input one-bit value, depending on the value of the first select input.

Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

Abstract: A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).

Abstract: A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2N.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract: The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.

Abstract: An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.

Abstract: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

Abstract: The present invention provides a LUT circuit that can simultaneously determine the corresponding output values of a plurality of input values. The LUT circuit of the present invention includes a plurality of comparators, a plurality of selecting circuits and at least one table stored in a memory. This table is used to record the values of dependent variables of a certain function. A plurality of input values (Xn) are sent to the LUT circuit at the same time. The selecting circuits generates select signals based on the received input values. Then, the select signals are sent to the comparators for letting the comparators output the corresponding output values.

Abstract: Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the same row. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by a set of wire segments that traverse through a set of the IC's wiring layers, and a set of vias when multiple wiring layers are involved. Some of the direct connections may have intervening circuits (e.g. buffer circuits). In some embodiments, the nodes in the array are all similar to each other.

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of the sets are user multiplexers. Each particular user multiplexer has input and output terminals and has a set of select terminals for receiving a set of user-design signals that directs the particular multiplexer to connect a set of the input terminals to a set of the output terminals. The user-design signals are signals generated internally by the IC.

Abstract: A programmable logic block for an asynchronous circuit design is disclosed. After a programmable setup, the logic block not only has the processing function of common devices, but also communicates using the asynchronous protocol so as to design an asynchronous device.

Abstract: Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.

Abstract: Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.

Abstract: A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.

Abstract: A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a plurality of signals into a serial signal stream and couples the serial signal stream to a conductor for distribution to a plurality of destinations in the IC. There is a receiver unit at each of the plurality of destinations and connected to the conductor. Each receiver unit extracts one of the plurality of signals from the serial signal stream received on the conductor. The transmitter unit comprises a multiplexer circuit and a counter circuit and time multiplexes the plurality of signals to form a serial signal stream, wherein a signal is selected for a time slot based on a count value of the counter circuit. The counter signal is also supplied to each receiver unit, which uses the counter signal to determine when to latch a signal from the serial signal stream.

Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and tasks associated with each transition. An execution block iteratively (in loops) transitions between the states according to the FSM representation, performing various operations according to the specified tasks in the transitions. In an embodiment, each state is associated with utmost one file providing inputs to the application. Such an approach provides an explicit control flow and easier way to develop and manage an application.

Abstract: A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is provided by the configurable logic block, such that invalid data received from the configurable logic block is replaced with programmable insertion data prior to transmission, while valid data is allowed to be transmitted without replacement. Also, data received by Input/Output (I/O) portions of the dedicated protocol generation unit are compared to programmable data patterns. After a positive comparison, matching data is either truncated and not delivered to the configurable logic block, or the matching data is delivered to the configurable logic block with appropriate data valid signaling.

Abstract: Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

Abstract: An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

Abstract: A PLD having logic blocks capable of performing addition with a constant and non-constant value where the constant value is provided directly to an adder, without first passing it through a look up table. The PLD includes a plurality of logic blocks arranged in a two dimensional array. Row and column interconnects are provided to interconnect the plurality of logic blocks arranged in the two dimensional array. The plurality of logic blocks each include a look up table configurable to perform combinational logic and an adder circuit configured to perform adding functions. Each logic block also includes circuitry configured to directly provide a constant value to the adder circuit without passing the constant value through the look up table. The look up table is therefore available to perform other logic functions that would otherwise have to performed elsewhere on the chip.

Abstract: The present invention relates to electronic integrated circuits (ICs) that retain identical functionality with better performance or lower power dissipation under RAM and hard-wire ROM fabrication options, without the need to alter transistor layout within the IC. An integrated circuit (IC) comprising: a plurality of transistors; and a first selectable fabrication option comprised of a user configurable memory circuit; and a second selectable fabrication option comprised of a hard-wired circuit in lieu of said user configurable memory circuit; wherein, the IC functionality and performance is determined by the configuration memory data in the first fabrication option, and wherein the identical configuration is hard-wired in the second fabrication option without altering the location of transistors within the IC. Such a programmable to hard-wire conversion provides a significant IC cost reduction, performance improvement and power dissipation reduction at minimal NRE cost and improved reliability.

Abstract: A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.