With Flip-flop Or Sequential Device Patents (Class 326/40)
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Patent number: 7631211Abstract: Circuits, methods, and apparatus are directed to sharing input and output functionality. A timing circuit usable for input and output functionality may be combined with another timing circuit to provide additional input/output functionality or to reduce the number of circuit elements for input/output functionality. For example, two timing circuits may be used to provide double data-rate input while still providing output functionality, or vice versa. Two timing circuits may also provide output that is timed and gated with an output enable signal.Type: GrantFiled: June 27, 2006Date of Patent: December 8, 2009Assignee: Altera CorporationInventor: Kevin W. Mai
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Patent number: 7629812Abstract: A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.Type: GrantFiled: August 3, 2007Date of Patent: December 8, 2009Assignee: DSM Solutions, Inc.Inventors: Damodar R. Thummalapally, Abhijit Ray
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Patent number: 7622948Abstract: A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The programmable devices may further include a chip select signal that is also connected in a daisy chain. Special instructions embedded in the configuration bitstream, which may be stored in the external memory, are used by the programmable devices to control the configuration process.Type: GrantFiled: June 9, 2008Date of Patent: November 24, 2009Assignee: Xilinx, Inc.Inventor: Wayne Edward Wennekamp
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Patent number: 7622975Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.Type: GrantFiled: July 10, 2007Date of Patent: November 24, 2009Assignee: QUALCOMM IncorporatedInventors: Fad Ad Hamdan, Anthony D. Klein
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Patent number: 7622961Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.Type: GrantFiled: September 23, 2005Date of Patent: November 24, 2009Assignee: Intel CorporationInventors: Edward Grochowski, Chris Wilkerson, Shih-Lien L. Lu, Murali Annavaram
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Patent number: 7619441Abstract: An apparatus for interconnecting stacked dice on a programmable integrated circuit is described. In one example, an integrated circuit die comprises a programmable integrated circuit that includes first and second interface tiles. The first interface tile is in electrical communication with a first array of pins on the integrated circuit die, and the second interface tile is in electrical communication with a second array of pins on the integrated circuit die. At least one dedicated routing resource is formed on the integrated circuit die between the first interface tile and the second interface tile. The at least one dedicated routing resource is configured to couple at least one pin of the first array of pins to at least one pin of the second array of pins.Type: GrantFiled: March 3, 2008Date of Patent: November 17, 2009Assignee: XILINX, Inc.Inventors: Arifur Rahman, Bernard J. New
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Publication number: 20090278566Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Inventors: David Lewis, David Cashman
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Patent number: 7609085Abstract: Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a two-input multiplexer. The second IMUX is also configured as a two-input multiplexer. The LUT is also configured as a third two-input multiplexer. An output of the first IMUX is connected to the first input of the LUT, an output of the second IMUX is connected to the second input of the LUT. A third input of the LUT accepts a selection bit.Type: GrantFiled: March 8, 2006Date of Patent: October 27, 2009Assignee: Tabula, Inc.Inventors: Herman Schmit, Andrew Caldwell, Steven Teig
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Patent number: 7602534Abstract: A CPU and an image memory are provided in a printing apparatus. An interface circuit device for inputting/outputting signals representing image data is interposed between the CPU and the image memory. The interface circuit device constitutes of a plurality of SSTL circuits. One of two adjoining pixels in image data is changed into a non-inverted pixel, and the other is changed into an inverted pixel. In the SSTL circuits, to which inputted is a signal representing the one pixel, an input signal is inputted so as not to invert an input signal. In the SSTL circuits, to which inputted is a signal representing the other pixel as an inverted element, an input signal is inputted to the inverted element so as to invert an input signal. This suppresses an increase in cost and an increase in the size of a device, while reducing the current in impedance matching.Type: GrantFiled: August 1, 2006Date of Patent: October 13, 2009Assignee: Dainippon Screen Mfg. Co., Ltd.Inventor: Keiichi Tanii
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Patent number: 7603599Abstract: Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S? is first provided close to node S that generates signal patterns to route through a path N? to load L. When it is impractical to test a network path N from source to load L, a load L? is further provided close to load L that receives the signal patterns from a routing path N? provided from source S. The paths N? and N? overlap to cover all the routing resources of the path N.Type: GrantFiled: June 3, 2005Date of Patent: October 13, 2009Assignee: Xilinx, Inc.Inventors: Matthieu P. H. Cossoul, Madabhushi V. R. Chari
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Patent number: 7598769Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.Type: GrantFiled: February 15, 2007Date of Patent: October 6, 2009Assignee: Altera CorporationInventor: Vincent Leung
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Patent number: 7592834Abstract: In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.Type: GrantFiled: June 30, 2008Date of Patent: September 22, 2009Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao
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Patent number: 7589556Abstract: Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.Type: GrantFiled: October 26, 2007Date of Patent: September 15, 2009Assignee: Altera CorporationInventors: Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Joseph Huang, Michael H. M. Chu, Chiakang Sung
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Patent number: 7589651Abstract: A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used in each receiver and each transmitter in each serial interface on the PLD. Alternatively, time division multiplexing can be used to allow the receiver and transmitter in each receiver/transmitter pair, or even multiple receiver/transmitter pairs, to share a single ADC. When none of the receiver/transmitter pairs associated with a particular ADC is being used, the ADC can be accessed for use simply as an ADC.Type: GrantFiled: August 25, 2006Date of Patent: September 15, 2009Assignee: Altera CorporationInventors: Sergey Shumarayev, Rakesh H. Patel, Wilson Wong
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Patent number: 7586327Abstract: A logic module for a structured ASIC is mask-programmable to perform any of a plurality of logic functions or to alternatively function as two static random access memory (“SRAM”) cells. Most or all of the circuitry needed to enable the logic module to function as SRAM cells is circuitry that is available for use in logic mode configuration of the module. Similarly, most or all of the logic circuitry of the logic module is put to use to provide the SRAM cells when the module is configured in SRAM mode. The circuitry of the logic module is therefore used very efficiently, whether the module is configured for logic mode or SRAM mode.Type: GrantFiled: March 25, 2008Date of Patent: September 8, 2009Assignee: Altera CorporationInventors: Kok Heng Choe, Kar Keng Chua
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Patent number: 7587537Abstract: Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.Type: GrantFiled: November 30, 2007Date of Patent: September 8, 2009Assignee: Altera CorporationInventor: Ali Burney
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Publication number: 20090219051Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.Type: ApplicationFiled: April 19, 2007Publication date: September 3, 2009Inventors: Wei Zhang, Niraj K. Jha, Li Shang
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Patent number: 7584447Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: August 12, 2005Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
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Patent number: 7579865Abstract: In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.Type: GrantFiled: August 5, 2008Date of Patent: August 25, 2009Assignee: Lattice Semiconductor CorporationInventors: David L. Rutledge, Wei Han, Yoshita Yerramilli
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Patent number: 7576562Abstract: A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.Type: GrantFiled: June 15, 2007Date of Patent: August 18, 2009Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: Sterling Whitaker, Lowell Miles, Jody Gambles, Gary K. Maki
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Patent number: 7576561Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises storing instructions in the device; selecting between one of the instructions stored in the device and an instruction coupled to an input/output port of the device; coupling the instruction to a non-volatile memory; and reading a configuration bitstream from the non-volatile memory based upon the selected instruction. A method of enabling a multi-boot configuration of a device having programmable logic is disclosed. The method comprises powering up the device using a first configuration bitstream from a first type of configuration device in response to a first command; receiving a reboot command; and reconfiguring the device using a second configuration bitstream from a second type of configuration device in response to a second command which is different than the first command. Circuits enabling a multi-boot configuration of a device having programmable logic are also disclosed.Type: GrantFiled: November 13, 2007Date of Patent: August 18, 2009Assignee: Xilinx, Inc.Inventor: Jinsong Huang
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Patent number: 7573295Abstract: A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.Type: GrantFiled: May 14, 2007Date of Patent: August 11, 2009Assignee: XILINX, Inc.Inventor: Laurent F. Stadler
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Patent number: 7573292Abstract: A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.Type: GrantFiled: February 15, 2008Date of Patent: August 11, 2009Assignee: XILINX, Inc.Inventor: Vi Chi Chan
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Patent number: 7570076Abstract: A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328). Each transistor has a control terminal (314, 316, 318) and a current path coupled between the output terminal and a respective circuit element of the plurality of circuit elements. A control circuit (300) has a plurality of output terminals (314, 316, 318). Each output terminal is coupled to the control terminal of a respective transistor of the plurality of transistors. The control circuit produces control signals at respective output terminals to selectively turn off at least one transistor and turn on at least other transistors of the plurality of transistors at a first time.Type: GrantFiled: October 13, 2004Date of Patent: August 4, 2009Assignee: Texas Instruments IncorporatedInventors: Andrew Marshall, Karan Singh Bhatia
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Patent number: 7570120Abstract: A multichannel numerically controlled oscillator is provided. The multichannel numerically controlled oscillator has a dual port memory. An output function generation lookup table in the dual port memory is used to generate output functions for the numerically controlled oscillator. A first channel of output is generated based on a first address signal that is presented on a first port of the dual port memory. A second channel of output is generated based on a second address signal that is presented on a second port of the dual port memory. First and second phase accumulators may be used to produce the address signals for the first and second ports of the dual port memory, respectively. The phase accumulators may each contain a register, an adder, and a feedback path. The registers in the phase accumulators and the dual port memory may handle signals at the clock rate of the output channels.Type: GrantFiled: June 18, 2007Date of Patent: August 4, 2009Assignee: Altera CorporationInventor: Benjamin Esposito
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Publication number: 20090189634Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.Type: ApplicationFiled: January 12, 2009Publication date: July 30, 2009Inventors: Sana Rezgui, John McCollum, Jih-Jong Wang
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Publication number: 20090174429Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.Type: ApplicationFiled: January 7, 2008Publication date: July 9, 2009Applicant: UNITY SEMICONDUCTOR CORPORATIONInventor: Robert Norman
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Patent number: 7557604Abstract: An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.Type: GrantFiled: May 3, 2005Date of Patent: July 7, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Shinsuke Onishi, Tsuguto Maruko
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Publication number: 20090167348Abstract: A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.Type: ApplicationFiled: January 16, 2008Publication date: July 2, 2009Inventor: Nij DORAIRAJ
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Publication number: 20090167349Abstract: A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE.Type: ApplicationFiled: May 12, 2008Publication date: July 2, 2009Inventors: Raminda Madurawe, Nij Dorairaj
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Publication number: 20090167347Abstract: A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Inventor: NIJ DORAIRAJ
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Publication number: 20090167350Abstract: Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.Type: ApplicationFiled: May 12, 2008Publication date: July 2, 2009Inventors: Raminda Madurawe, Nij Dorairaj
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Patent number: 7551002Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.Type: GrantFiled: January 15, 2008Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Paul Gary Reuland, Brian Andrew Schuelke
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Patent number: 7550324Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.Type: GrantFiled: November 15, 2007Date of Patent: June 23, 2009Assignee: Xilinx, Inc.Inventors: James A. Walstrum, Jr., Steven E. McNeil, Shalin Umesh Sheth
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Patent number: 7548095Abstract: An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are disposed in the p-type semiconductor region. First and second p-wells are respectively disposed in the first and second deep n-wells. First and second segments of Flash memory are disposed in the in first and second p-wells. N-type regions are disposed in each deep n-well between the outer boundary of the p-wells and the outer boundary of the deep n-wells.Type: GrantFiled: January 30, 2008Date of Patent: June 16, 2009Assignee: Actel CorporationInventors: Zhigang Wang, Fethi Dhaoui, Santosh Yachareni
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Patent number: 7548091Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.Type: GrantFiled: July 29, 2005Date of Patent: June 16, 2009Assignee: Altera CorporationInventor: Lin-Shih Liu
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Publication number: 20090146686Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.Type: ApplicationFiled: September 8, 2008Publication date: June 11, 2009Inventors: Martin Voogel, Jason Redgrave, Trevis Chandler
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Patent number: 7545167Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurably routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.Type: GrantFiled: January 28, 2008Date of Patent: June 9, 2009Assignee: Tabula, Inc.Inventors: Steven Teig, Herman Schmit, Jason Redgrave, Vikas Chandra
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Patent number: 7545168Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.Type: GrantFiled: April 18, 2008Date of Patent: June 9, 2009Assignee: Actel CorporationInventor: Arunangshu Kundu
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Patent number: 7538579Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: December 1, 2006Date of Patent: May 26, 2009Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
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Patent number: 7538576Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.Type: GrantFiled: September 20, 2007Date of Patent: May 26, 2009Assignee: Actel CorporationInventors: John McCollum, Gregory Bakker, Jonathan Greene
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Patent number: 7538577Abstract: A mechanism within an electronic system for adapting a field programmable gate array (FPGA) to a flash memory device that supports a synchronous serial peripheral interface (SPI) by coupling a small amount of MSI logic with the FPGA and the flash memory device, to configure the FPGA to a designed configuration state. The system comprises a first and additional FPGAs that support a serial configuration interface, SPI flash memory, and a parallel-load 8-bit shift register. SPI flash memory is initialized with a first configuration data pattern that is read from SPI flash memory and applied to the FPGAs during a first device configuration process resulting in the FPGAs each attaining a designed configuration state. The SPI flash memory is subsequently initialized with a second configuration data pattern by means of the first FPGA. Each FPGA attains another distinct designed configuration state by a second device configuration process.Type: GrantFiled: June 29, 2005Date of Patent: May 26, 2009Inventor: Thomas Bollinger
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Patent number: 7538574Abstract: In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.Type: GrantFiled: December 5, 2005Date of Patent: May 26, 2009Assignee: Lattice Semiconductor CorporationInventors: Howard Tang, Jack T. Wong, Clark Wilkinson, Jeffrey S. Byrne
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Patent number: 7535253Abstract: Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.Type: GrantFiled: November 15, 2007Date of Patent: May 19, 2009Assignee: Lattice Semiconductor CorporationInventors: Howard Tang, Roger Spinti, San-Ta Kow, Ju Shen
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Patent number: 7532032Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.Type: GrantFiled: August 28, 2006Date of Patent: May 12, 2009Assignee: Tabula, Inc.Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
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Patent number: 7525344Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: GrantFiled: May 27, 2007Date of Patent: April 28, 2009Assignee: Tabula, Inc.Inventors: Steven Teig, Herman Schmit, Jason Redgrave
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Patent number: 7525343Abstract: A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least one internal register of a hardware block in a PLD. The PLD is actively reconfigured with a first partial bitstream to sever first connections between input/output (IO) pins of the hardware block and a user design, and establish second connections between the IO pins and state access logic. The at least one internal register is accessed using the state access logic. The PLD is actively reconfigured with a second partial bitstream to establish third connections between the IO pins and the user design.Type: GrantFiled: December 20, 2007Date of Patent: April 28, 2009Assignee: Xilinx, Inc.Inventors: Stephen A. Neuendorffer, Brandon J. Blodget
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Patent number: 7525340Abstract: A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.Type: GrantFiled: September 19, 2005Date of Patent: April 28, 2009Assignee: Altera CorporationInventors: Sergey Y Shumarayev, Rakesh H Patel, Chong H Lee
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Patent number: 7518400Abstract: Some embodiments provide a barrel shifter on a configurable integrated circuit (IC). The barrel shifter has a first set of tiles and a second set of tiles with configurable circuits. The barrel shifter also has a first set of non-neighboring offset connections (NNOCs) connecting at least one of the tiles in the first set to at least one of the tiles in the second set.Type: GrantFiled: March 8, 2006Date of Patent: April 14, 2009Assignee: Tabula, Inc.Inventors: Jason Redgrave, Herman Schmit
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Patent number: RE40894Abstract: A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.Type: GrantFiled: June 5, 2003Date of Patent: September 1, 2009Assignee: Altera CorporationInventors: Rakesh H. Patel, Kevin A. Norman