Abstract: A circuit for enabling an IC having a normal mode for performing normal functions and a program mode for programming settings of the IC to use same pins in both modes. The circuit includes an input circuit for receiving the input data; internal circuits for processing the input data in the normal mode; a program circuit for processing the input data in the program mode, a program enable circuit for providing a program enable signal for switching the IC from the normal to the program mode; and a demultiplexer circuit for providing the input data as normal data to internal circuits when the IC is in the normal mode and as program data to the program circuit when the IC is in the program mode.

Abstract: An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.

Abstract: According to one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the configuration data of the bitstream into a first type of code word; encoding a set of more-prevalent data words within the configuration data into a second type of codeword; and identifying in the compressed bitstream at least some of the data words that are members of the set of more-prevalent data words.

Abstract: A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in state of the data node. The integrated circuit also includes a reset transistor, coupled to the data node, that resets the data node to a first state in response to a transition in a timing signal, an input transistor, coupled to the data node, that asserts the data node to a second state in response to receipt of a data signal, and reset logic coupled between the output node and the data node. The first reset logic resets the output node to an original state in response to resetting of the data node if the output node achieves a set state. The integrated circuit further includes feedback logic coupled between the output node and a reset input node of the reset logic that limits a duration of operation of the reset logic.

Abstract: A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control.

Abstract: An integrated circuit device such as a PLD is divided into a plurality of logic blocks, each including one or more resources of the device. The device includes a plurality of switch elements and a number of signal isolation circuits. The switch elements selectively disable corresponding logic blocks to reduce power consumption, and the signal isolation circuits selectively isolates corresponding logic blocks to prevent the transmission of invalid data from disabled logic blocks to enabled logic blocks.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

Abstract: A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

Abstract: A semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element, wherein reading the generated signal protects data stored at the storage element from a read condition disturbance.

Abstract: A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic (4) are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (4). The interconnection circuit (5) connects the output lines or the external input lines of memory for logic (4) in the preceding stage and the input lines of memory for logic (4) of the succeeding stage between two memories for logic (4), according to the information for connection memorized in memory for interconnections (6). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed.

Abstract: Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable logic device, wherein a plurality of outputs from logic blocks is coupled to a plurality of inputs to logic blocks by a single wire segment comprising a programmable time multiplexing method. A second aspect is a software placement and route tool, wherein a plurality of routs is assigned to a single route, wherein the plurality of routs is routed in the single route by a time multiplexed method. A third aspect is a critical signal propagation path in a programmable logic device comprising global non-overlapping control signals and time multiplexed wires, wherein each control signal assigns a programmable time slot for multiple signals within one of said wires, further comprising one or more critical signals assigned to the last multiplexed time slot.

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract: A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a configurable logic block; and a reset signal coupled to the block of memory elements, the reset signal enabling partial reconfiguration of the memory cells of the configurable logic block. Each the memory cell may be coupled to receive the reset signal enabling the partial reconfiguration of the block of memory cells of the configurable logic block. The reset signal may comprise a plurality of signals, wherein each signal of the plurality of signals is coupled to a memory cell of the block of memory cells. Each memory cell may also receive a signal for setting an initial state. A method of enabling partial reconfiguration of memory cells of a look-up table of a programmable logic device is also described.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: A programmable logic device may comprise a plurality of programmable resources and non-volatile configuration memory to store configuration data by which to configure the programmable resources. Test override circuitry may determine a test mode and selectively override the configuration data stored in the non-volatile configuration memory during the test mode for configuring the programmable resources based at least in part on test configuration data other than the configuration data stored in the non-volatile memory. A buffer may be operable to drive a configuration select node for at least one of the programmable resources for designating a configuration therefore based on the configuration data of the non-volatile memory. The test override circuitry may comprise a pull-down circuit operable, when enabled dependent on the test configuration data, to drive the buffer with a high/low level capable of overriding a state of the non-volatile configuration memory.

Abstract: Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

Abstract: A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A one input non-volatile-memory-transistor based lookup table is coupled to each of the n data inputs of the multiplexer. The multiplexer has X inputs wherein n=2X as is known in the art. A sense amplifier is coupled to the output of the multiplexer.

Abstract: Some embodiments of the invention provide a configurable logic circuit. The logic circuits has inputs for receiving input data. It also has a first connecting circuit for receiving configuration data and at least a portion of the input data. Based at least partially on the received portion of the input data, the first connecting circuit selects configuration data sub-sets. The logic circuit also includes a second core-logic circuit for receiving configuration data sub-sets from the first connecting circuit and for providing the output data. At least two configuration data sub-sets configure the configurable logic circuit to perform at least two different functions on the input data to produce output data.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This “soft-wired” set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of the reconfigurable device. Additionally, the set of boundary scan registers only exists when a testing configuration is loaded into the reconfigurable device. When testing is complete, the testing configuration is erased and the functional blocks may implement other operations. Thus, the set of boundary scan registers consumes no additional chip area. Furthermore, as the set of boundary scan registers disappears after testing, a functional path enabling normal operation modes is unnecessary. Therefore, manually created functional test data is not needed. Instead, ATPG software can create test data from hardware descriptions of the IP core and the set of boundary scan registers.

Abstract: A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

Abstract: A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

Abstract: A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (20). The control logic comprises a plurality of logic elements (26, 28, 30, 32) arranged to generate a first set of two-input logic functions (f, (a, b)) and a programmable inverter (36) arranged to generate a second set of two-input logic functions, the second set of two-input logic functions being the complement functions of the first set of two-input logic functions. SRAM memory cells (4 bit memory batch (38)) may be used for configuration purposes, realising a compact logic module or block that is also re-programmable.

Abstract: A logic basic cell for processing a first and a second data signal, having a multiplex device for multiplexing the first and second data signals in a multiplex operating state, having a logic device for forming a logic combination of the first and second data signals in accordance with a selectable logic function in a logic function operating state, it being possible to provide, as an output signal, one of the first and second data signals during the multiplex operating state and the logic combination of the first and second data signals in accordance with the selected logic function during the logic function operating state. The logic basic cell contains a control unit, which predetermines, based on a control signal, the logic basic cell operates in the multiplex operating state or in the logic function operating state.

Abstract: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

Abstract: A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.

Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.

Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

Abstract: Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.

Abstract: The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.

Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts, and a customized layer provided over the common wiring layer to form the user circuit. In the semiconductor integrated circuit apparatus, a functional cell constituting a sequential circuit such as a flip-flop and a functional cell constituting a combinational circuit are placed in matrix of column and row. Further, the functional cell constituting the sequential circuit is placed obliquely in the matrix.

Abstract: In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

Abstract: A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The programmable devices may further include a chip select signal that is also connected in a daisy chain. Special instructions embedded in the configuration bitstream, which may be stored in the external memory, are used by the programmable devices to control the configuration process.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Abstract: For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control circuit of the data retention cell. The data signal furnished to a master latch unit of the data retention cell is controlled to switch between an input data signal and the output data signal by the input control circuit in response to a retention signal. The switching of the data signal for refreshing the master latch unit is delayed by a delay unit of the input control circuit, which functions to make sure that the data-preserving process is properly operated on any transition from the power-saving mode to a power-active mode.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.